JPS6296731U - - Google Patents
Info
- Publication number
- JPS6296731U JPS6296731U JP1985186862U JP18686285U JPS6296731U JP S6296731 U JPS6296731 U JP S6296731U JP 1985186862 U JP1985186862 U JP 1985186862U JP 18686285 U JP18686285 U JP 18686285U JP S6296731 U JPS6296731 U JP S6296731U
- Authority
- JP
- Japan
- Prior art keywords
- time
- computer
- memory
- clock signal
- signal sent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004397 blinking Effects 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Digital Computer Display Output (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
はこの考案の要部接続図であり、１はデイスプレ
イ部、２はキーボード、３は電源入、切スイツチ
、４は経過時間表示部分、５は時間設定器、６は
パルス発生器、７は計算機、９はメモリ、１０は
減算回路、１１はフリツカ信号発生器、１２はＡ
ＮＤ回路、１３はビデオ信号生成回路、１５はＣ
ＲＴである。なお、図中同一あるいは相当部分に
は同一符号を付して示してある。
Figure 1 is a diagram showing an embodiment of this invention, and Figure 2 is a connection diagram of the main parts of this invention, where 1 is a display section, 2 is a keyboard, 3 is a power on/off switch, and 4 is an elapsed time display. 5 is a time setter, 6 is a pulse generator, 7 is a calculator, 9 is a memory, 10 is a subtraction circuit, 11 is a flicker signal generator, 12 is an A
ND circuit, 13 is a video signal generation circuit, 15 is C
It is RT. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.
Claims (1)
計算機につながる周辺・端末装置において、電源
スイツチを「入」にした時の計算機から送られる
時計信号による時刻を記憶するメモリと、電源ス
イツチを「入」にしたあとの経過時間を計算機か
ら送られる時計信号による現在時刻から上記メモ
リに記憶してある使用開始時の時刻を差引くこと
によつて求める減算回路と、上記減算回路の出力
である経過時間を上記デイスプレイ部の所定位置
に表示せしめる手段と、前記経過時間が予め設定
してある時間と等しくなつた時デイスプレイ部に
表示してある時間を点滅させる手段とを備えたこ
とを特徴とする周辺・端末装置。 A peripheral/terminal device that is equipped with a display unit and a keyboard and is connected to the main computer has a memory that stores the time based on the clock signal sent from the computer when the power switch is turned on, and a memory that stores the time based on the clock signal sent from the computer when the power switch is turned on. A subtraction circuit calculates the elapsed time by subtracting the time at the start of use stored in the memory from the current time according to the clock signal sent from the computer, and the elapsed time is the output of the subtraction circuit. The surrounding area is characterized by comprising means for displaying the time on the display section at a predetermined position, and means for blinking the time displayed on the display section when the elapsed time becomes equal to a preset time. Terminal device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985186862U JPS6296731U (en) | 1985-12-04 | 1985-12-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985186862U JPS6296731U (en) | 1985-12-04 | 1985-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6296731U true JPS6296731U (en) | 1987-06-20 |
Family
ID=31136807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985186862U Pending JPS6296731U (en) | 1985-12-04 | 1985-12-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6296731U (en) |
-
1985
- 1985-12-04 JP JP1985186862U patent/JPS6296731U/ja active Pending