CN220962186U - Power management control circuit - Google Patents

Abstract

The utility model discloses a power management control circuit, which realizes transient voltage pull-up and steady voltage pull-down at a VDC pin of a power management chip by arranging a capacitor charging and discharging circuit, further forms low-voltage states with different durations at a PWRON pin of the power management chip by triggering duration of a tact switch, realizes association of different voltage states and power management response events by combining a main control module, and realizes various power management events such as power-on startup, key startup, shutdown, standby and the like by a low-cost circuit.

Description

Power management control circuit

Technical Field

The utility model relates to the field of power supply management control, in particular to a power supply management control circuit.

Background

Embedded electronic devices permeate into the aspects of daily work and life. Based on comprehensive consideration of power consumption, consumer use habit and actual application scene, the on-off control requirement on equipment is strong and quite different, such as power-on start-up, key time on-off, standby, wake-up and other operation control.

With the increasing popularity of Power management integrated chips (PMIC, power MANAGEMENT IC), power management for electronic devices has actually been converted into control of PMIC.

In the prior art, in order to realize multiple on-off control, an ASIC control circuit or even a single-chip microcomputer is often used to form a level state signal required by PMIC control, so that the complexity and the cost of the circuit are high, and the method is not suitable for embedded electronic equipment.

Disclosure of utility model

In view of the above, in order to solve the problem of higher cost of the power management chip control scheme in the prior art, the utility model provides a power management control circuit, which combines the functions of a PMIC, and realizes the control of the PMIC by using a simple circuit so as to realize the power management of the whole equipment.

In order to solve the above problems, in the power management control circuit of the present utility model, the power management control circuit includes a first control circuit and a power management chip, an output end of the first control circuit is connected to a VDC pin of the power management chip, and a capacitor charging branch and a capacitor discharging branch are disposed in the first control circuit, so that the VDC pin can be pulled up to a high level after an external power supply is powered up, and pulled down to a low level after the capacitor is charged.

Specifically, the capacitor charging branch circuit comprises a first capacitor, a first resistor and a second resistor, wherein the first end of the first capacitor is connected with the output end of the first control circuit on one hand, and is grounded through the first resistor on the other hand; the second end of the first capacitor is connected with a power supply input end through a second resistor, and the power supply input end is connected with the external power supply.

The capacitor discharging branch circuit comprises a first capacitor and a third resistor, and the second end of the first capacitor is grounded through the third resistor.

Further, the power control management circuit further comprises a second control circuit, and the output end of the second control circuit is connected with a PWRON pin of the power management chip; the second control circuit comprises a tact switch, and the second control circuit can form low-voltage states with different duration at the PWRON pin according to the pressing duration of the tact switch.

The first end of the tact switch is grounded, the second end of the tact switch is connected with the output end of the second control circuit and the first end of the second capacitor through a fourth resistor, and the second end of the second capacitor is grounded; and a pull-up resistor is integrated in a PWRON pin of the power management chip.

Further, the power management control circuit further comprises a main control module, the main control module is connected with the power management chip, the power management chip monitors the voltage change states of the VDC pin and the PWRON pin and sends the voltage change states to the main control module, and the main control module sends event execution instructions to the power management chip according to preset voltage change states and event response relations.

Compared with the prior art, the utility model has the following advantages:

The power management control circuit realizes the transient voltage pull-up and steady voltage pull-down at the VDC pin of the power management chip by arranging the capacitor charging and discharging circuit, forms low-voltage states with different durations at the PWRON pin of the power management chip by touching the key trigger duration of the switch, further realizes the association of different voltage states and power management response events by combining the main control module, and realizes various power management events such as power-on startup, key startup, shutdown, standby and the like by a low-cost circuit.

Drawings

FIG. 1 is a schematic diagram of a power management control circuit according to the present utility model.

Detailed Description

The utility model will be further illustrated with reference to examples.

The first, second, third, fourth, etc. in the present utility model are not limited to the priority and order of the components or terminals, but are used only to distinguish different components and terminals.

As shown in fig. 1, the power management control circuit in the present utility model includes a first control circuit, a second control circuit and a power management chip PMIC, wherein an output end of the first control circuit is connected with a VDC pin of the power management chip PMIC, and an output end of the second control circuit is connected with a PWRON pin of the power management chip PMIC; the first control circuit comprises a first capacitor C1, wherein a first end of the first capacitor C1 is connected with the output end of the first control circuit on one hand and grounded through a first resistor R1 on the other hand; the second end of the first capacitor C1 is connected with a power supply input end VDD through a second resistor R2, the power supply input end VDD is connected with an external power supply, and the second end of the first capacitor C1 is grounded through a third resistor R3; the second resistor R2, the first capacitor C1 and the first resistor R1 form a charging branch of the first capacitor C1; the first capacitor C1 and the third resistor R3 form a discharge branch of the first capacitor C1; the second control circuit comprises a tact switch K1, a first end of the tact switch K1 is grounded, a second end of the tact switch K1 is connected with the output end of the second control circuit and the first end of a second capacitor C2 through a fourth resistor R4, and the second end of the second capacitor C2 is grounded; the pull-up resistor R5 is integrated inside the PWRON pin inside the power management chip PMIC.

When an external power supply supplies power, a power supply input end VDD of the first control circuit is connected with direct current, a charging branch of the first capacitor C1 is conducted, the first capacitor C1 is charged, at the moment, the voltage at the VDC pin is the voltage at two ends of the first resistor R1, at the moment, the voltage at the VDC pin is pulled up, a power management chip PMIC can monitor the rising voltage, when the charging of the capacitor is finished, the charging branch of the first capacitor is disconnected, at the moment, the voltage at the VDC pin is pulled down, and the default state is recovered; then, the first capacitor discharges through the third resistor, and when the input end VDD to be supplied is disconnected from the dc power supply and is re-connected with the dc power again, the charging branch of the first capacitor can be charged again.

When the switch key is in an OFF state, the voltage at the PWRON pin is a high level V, and when the switch key is switched to an ON state, a branch formed by the fourth resistor R4 and the internal pull-up resistor R5 is turned ON, the voltage at the PWRON pin is reduced to a low level, and the duration of the low level is determined by the duration of the pressing of the light touch switch K1, so that different power management requirements can be set according to the duration of the low voltage of the PWRON pin.

The power management control circuit further comprises a main control module (not shown), the main control module is connected with the power management chip, the power management chip monitors voltage change states of the VDC pin and the PWRON pin and sends the voltage change states to the main control module, and the main control module sends event execution instructions to the power management chip according to preset voltage change states and event response relations.

By adopting the power management control circuit, different power management events can be set by combining the voltage change states of the VDC pin and the PWRON pin and software, so that the power supply management of each functional module is realized. As an implementation, as with the basic design logic of a common power management chip PMIC, the VCCA pin and VCCIO pin of the power management chip PMIC are externally powered; the main control module can adopt System On Chip (SOC), MOSI, CLK, PWRCTRL pins and the like are connected with the SOC to receive an execution instruction sent by the SOC; INT sends the voltage change state of the VDC pin and the PWRON pin to the SOC, and EXT_EN sends an enable signal to other external DC-DC units according to the instruction. The correspondence between the voltage change state and the power management event may be set according to specific situations, for example: the VDC pin is monitored to rise in voltage, and the voltage rising corresponds to a power-on starting event; setting the PWRON pin maintain low voltage 2s as a standby event; setting the PWRON pin maintain low voltage for 5s as a shutdown event; setting the PWRON pin to a wake state with the PWRON pin maintained low voltage 1 s; the PWRON pin maintains the low voltage 3s to be set as a reset event, when the voltages of the VDC pin and the PWRON pin change, the power management chip PMIC sends the state information to the SOC through the INT pin, the SOC judges the corresponding response event, and then sends the corresponding execution instruction to the power management chip PMIC through the MOSI pin and the like, and the power management chip PMIC executes specific power management corresponding to the event.

The preferred embodiments of the present utility model have been described in detail above, but the present utility model is not limited to the specific details of the above embodiments, and various equivalent changes can be made to the technical solution of the present utility model within the scope of the technical concept of the present utility model, and all the equivalent changes belong to the protection scope of the present utility model.

Claims (6)

1. The power management control circuit is characterized by comprising a first control circuit and a power management chip, wherein the output end of the first control circuit is connected with a VDC pin of the power management chip, and a capacitor charging branch and a capacitor discharging branch are arranged in the first control circuit, so that the VDC pin can be pulled up to a high level after an external power supply is electrified and pulled down to a low level after the capacitor is charged.

2. The power management control circuit of claim 1 wherein the capacitor charging branch comprises a first capacitor, a first resistor and a second resistor, a first end of the first capacitor being connected to the output of the first control circuit on the one hand and to ground through the first resistor on the other hand; the second end of the first capacitor is connected with a power supply input end through a second resistor, and the power supply input end is connected with the external power supply.

3. The power management control circuit of claim 2 wherein the capacitive discharge branch comprises a first capacitor and a third resistor, the second end of the first capacitor being grounded through the third resistor.

4. A power management control circuit according to claim 1 or 3, further comprising a second control circuit, an output of the second control circuit being connected to a PWRON pin of the power management chip; the second control circuit comprises a tact switch, and the second control circuit can form low-voltage states with different duration at the PWRON pin according to the pressing duration of the tact switch.

5. The power management control circuit of claim 4 wherein the first terminal of the tact switch is grounded and the second terminal is connected to the output terminal of the second control circuit and the first terminal of the second capacitor through a fourth resistor, the second terminal of the second capacitor being grounded; and a pull-up resistor is integrated in a PWRON pin of the power management chip.

6. The power management control circuit of claim 4, further comprising a master control module, wherein the master control module is connected to the power management chip, wherein the power management chip monitors voltage change states of the VDC pin and the PWRON pin and sends the voltage change states to the master control module, and wherein the master control module sends an event execution instruction to the power management chip according to a preset voltage change state and event response relationship.