CN213518246U - Structure for controlling power-on time sequence of PCIE board card - Google Patents
Structure for controlling power-on time sequence of PCIE board card Download PDFInfo
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- CN213518246U CN213518246U CN202023080966.0U CN202023080966U CN213518246U CN 213518246 U CN213518246 U CN 213518246U CN 202023080966 U CN202023080966 U CN 202023080966U CN 213518246 U CN213518246 U CN 213518246U
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 59
- 239000003990 capacitor Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- PXUQTDZNOHRWLI-OXUVVOBNSA-O malvidin 3-O-beta-D-glucoside Chemical compound COC1=C(O)C(OC)=CC(C=2C(=CC=3C(O)=CC(O)=CC=3[O+]=2)O[C@H]2[C@@H]([C@@H](O)[C@H](O)[C@@H](CO)O2)O)=C1 PXUQTDZNOHRWLI-OXUVVOBNSA-O 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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Abstract
The utility model discloses a structure for controlling power-on time sequence of a PCIE board card, which comprises a golden finger, wherein a 3.3V pin of the golden finger is electrically connected with an RTC circuit through a diode; the 3.3V pin of the golden finger is electrically connected with the delay circuit; the 12V pin of the golden finger is electrically connected with the first DC-DC conversion module; the delay circuit is electrically connected with an enabling port of the first DC-DC conversion module; the first DC-DC conversion module is electrically connected with the second DC-DC conversion module. The 3.3V pin of the golden finger directly supplies power to the RTC circuit through a diode, the 3.3V pin of the golden finger provides an enabling signal for the first DC-DC conversion module through the delay circuit, and the enabling signal has certain delay compared with 3.3V, so that the RTC circuit is ensured to be powered on preferentially; the delay circuit is packaged by SC70, so that the delay circuit occupies a smaller PCIE board card space, and more space is provided for the design of the PCIE board card.
Description
Technical Field
The utility model relates to a PCIE power-on design field especially relates to a structure of power-on time sequence on control PCIE integrated circuit board.
Background
With the continuous improvement of PCIE technology, more and more PCIE products are integrated with a CPU to realize more functions. Since the PCIE standard has a certain requirement on the size of the board, particularly after the CPU is integrated, the peripheral circuit space is smaller.
Currently, many PCIE products use an RTC circuit, and some PCIE products have a requirement on a power-on timing of the RTC circuit, and usually require that a part of the RTC circuit is powered on first. In the prior art, many PCIE products use a button cell as a power supply cell of the RTC circuit, and since the button cell is always charged, whenever other power sources power on the button cell, the RTC circuit can be ensured to be earlier than other power sources, and the power-on timing sequence requirement of the PCIE product is satisfied. In the prior art, a high-power MOS delay switch is added to a circuit for supplying power to a non-RTC circuit by a power supply of a PCIE product, so that the non-RTC circuit is powered on behind the RTC circuit by the turn-on delay of the MOS delay switch. However, the problem existing in the prior art is that no matter button cells or MOS delay switches are used, the PCIE board occupies a large area, and the design space of the PCIE board product is small.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problems, the present invention provides a structure for controlling the power-on sequence of a PCIE board card, which comprises a golden finger,
the 3.3V pin of the golden finger is electrically connected with the RTC circuit through a diode;
the 3.3V pin of the golden finger is electrically connected with the delay circuit;
the 12V pin of the golden finger is electrically connected with the first DC-DC conversion module;
the delay circuit is electrically connected with an enabling port of the first DC-DC conversion module;
the first DC-DC conversion module is electrically connected with the second DC-DC conversion module.
Furthermore, the delay circuit adopts an ADM1086 delay chip, and the ADM1086 delay chip is packaged by SC 70.
Furthermore, the 3.3V pin of the gold finger is electrically connected to two first voltage dividing resistors, the Vin port of the ADM1086 delay chip is electrically connected between the two first voltage dividing resistors, the Vcc port and the ENin port of the ADM1086 delay chip are electrically connected to the 3.3V pin of the gold finger, the GND port of the ADM1086 delay chip is grounded, the CEXT port of the ADM1086 delay chip is connected to a grounded capacitor, and the ENout port of the ADM1086 delay chip is electrically connected to the enable port of the first DC-DC conversion module.
Further, the capacitance value of the capacitor
Wherein T isTime delayIs the required delay time.
Furthermore, the first DC-DC conversion module is a voltage regulator converting 12V to 3.3V, an output terminal of the first DC-DC conversion module is electrically connected to two second voltage dividing resistors, an output terminal of the first DC-DC conversion module is electrically connected to an input terminal of the second DC-DC conversion module, and an enable port of the second DC-DC conversion module is connected between the two second voltage dividing resistors.
The structure for controlling the power-on time sequence of the PCIE board card provided by the application has the following beneficial effects:
according to the structure for controlling the power-on time sequence of the PCIE board card, power is supplied through the power pin of the golden finger, a button battery and related accessories are not required to be installed, the cost can be effectively reduced, and the space of the PCIE board card is saved; the 3.3V pin of the golden finger directly supplies power to the RTC circuit through a diode, the 3.3V pin of the golden finger provides an enabling signal for the first DC-DC conversion module through the delay circuit, and the enabling signal has certain delay compared with 3.3V, so that the RTC circuit is ensured to be powered on preferentially; the delay circuit is packaged by SC70, so that the delay circuit occupies a smaller PCIE board card space, and more space is provided for the design of the PCIE board card. The first DC-DC conversion module is electrically connected with a second DC-DC conversion module, and the second DC-DC conversion module supplies power when the output voltage of the first DC-DC conversion module enables the second DC-DC conversion module through a second voltage dividing resistor. Therefore, the power-on time sequence of the PCIE product device is effectively controlled.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of controlling a power-on timing sequence of a PCIE board in an embodiment of the present invention;
fig. 2 is a schematic diagram of a connection between a delay circuit and a first DC-DC conversion module according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a connection between a first DC-DC conversion module and a second DC-DC conversion module according to an embodiment of the present invention.
Reference numerals and meanings in the drawings:
1. the device comprises a golden finger, 2, a diode, 3, an RTC circuit, 4, a delay circuit, 5, a first DC-DC conversion module, 6 and a second DC-DC conversion module.
The purpose of the present invention is to provide a novel and improved method and apparatus for operating a computer.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. The present invention is explained in detail with reference to the accompanying drawings, wherein fig. 1 is a schematic structural diagram for controlling a power-on timing sequence of a PCIE board in an embodiment of the present invention; fig. 2 is a schematic diagram of a connection between a delay circuit and a first DC-DC conversion module according to an embodiment of the present invention; fig. 3 is a schematic diagram of a connection between a first DC-DC conversion module and a second DC-DC conversion module according to an embodiment of the present invention.
Referring to fig. 1, the utility model provides a structure of electric chronogenesis on control PCIE integrated circuit board, including golden finger 1, wherein, a pin, No. two pins, No. three pins of golden finger A face of general PCIE integrated circuit board are 12V pins, and No. eight pins are 3.3V pins, and No. ten pins are 3.3V spare pins. No. two pins and No. three pins of the side B of the golden finger are 12V pins, and No. nine pins and No. ten pins are 3.3V power supplies.
Any 3.3V pin of the golden finger 1 is electrically connected with an RTC circuit 3 through a diode 2; the 3.3V pin of the golden finger 1 directly supplies power to the RTC circuit 3 through the diode 2. The RTC circuit is a real-time clock circuit.
The 3.3V pin of the golden finger 1 is electrically connected with the delay circuit 4; in a specific implementation process, the delay circuit 4 may adopt an ADM1086 delay chip, and the ADM1086 delay chip is packaged by using SC 70.
Referring to fig. 2, the 3.3V pin of the gold finger 1 is electrically connected to two first voltage dividing resistors R1 and R2, the first voltage dividing resistor R1 and the first voltage dividing resistor R2 are connected in series to ground, the Vin port of the ADM1086 delay chip is electrically connected between the first voltage dividing resistor R1 and the first voltage dividing resistor R2, the Vcc port and the ENin port of the ADM1086 delay chip are electrically connected to the 3.3V pin of the gold finger 1, the GND port of the ADM1086 delay chip is connected to ground, the CEXT port of the ADM1086 delay chip is connected to a grounded capacitor, and in a specific implementation, a capacitance value of the capacitor is connected to a grounded capacitor
Wherein T isTime delayIs the required delay time.
The 12V pin of the golden finger 1 is electrically connected with the voltage input end of the first DC-DC conversion module 5; the delay circuit 4 is electrically connected to an enable port of the first DC-DC conversion module 5; specifically, the ENout port of the ADM1086 delay chip is electrically connected to the enable port of the first DC-DC conversion module 5. The first DC-DC conversion module 5 is a voltage regulator converting 12V to 3.3V. The output end of the first DC-DC conversion module 5 is electrically connected to the filter capacitor.
The first DC-DC conversion module 5 is electrically connected to the second DC-DC conversion module 6. Referring to fig. 3, the output terminal of the first DC-DC conversion module 5 is electrically connected to two second voltage dividing resistors, specifically, the output terminal of the first DC-DC conversion module 5 is electrically connected to the second voltage dividing resistor R3 and the second voltage dividing resistor R4 which are connected in series, the second voltage dividing resistor R4 is grounded, the output terminal of the first DC-DC conversion module 5 is electrically connected to the input of the second DC-DC conversion module 6, and the enable port of the second DC-DC conversion module 6 is connected between the second voltage dividing resistor R3 and the second voltage dividing resistor R4. And the output end of the second DC-DC conversion module 6 is electrically connected with a filter capacitor.
According to the structure for controlling the power-on time sequence of the PCIE board card, power is supplied through the power pin of the golden finger 1, a button battery and related accessories are not required to be installed, the cost can be effectively reduced, and the space of the PCIE board card is saved; the 3.3V pin of the gold finger 1 directly supplies power to the RTC circuit 3 through the diode 2, and the 3.3V pin of the gold finger 1 provides an enable signal for the first DC-DC conversion module 5 through the delay circuit 4, so that the enable signal has a certain delay time compared with 3.3V, thereby ensuring that the RTC circuit 3 is powered on preferentially; the delay circuit 4 is packaged by adopting SC70, so that the delay circuit occupies a smaller PCIE board space, and provides more space for the design of PCIE boards. The first DC-DC conversion module 5 is connected to a second DC-DC conversion module 6, and the second DC-DC conversion module 6 supplies power when the output voltage of the first DC-DC conversion module 5 enables the second DC-DC conversion module 6 through a second voltage dividing resistor, by the second DC-DC conversion module 6. Therefore, the power-on time sequence of the PCIE product device is effectively controlled.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (5)
1. A structure for controlling the power-on time sequence of a PCIE board card is characterized by comprising a golden finger (1), wherein,
the 3.3V pin of the golden finger (1) is electrically connected with the RTC circuit (3) through the diode (2);
the 3.3V pin of the golden finger (1) is electrically connected with the delay circuit (4);
the 12V pin of the golden finger (1) is electrically connected with the first DC-DC conversion module (5);
the delay circuit (4) is electrically connected with an enabling port of the first DC-DC conversion module (5);
the first DC-DC conversion module (5) is electrically connected with the second DC-DC conversion module (6).
2. The structure for controlling the power-on timing sequence of a PCIE board according to claim 1, wherein the delay circuit (4) employs an ADM1086 delay chip, and the ADM1086 delay chip is packaged by using SC 70.
3. The structure for controlling power-on timing of a PCIE card according to claim 2, wherein a 3.3V pin of the gold finger (1) is electrically connected to two first voltage-dividing resistors, a Vin port of the ADM1086 delay chip is electrically connected between the two first voltage-dividing resistors, a Vcc port and an ENin port of the ADM1086 delay chip are electrically connected to the 3.3V pin of the gold finger (1), a GND port of the ADM1086 delay chip is grounded, a CEXT port of the ADM1086 delay chip is connected to a grounded capacitor, and an ENout port of the ADM1086 delay chip is electrically connected to an enable port of the first DC-DC conversion module (5).
4. The structure for controlling the power-on timing sequence of a PCIE card of claim 3, wherein a capacitance value of the capacitor
Wherein T isTime delayIs the required delay time.
5. The structure for controlling the power-on sequence of a PCIE board according to claim 1, wherein the first DC-DC conversion module (5) is a voltage regulator that converts 12V to 3.3V, an output end of the first DC-DC conversion module (5) is electrically connected to two second voltage-dividing resistors, an output end of the first DC-DC conversion module (5) is electrically connected to an input of the second DC-DC conversion module (6), and an enable port of the second DC-DC conversion module (6) is connected between the two second voltage-dividing resistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023080966.0U CN213518246U (en) | 2020-12-18 | 2020-12-18 | Structure for controlling power-on time sequence of PCIE board card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023080966.0U CN213518246U (en) | 2020-12-18 | 2020-12-18 | Structure for controlling power-on time sequence of PCIE board card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213518246U true CN213518246U (en) | 2021-06-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202023080966.0U Active CN213518246U (en) | 2020-12-18 | 2020-12-18 | Structure for controlling power-on time sequence of PCIE board card |
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| Country | Link |
|---|---|
| CN (1) | CN213518246U (en) |
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- 2020-12-18 CN CN202023080966.0U patent/CN213518246U/en active Active
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