JPH06342414A - Data transfer device - Google Patents

Abstract

PURPOSE:To provide the data transfer device, which can speedily restart transfer after the transfer operation is interrupted, without expanding circuit scale. CONSTITUTION:A read/write control circuit 3 and a data storage device 7 for temporarily storing data are interposed between a host device 9 and a memory 10, data to be asynchronously transferred between the host device 9 and the memory 10 are temporarily stored in the data storage device 7 based on the control of the read/write control circuit 3, and the data stored in the data storage device 7 are transferred to the host device 9 or the memory 10 based on the control of the read/write control circuit 3. The read/write control circuit 3 is provided with a function for storing an address corresponding to the data stored in the data storage device 7 based on the control of this read/write control circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device for transferring data between a host device such as MPU and a memory in a data processing device.

In recent data processing apparatuses, there is an increasing demand for speeding up processing operations, ensuring high reliability and cost performance. Therefore, in the data transfer device used in such a data processing device, it is required to improve the efficiency of the retransfer operation after the transfer operation is interrupted due to some abnormality.

[0003]

2. Description of the Related Art An example of a conventional data transfer device will be described with reference to FIG. The timing adjusting circuit 1 operates so as to adjust the timing when a data writing operation to a memory or a data reading operation from a memory is performed between an upper device such as an MPU which operates asynchronously and a memory. .

That is, the timing adjustment circuit 1 receives a data request signal DRE from an MPU (not shown).
Q, write and read control signal XWR, and data strobe signal XDS are input, and the same timing adjustment circuit 1
To MPU, the acknowledge signal DACK is output, and the timing adjustment circuit 1 outputs the control signals XWE, XRAS, and XCAS to the memory (not shown).

Further, the timing adjusting circuit 1 outputs a control signal to the FIFO memory 2 based on the signals DREQ, XWR and XDS. Further, the timing adjustment circuit 1 outputs a control signal to the address control circuit 5 and the FIFO memory 2 based on the control signals DREQ, XWR and XDS.

The address control circuit 5 outputs address signals MA7 to MA0 to the memory based on the control signal output from the timing adjustment circuit 1 and an instruction from the MPU.

In the FIFO memory 2, data D7 to D output from the MPU at the time of writing operation is written.
0 is written, and the written data is FI based on the control signal of the timing adjustment circuit 1.
Write data MD7 to MD0 are sequentially output from the FO memory 2 to the memory in order from the previously written data.

Further, the data MD7 to MD0 read from the memory are written into the FIFO memory 2 during the read operation, and the written data is based on the control signal of the timing adjusting circuit 1. , From the FIFO memory 2 to the MPU,
Read data D7 to
It is sequentially output as D0.

In the data transfer apparatus configured as described above, the data D output from the MPU to the FIFO memory 2 during the data write operation from the MPU to the memory.
7 to D0 are stored in the same FIFO memory 2 and
The write data MD7 to MD0 are sequentially output from the O memory 2 to the memory at a predetermined timing.

That is, the timing adjustment circuit 1 is an MPU.
The FIFO memory 2 is controlled based on the control signals DREQ, XWR, and XDS output from the MPU.
The data D7 to D0 output to the O memory are sequentially stored in the FIFO memory 2 under the control of the timing adjustment circuit 1.

The data D7 to D0 stored in the FIFO memory 2 are output to the memory as write data MD7 to MD0 in synchronization with the control signals XWE, XRAS, XCAS output from the timing adjusting circuit 1 to the memory. .

At this time, the address control circuit 5 outputs the address value of the memory into which the write data MD7 to MD0 are written based on the control signal output from the timing adjusting circuit 1 to the FIFO memory 2.

In the FIFO memory 2, the same F
Whether there is a free area in the IFO memory 2 and the same FI
It detects whether or not there is valid write data in the FO memory 2, and outputs it to the timing adjustment circuit 1.

Further, during the data read operation from the memory to the MPU, read data MD7 to MD0 read from the memory to the FIFO memory are stored in the FIFO memory 2 and read from the FIFO memory 2 to the MPU at a predetermined timing. The data D7 to D0 are sequentially output.

That is, the timing adjustment circuit 1 is an MPU.
The address control circuit 5 is controlled based on each control signal DREQ, XWR, XDS output from
Read data MD7 to MD read to the FO memory
0 is the same FIFO under the control of the timing adjustment circuit 1.
Sequentially stored in the O memory 2.

Then, the read data MD7 to MD0 stored in the FIFO memory 2 are transferred to the timing adjustment circuit 1
Are output to the memory as read data D7 to D0 in synchronization with the control signal DACK output from the.

At this time, in the FIFO memory 2, the same FI
Whether there is a free area in the FO memory 2 and the same FIFO
It is detected whether or not there is valid read data in the O memory 2, and it is output to the timing adjustment circuit 1.

[0018]

In the above data transfer apparatus, if the transfer operation is requested again from the MPU after the transfer operation is interrupted due to some abnormality during data transfer, the transfer operation is set to the same MPU. The following operations are performed based on the executed program.

That is, the MPU erases the data remaining in the FIFO memory 2, resets the address value of the address control circuit 5, and then restarts the transfer operation of the data which has not been transferred.

In such a case, the MPU must detect how far the transfer of the read data or the write data has been completed through the FIFO memory 2 and calculate the address of the data that needs to be retransferred.

Since the data remaining in the FIFO memory 2 is erased, it is necessary to transfer the erased data to the FIFO memory 2 again when the transfer is restarted. Therefore, there is a problem that the transfer time increases.

Further, the following transfer resuming operation may be set. That is, the number of data remaining in the FIFO memory 2 is detected, and the same F
The address of the leading data of the data remaining in the IFO memory 2 is calculated. Then, the address of the transfer destination and the address of the head data are sequentially compared, and when both addresses match, the transfer operation is restarted from the head data.

However, in order to set such a transfer restart operation, in the MPU or its peripheral circuit,
Since it is necessary to have a function of detecting the number of data remaining in the FIFO memory 2 and a calculation function for calculating the start address of the data, there is a problem that the circuit scale increases.

Further, since it takes time to detect the number of data and calculate the head address as described above, there is a problem that it takes time to restart the transfer operation. An object of the present invention is to provide a data transfer device capable of promptly performing a transfer restart operation after interrupting a transfer operation without increasing the circuit scale.

[0025]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, the read / write control circuit 3 and the data storage device 7 for temporarily storing data are interposed between the host device 9 and the memory 10, and the host device 9 and the memory 1 are connected.
The data transferred asynchronously with 0 is stored in the data storage device 7 under the control of the read / write control circuit 3.
The data temporarily stored in the data storage device 7 is transferred to the host device 9 or the memory 10 under the control of the read / write control circuit 3. The read / write control circuit 3 has a function of storing an address corresponding to the data stored in the data storage device 7 under the control of the read / write control circuit 3.

[0026]

In the data transfer operation, the contents of the data stored in the data storage device 7 can be confirmed based on the address stored in the read / write control circuit 3.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIG.
3 and FIG. The same components as those in the conventional example will be described with the same reference numerals.

The timing adjusting circuit 1 adjusts the timing when performing a data writing operation from the MPU to the memory or a data reading operation from the memory to the MPU between the MPU and the memory which operate asynchronously. To work.

That is, the timing adjustment circuit 1 receives a data request signal DRE from an MPU (not shown).
Q, write and read control signal XWR, and data strobe signal XDS are input, and the same timing adjustment circuit 1
Control signal DACK is output to the MPU from the timing adjustment circuit 1 and each control signal X is sent to the memory (not shown).
WE, XRAS, XCAS are output.

Further, the timing adjusting circuit 1 outputs a control signal to the first and second FIFO memories 2 and 4 based on the control signals DREQ, XWR and XDS. In addition, the timing adjustment circuit 1 controls the control signals DRE.
A control signal is output based on Q, XWR, and XDS.

The address control circuit 5 outputs an address signal for performing a read operation from the memory based on a control signal output from the timing adjustment circuit 1 and an instruction from the MPU, to the first FIFO memory 4 and a selector. Output to the circuit 8.

During the read operation, the selector circuit 8 selects the address signal output from the address control circuit 5 and outputs it to the memory as address signals MAD7 to MAD0.

Further, the first selector circuit 8 selects an address signal output from the first FIFO memory 4 during a write operation and outputs the address signal MA to the memory.
Output as 7 to MA0.

Address signals output from the address control circuit 5 are sequentially written in the first FIFO memory 4, and the written address signals are output to the selector circuit 8 in the order of writing.

Data corresponding to the address written in the first FIFO memory 4 is written in the second FIFO memory 2 in synchronization with the write operation in the first FIFO memory 4.

That is, during the write operation, the data D7 to D0 output from the MPU is the second FIFO.
While being written in the O memory 2, the written data is transferred from the second FIFO memory 2 to the memory on the basis of the control signal of the timing adjusting circuit 1.
Write data MD7 in order from the previously written data
~ MD0 are sequentially output.

In the second FIFO memory 2,
During the read operation, the data MD7 to MD0 read from the memory are written, and the written data is written from the second FIFO memory 2 to the MP based on the control signal of the timing adjustment circuit 1.
To the U, the read data D7 to D0 are sequentially output from the previously written data.

Next, the operation of the data transfer device configured as described above will be described with reference to FIG. When the write / read control signal XWR input from the MPU becomes H level, the data transfer device enters the read mode in which the data stored in the memory is transferred to the MPU.

In this state, when the L level data request signal DREQ and the data strobe signal XDS are input to the timing adjustment circuit 1, the timing adjustment circuit 1 outputs the H level write control signal XWE to the memory.
Each of the control signals XRAS and XCAS is input, the data is read from the same memory, and the data is output to the second FIFO memory 2.

When the data output from the second FIFO memory 2 to the MPU is ready, the timing adjustment circuit 1
The acknowledge signal DACK is input to the MPU from the
The PU inputs the control signal XDS and the data is read.

That is, based on the control signals XRAS and XCAS output from the timing adjustment circuit 1 to the memory, the address control circuit 5 outputs an address for reading data from the memory to the selector circuit 8 and the first FIFO memory 4. .

In the selector circuit 8, the address control circuit 5
The address value output from the address signal MA7 to MA
It is output to the memory as 0. The first FIFO memory 4 sequentially stores the address values.

Address values MA7 to M input to the memory
The read data MD7 to MD0 read from the same memory based on A0 are sequentially stored in the second FIFO memory 2.

The address values MA7 to MA0 stored in the first FIFO memory 4 and the read data MD7 to MD0 stored in the second FIFO memory 2 are output from the timing adjusting circuit 1 at the timing based on the data strobe signal XDS. Are output sequentially.

Then, the address values MA7 to MA0 stored in the first FIFO memory 4 are transferred from the first FIFO memory 4 via the timing adjustment circuit 1 to the address signal AD.
It is output to the MPU as DR.

The read data MD7 to MD0 stored in the second FIFO memory 2 are transferred from the second FIFO memory 2 to the MPU as read data D7 to D0.

During the read operation, after the transfer operation is stopped due to some abnormality, an instruction is executed from the MPU to restart the transfer operation, and the request signal DREQ is input to the timing adjustment circuit 1. The transfer operation is immediately restarted based on the data remaining in the first and second FIFO memories 4 and 2.

That is, the MPU reads the start address of the address value remaining in the first FIFO memory 4,
If the address is an address for restarting the transfer, the request signal DREQ is output to the timing adjustment circuit 1. Then, the storage of the address value in the first FIFO memory 4 and the transfer of the read data via the second FIFO memory 2 are restarted.

The same applies to the resuming operation after the transfer interruption during the writing operation. That is, during the write operation, the address values output by the address control circuit 5 are sequentially written in the first FIFO memory 4.

Then, in the restart operation after the transfer is interrupted, the MPU reads the start address of the address value remaining in the first FIFO memory 4, and if the address is the address for restarting the transfer, the request signal DREQ.
Is output to the timing adjustment circuit 1. And the first F
Storage of address value in IFO memory 4 and second FIFO
Writing of data via the O memory 2 is restarted.

As described above, in this data transfer apparatus, in addition to the second FIFO memory 2 for temporarily storing data, the address value corresponding to the data stored in the second FIFO memory 2 is temporarily stored. A first FIFO memory 4 is provided.

Therefore, at the time of resuming operation after the transfer is interrupted, the number of data remaining in the second FIFO memory 4 is detected, the memory address operation for continuing the transfer or the FIFO memory is reset and transferred to the address control circuit 5. Processing such as setting a memory address for continuation is unnecessary.

Therefore, the restart operation after the transfer interruption can be promptly performed, and the MPU at the time of the transfer restart operation can be performed.
It is also possible to reduce the burden of.

[0054]

As described above in detail, the present invention has an excellent effect that it is possible to provide a data transfer device capable of promptly performing a transfer restart operation after suspending a transfer operation without increasing the circuit scale. Demonstrate.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment.

FIG. 3 is a waveform diagram showing the operation of one embodiment.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 3 read / write control circuit 7 data storage device 9 host device 10 memory

Claims (1)

[Claims] 1. A read / write control circuit (3) and a data storage device (7) for temporarily storing data are interposed between a host device (9) and a memory (10), and the host device (9). Data that is asynchronously transferred between the memory and the memory (10) is temporarily stored in the data storage device (7) under the control of the read / write control circuit (3), and then stored in the data storage device (7). A data transfer device for transferring the stored data to the host device (9) or the memory (10) under the control of the read / write control circuit (3), wherein the read / write control circuit (3) A data transfer device for storing an address corresponding to data stored in the data storage device (7).