JPH06338682A - Manufacture of multilayer substrate - Google Patents

Abstract

PURPOSE:To surely reduce warp of a multilayer substrate with good operativity and to readily control a thickness of the multilayer substrate. CONSTITUTION:The constitution includes a process for forming a wiring pattern 26 on a plurality of circuit sheets 21, 22, 25, a process for flattening the circuit sheets 21, 22, 25 by forming a member 27 of the same material as the circuit sheets 21, 22, 25 on the circuit sheets 21, 22, 25 not including the wiring pattern 26 and a process for baking after laminating a plurality of flattened circuit sheets 21, 22, 25 integrally.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a method for manufacturing a multilayer substrate.

[0002]

2. Description of the Related Art Conventionally, a manufacturing method of this type will be described with reference to FIGS. 2 is a sectional view of a manufacturing process, FIG. 3 is a sectional view of a multilayer substrate, and FIG. 4 is a sectional view showing a warp of the multilayer substrate. First, after the adhesive 2 or the like is applied to all or part of the back surface peripheral portion of the glass ceramic green sheet 1 as a dummy sheet (FIG. 2a), 2 to 4 glass ceramic green sheets 1 are stacked and adhered, The polishing sheet 3 is formed. Next, a via hole 4 serving as an electric conduction path for transmitting an electric signal of a wiring pattern, which will be described later, to the surface of the substrate is formed in a predetermined portion of the polishing sheet 3 by punching or the like (FIG. 2b). After that, Au, Ag,
Via conductor paste material 5 made of Cu or a compound thereof is collectively filled by printing or the like (FIG. 2C).

Subsequently, a glass ceramic green sheet for circuit (hereinafter, referred to as a circuit sheet) 6, 7 is provided with a via hole 8 by punching or the like, and Au, Ag, Cu or those is formed in the via hole 8. The conductor paste material 9 for vias made of the above compound is collectively filled by printing or the like. After that, circuit sheets 6 and 7, and circuit sheet 1
On the surface of 0, a wiring pattern 11 of an inner layer circuit made of Au, Ag, Cu or a compound thereof and connected to the via paste material 9 is formed (FIG. 2d). After that, the circuit sheet 10, the circuit sheet 7, the circuit sheet 6 and the polishing sheet 3 are sequentially laminated, press-bonded by heating and pressing to be integrated, and then baked (FIG. 3).

At the time of firing, the upper and lower warps 12 and 13 of about 50 to 200 μm are generated due to the difference in firing shrinkage ratio between the wiring pattern 11 and the polishing sheet 3 and the circuit sheets 6, 7, and 10. The sheet 3 is ground to the line A-A to reduce the upper warp 12 and the lower warp 13 (FIG. 4). Thus, the multilayer glass ceramic substrate is completed. In this case, from the uppermost point of the upper sloping 12 to the lower sloping 13
The sled up to the lowest point is L, the thickness of the glass ceramic green sheet 1 is t, the glass ceramic green sheet 1
Where n is the number of stacked layers, n is n × t ≧ L (L is approximately 5
0 to 200 μm) (normally n = 2 to 2)
4) and N is the number of polishing layers, N × t ≧ L and N <
satisfy n.

[0005]

However, in the above-mentioned conventional manufacturing method, since the warping is reduced, it is necessary to form the polishing sheet 3 and the polishing step, so that the workability is deteriorated. there were. Further, when the thickness of the multilayer substrate is limited as in a thin multi-chip module or the like, a sufficient number of glass ceramic green sheets 1 cannot be stacked, which causes a problem that warpage cannot be completely reduced. . Further, since the warp amount varies even in the multi-layer substrates of the same lot, the polishing amount of the polishing sheet 3 is different for each multi-layer substrate, which causes a problem in that the thickness of the multi-layer substrate varies. In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a multilayer substrate, which can surely reduce warpage of the multilayer substrate with good workability and can easily control the thickness of the multilayer substrate.

[0006]

In order to achieve the above-mentioned object, the present invention comprises a step of forming a wiring pattern on a plurality of circuit sheets, and the circuit in the area excluding the wiring pattern on the circuit sheet. And a step of flattening the circuit sheet by forming a member of the same material as that of the circuit sheet, and a step of firing after laminating and integrating a plurality of the flattened circuit sheets.

[0007]

In the present invention, the circuit sheet is flattened by forming a member of the same material as the circuit sheet in the area excluding the wiring pattern on the circuit sheet, so that the density in the multilayer substrate is made uniform. The warpage of the multi-layer substrate during firing is reliably reduced without forming and polishing the polishing sheet.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a multilayer substrate of the present invention will be described below with reference to FIG. Note that FIG. 1 shows a cross-sectional view of the manufacturing process. First, the circuit sheet (glass ceramic green sheet) 21, 22 is provided with a via hole 23 by punching or the like.
A via conductor paste material 24 made of u, Ag, Cu or a compound thereof is collectively filled by printing or the like. After that, on the surfaces of the circuit sheets 21 and 22 and the circuit sheet 25, Au, Ag, Cu or a compound thereof is formed,
Wiring pattern 2 to which via paste material 24 for vias is connected
6 (FIG. 1a).

Next, the circuit sheets 21, 22, 25 are placed on the circuit sheets 21, 22, 25 excluding the wiring pattern 26.
The flattening paste material 27 of the same material as the wiring pattern 26
Printed and dried to the same height as the circuit sheets 21, 2
Plane 2 and 25 (Fig. 1b). After that, the circuit sheet 25, the circuit sheet 22, and the circuit sheet 21 are sequentially laminated, pressure-bonded by heating and pressure to be integrated, and then baked. Thus, the multilayer glass ceramic substrate is completed (FIG. 1c). As described above, in this embodiment, after the circuit sheets 21, 22, 25 are flattened by the flattening paste material 27 which is the same material as the circuit sheets 21, 22, 25, the circuit sheets 21, 22, 25 are Since the layers are laminated, the density in the multilayer substrate is made uniform, and warpage during firing can be prevented. Further, this embodiment can be applied to thin film circuit pattern formation by sputtering or the like on the substrate surface, and enables high speed signal transmission of the thin film circuit.

[0010]

As described above, according to the present invention, a member made of the same material as the circuit sheet is formed on the circuit sheet other than the wiring pattern, and the circuit sheet is planarized and then laminated and integrated. Therefore, the density in the multilayer substrate is made uniform, and warpage of the multilayer substrate is reduced without forming and polishing the polishing sheet. Therefore, warpage can be reliably reduced with good workability, and the thickness of the multilayer substrate can be easily controlled.

[Brief description of drawings]

FIG. 1 is a process sectional view of a manufacturing method of the present invention.

FIG. 2 is a process sectional view of a conventional manufacturing method.

FIG. 3 is a sectional view of a conventional multilayer substrate.

FIG. 4 is a sectional view showing a warp of a conventional multilayer substrate.

[Explanation of symbols]

 21,22,25 Circuit sheet 23 Via hole 24 Via conductor paste material 26 Wiring pattern 27 Flattening paste material

Claims (1)

[Claims] 1. A step of forming a wiring pattern on a plurality of circuit sheets, and a member of the same material as that of the circuit sheet is formed in an area of the circuit sheet excluding the wiring pattern. And a step of flattening the plurality of flattened circuit sheets, and firing the laminated and integrated circuit sheets.