JPH0661646A - Circuit board and production thereof - Google Patents
Circuit board and production thereofInfo
- Publication number
- JPH0661646A JPH0661646A JP21055492A JP21055492A JPH0661646A JP H0661646 A JPH0661646 A JP H0661646A JP 21055492 A JP21055492 A JP 21055492A JP 21055492 A JP21055492 A JP 21055492A JP H0661646 A JPH0661646 A JP H0661646A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film circuit
- circuit
- board
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、回路基板及びその製造
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board and a method for manufacturing the same.
【0002】[0002]
【従来の技術】硬質回路基板上に薄膜回路を形成した回
路基板の従来例を図13に示す。この従来例において、
グリーンシートを焼成して形成されたセラミック多層基
板(硬質基板1)の表面部に薄膜回路2が形成されてい
る。2. Description of the Related Art FIG. 13 shows a conventional circuit board in which a thin film circuit is formed on a hard circuit board. In this conventional example,
A thin film circuit 2 is formed on the surface of a ceramic multilayer substrate (hard substrate 1) formed by firing a green sheet.
【0003】薄膜回路2は、ポリイミド樹脂を絶縁層4
として複数数層の導体層を積層して形成される。The thin film circuit 2 includes a polyimide resin as an insulating layer 4
Is formed by laminating a plurality of conductor layers.
【0004】[0004]
【発明が解決しようとする課題】しかし、上述した従来
例において、ポリイミド絶縁層4のキュア工程での加熱
により生じるポリイミド絶縁層4の残留応力や、あるい
は基板1の反りによる応力により、図13(b)に示す
ように、ポリイミド絶縁層4が基板1の界面から剥離し
たり、あるいは、基板1の界面が破損することがあり、
製造歩止まりが低いという欠点を有するものであった。However, in the above-mentioned conventional example, the residual stress of the polyimide insulating layer 4 caused by the heating in the curing step of the polyimide insulating layer 4 or the stress due to the warp of the substrate 1 causes the problem shown in FIG. As shown in b), the polyimide insulating layer 4 may be peeled from the interface of the substrate 1 or the interface of the substrate 1 may be damaged.
It had a defect that the production yield was low.
【0005】本発明は、以上の欠点を解消すべくなされ
たものであって、製造歩止まりが高い回路基板及びその
製造方法を提供することを目的とする。The present invention has been made to solve the above drawbacks, and an object of the present invention is to provide a circuit board having a high manufacturing yield and a manufacturing method thereof.
【0006】[0006]
【課題を解決するための手段】本発明によれば上記目的
は、実施例に対応する図1に示すように、硬質基板1上
に薄膜回路2を積層した回路基板であって、前記基板1
の薄膜回路2積層面の周縁に、内方から外方に向かう複
数の凹溝3、3・・を凹設した回路基板を提供すること
により達成される。According to the present invention, the above-mentioned object is a circuit board in which a thin film circuit 2 is laminated on a hard substrate 1 as shown in FIG.
It is achieved by providing a circuit board in which a plurality of concave grooves 3, 3, ...
【0007】また、上記回路基板は、配線パターン5が
印刷されたグリーンシート6を複数枚積層した後、焼成
してヴィア7により層間接続されたセラミック多層基板
1を得、次いで、前記セラミック多層基板1の表面部周
縁に内方から外方に向かう複数の凹溝3、3・・を研削
し、この後、前記凹溝3形成面上に薄膜回路2を形成す
る回路基板の製造方法により製造される。In the circuit board, a plurality of green sheets 6 each having a wiring pattern 5 printed thereon are laminated and then fired to obtain a ceramic multilayer board 1 which is interconnected by vias 7. Then, the ceramic multilayer board is obtained. Manufactured by a method for manufacturing a circuit board in which a plurality of recessed grooves 3, 3 ... To be done.
【0008】[0008]
【作用】本発明における硬質基板1は、表面周縁に内方
から外方に向かう複数の凹溝3を備え、薄膜回路2は、
上記凹溝3を備えた面上に構成される。The hard substrate 1 according to the present invention is provided with a plurality of concave grooves 3 extending from the inner side to the outer side at the peripheral edge of the surface, and the thin film circuit 2 is
It is formed on the surface provided with the concave groove 3.
【0009】薄膜回路2の構成工程において、薄膜回路
2の絶縁層4に残留する応力、あるいは基板1の反りに
よる応力は、各凹溝3により吸収され、薄膜回路2との
境界面からの剥離等が確実に防止される。In the process of forming the thin film circuit 2, the stress remaining in the insulating layer 4 of the thin film circuit 2 or the stress caused by the warp of the substrate 1 is absorbed by each groove 3 and separated from the boundary surface with the thin film circuit 2. Are reliably prevented.
【0010】[0010]
【実施例】以下、本発明の望ましい実施例を添付図面に
基づいて詳細に説明する。図3以下に回路基板の製造方
法を示し、図3ないし図5はセラミック多層基板1(硬
質基板1)の製造工程を、図6以下は、薄膜回路2の製
造工程を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. A method of manufacturing a circuit board is shown in FIG. 3 and subsequent figures, FIGS. 3 to 5 show a manufacturing step of the ceramic multilayer board 1 (hard board 1), and FIG. 6 and subsequent figures show a manufacturing step of the thin film circuit 2.
【0011】先ず、セラミック粉体、および適宜のバイ
ンダをスラリー状に混練して形成されるグリーンシート
6にヴィアホール8を穿孔し、該ヴィアホール8内に導
体金属を充填する。First, a via hole 8 is bored in a green sheet 6 formed by kneading a ceramic powder and an appropriate binder in a slurry form, and the via hole 8 is filled with a conductive metal.
【0012】この後、グリーンシート6上に導体金属を
スクリーン印刷して所定の配線パターン5、5・・を形
成する(図3参照)。このようにして形成された複数の
グリーンシート6、6・・は、複数枚積層され、焼成炉
において焼成される。焼成により図4に示すように、各
導体層間がヴィア7により適宜接続されたセラミック多
層基板1が得られる。Thereafter, a conductor metal is screen-printed on the green sheet 6 to form predetermined wiring patterns 5, 5, ... (See FIG. 3). The plurality of green sheets 6, 6 ... Formed in this way are laminated and fired in a firing furnace. By firing, as shown in FIG. 4, a ceramic multilayer substrate 1 in which the conductor layers are properly connected by vias 7 is obtained.
【0013】以上のようにして形成されたセラミック多
層基板1の表面部には、図5に示すように、適宜の切削
手段を使用して凹溝3、3・・が凹設される。凹溝3
は、セラミック多層基板1の周縁部に形成され、内方か
ら外方に向かう方向に平行に設けられる。.. are formed in the surface portion of the ceramic multi-layer substrate 1 formed as described above by using an appropriate cutting means, as shown in FIG. Groove 3
Are formed on the peripheral portion of the ceramic multilayer substrate 1 and are provided parallel to the direction from the inside to the outside.
【0014】次いで、上記セラミック多層基板1上に薄
膜回路2が形成される。すなわち、先ず、上記セラミッ
ク多層基板1上には、導体膜(密着層)がスパッタリン
グ工程により形成される(図6参照)。この後、スパッ
タ膜9上にレジスト層10を形成する(図7参照)。Next, a thin film circuit 2 is formed on the ceramic multilayer substrate 1. That is, first, a conductor film (adhesion layer) is formed on the ceramic multilayer substrate 1 by a sputtering process (see FIG. 6). Then, a resist layer 10 is formed on the sputtered film 9 (see FIG. 7).
【0015】次に、レジスト層10が形成されたセラミ
ック多層基板1をメッキすると、スパッタ膜9が露出し
ている部位が図8に示すように、導体金属11により選
択メッキされ、この後、レジスト層10を剥離し、次い
で、パネルエッチングにより露出したスパッタ膜9をエ
ッチングして1層の薄膜回路パターン12が形成される
(図9、図10参照)。Next, when the ceramic multilayer substrate 1 on which the resist layer 10 is formed is plated, the portion where the sputtered film 9 is exposed is selectively plated with the conductive metal 11 as shown in FIG. The layer 10 is peeled off, and then the sputtered film 9 exposed by panel etching is etched to form a single-layer thin film circuit pattern 12 (see FIGS. 9 and 10).
【0016】以上の薄膜回路パターン12は、セラミッ
ク多層基板1上に複数層積層されるもので、第2層以降
の積層に際して、先ず、下層全面に渡って感光性ポリイ
ミド13がスピンコーティングにより塗布される(図1
1参照)。The above-mentioned thin film circuit pattern 12 is formed by laminating a plurality of layers on the ceramic multilayer substrate 1. When laminating the second and subsequent layers, first, the photosensitive polyimide 13 is applied by spin coating over the entire lower layer. (Fig. 1
1).
【0017】この後、露光、現像、ハードベーク工程を
経て感光性ポリイミド13を選択エッチングすると、層
間接続ヴィア7’を残して下層がポリイミド絶縁層4に
より絶縁された状態となり(図12参照)、この上面に
上述した同様の手順で複数層の回路パターンを積層し
て、図2に示す回路基板が形成される。After that, when the photosensitive polyimide 13 is selectively etched through the steps of exposure, development, and hard baking, the lower layer is insulated by the polyimide insulating layer 4 leaving the interlayer connection via 7 '(see FIG. 12), A circuit board shown in FIG. 2 is formed by laminating a plurality of layers of circuit patterns on the upper surface in the same procedure as described above.
【0018】なお、以上において凹溝3は、グリーンシ
ート6の焼成後に行われる切削工程により形成される
が、この外に、グリーンシート6の積層、圧縮時に形成
することも可能であり、この場合、圧縮型に、凹溝3に
対応する突部を設けておけば、特別の工程を要すること
なく、凹溝3の形成を行うことができる。In the above, the groove 3 is formed by a cutting process performed after firing the green sheet 6, but it is also possible to form the groove 3 when laminating and compressing the green sheet 6 in this case. If the protrusion corresponding to the concave groove 3 is provided in the compression mold, the concave groove 3 can be formed without requiring a special process.
【0019】また、硬質基板1としては、セラミック多
層基板以外に、ガラス基板等にも適用することができる
ことはもちろんである。Further, the hard substrate 1 can be applied not only to the ceramic multilayer substrate but also to a glass substrate or the like.
【0020】[0020]
【発明の効果】以上の説明から明らかなように、本発明
によれば、基板の反り、あるいは絶縁膜の製造時におけ
る歪みによる応力が凹溝により吸収されるために、薄膜
部の剥離を完全に防止することができ、製造歩止まりを
向上させることができる。As is apparent from the above description, according to the present invention, since the stress due to the warp of the substrate or the strain during the manufacturing of the insulating film is absorbed by the concave groove, the peeling of the thin film portion can be completed completely. Can be prevented and the manufacturing yield can be improved.
【図1】本発明の実施例を示す斜視図である。FIG. 1 is a perspective view showing an embodiment of the present invention.
【図2】図1の断面図である。FIG. 2 is a cross-sectional view of FIG.
【図3】グリーンシートの積層工程を示す図である。FIG. 3 is a diagram showing a stacking process of green sheets.
【図4】硬質基板の断面図である。FIG. 4 is a cross-sectional view of a hard substrate.
【図5】凹溝を切削した状態を示す斜視図である。FIG. 5 is a perspective view showing a state in which a groove is cut.
【図6】スパッタ膜の形成工程を示す断面図である。FIG. 6 is a cross-sectional view showing a step of forming a sputtered film.
【図7】レジスト膜の形成状態を示す断面図である。FIG. 7 is a cross-sectional view showing a formation state of a resist film.
【図8】導体金属のメッキ工程を示す断面図である。FIG. 8 is a cross-sectional view showing a conductive metal plating step.
【図9】レジスト膜を剥離した状態を示す断面図であ
る。FIG. 9 is a cross-sectional view showing a state in which a resist film is peeled off.
【図10】薄膜回路パターンを示す断面図である。FIG. 10 is a cross-sectional view showing a thin film circuit pattern.
【図11】ポリイミドの塗布工程を示す断面図である。FIG. 11 is a cross-sectional view showing a polyimide coating step.
【図12】ポリイミドの露光状態を示す断面図である。FIG. 12 is a cross-sectional view showing an exposed state of polyimide.
【図13】従来例を示す図で、(a)は全体斜視図、
(b)は薄膜回路の剥離状態を示す図である。FIG. 13 is a view showing a conventional example, (a) is an overall perspective view,
(B) is a figure which shows the peeling state of a thin film circuit.
1 硬質基板 2 薄膜回路 3 凹溝 4 絶縁層 5 配線パターン 6 グリーンシート 7 ヴィア 1 Hard Substrate 2 Thin Film Circuit 3 Recessed Groove 4 Insulating Layer 5 Wiring Pattern 6 Green Sheet 7 Via
Claims (4)
回路基板であって、 前記基板(1)の薄膜回路(2)積層面の周縁に、内方から
外方に向かう複数の凹溝(3、3・・)を凹設した回路基
板。1. A circuit board in which a thin film circuit (2) is laminated on a hard substrate (1), the inside of the substrate (1) being directed from the inside to the outside of the periphery of the laminated surface of the thin film circuit (2). A circuit board with multiple recesses (3, 3, ...)
り、かつ、薄膜回路(2)の絶縁層(4)はポリイミド樹脂
により形成される請求項1記載の回路基板。2. The circuit board according to claim 1, wherein the board (1) is a ceramic multilayer board, and the insulating layer (4) of the thin film circuit (2) is formed of a polyimide resin.
ート(6、6・・)を複数枚積層した後、焼成してヴィア
(7)により層間接続されたセラミック多層基板(1)を
得、 次いで、前記セラミック多層基板(1)の表面部周縁に内
方から外方に向かう複数の凹溝(3、3・・)を研削し、 この後、前記凹溝(3)形成面上に薄膜回路(2)を形成す
る回路基板の製造方法。3. A via is formed by stacking a plurality of green sheets (6, 6 ...) On which a wiring pattern (5) is printed and then firing them.
A ceramic multilayer substrate (1) interconnected by (7) is obtained, and then a plurality of concave grooves (3, 3, ...) From the inside to the outside are formed on the peripheral edge of the surface of the ceramic multilayer substrate (1). A method of manufacturing a circuit board, which comprises grinding, and then forming a thin film circuit (2) on the surface of the groove (3) formed.
工程において形成される請求項3記載の回路基板の製造
方法。4. The method for manufacturing a circuit board according to claim 3, wherein the recessed groove (3) is formed in a green sheet (6) laminating step.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21055492A JPH0661646A (en) | 1992-08-07 | 1992-08-07 | Circuit board and production thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21055492A JPH0661646A (en) | 1992-08-07 | 1992-08-07 | Circuit board and production thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0661646A true JPH0661646A (en) | 1994-03-04 |
Family
ID=16591246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21055492A Withdrawn JPH0661646A (en) | 1992-08-07 | 1992-08-07 | Circuit board and production thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0661646A (en) |
-
1992
- 1992-08-07 JP JP21055492A patent/JPH0661646A/en not_active Withdrawn
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991102 |