JPH06338522A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method for a compound semiconductor device which can be handled easily and the cracks and chippings generated by dicing can be prevented by conducting a process with which a chip is divided by lapping back and a PHS metal is maintained in a wafer state thereafter. CONSTITUTION:Grooves 15 are formed on the dicing line on the surface of the substrate 1 where an element is formed. The bottom face of the grooves 15 is exposed by lapping back and separated into chips. A PHS metal layer 9 is formed, and each chip is coupled by metal layer 9. The metal layer 9 is divided into chips by dicing it through the grooves 15.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a high power GaAs MES.
The present invention relates to a method for manufacturing a FET, and more particularly to a method for manufacturing a GaAs MESFET which is easy to handle in a wafer state.

[0002]

2. Description of the Related Art GaAs power, which is an example of a semiconductor device,
The MESFET has, for example, the structure shown in FIGS. 5A and 5B (Japanese Patent Laid-Open No. 4-165676). In the figure,
(1) is a semi-insulating substrate, (2), (3) and (4) are source, gate and drain electrodes formed on the substrate (1), (5), (6), ( 7) is source, gate,
A drain bonding pad, (8) is an N-type active layer formed on the surface of the substrate (1), and (9) is a metal layer such as gold plating formed on the back surface of the substrate (1) for a heat dissipation electrode and a thinned substrate. Plated heat sink (hereinafter referred to as PH) provided to improve the mechanical strength of (1)
(Abbreviated as S).

Usually, in the manufacture of semiconductor devices, a large number of elements are formed on a wafer and then the wafer is diced to be separated into individual chips. However, GaAs wafers are fragile in material, and GaA that adopts the PHS structure in particular is used.
In sMESFET, the substrate (1) is used to reduce the thermal resistance.
Since it is formed to be extremely thin with a thickness of 10 to 30 μ, there is a drawback that cracks and chips of the wafer frequently occur during dicing.

Therefore, a manufacturing method as shown in FIG. 6 was devised. That is, after forming an element on the surface of the substrate (1), the substrate (1) is attached to the support plate (11) with wax (12), and the back surface of the substrate (1) is polished to a thickness of 10 to 30 μm. Electrodes for plating are formed on the entire surface, and a resist mask (1) is provided between the chips as shown in FIG.
3) is formed, and only the lower part of the active layer (8) is partially plated with gold to form a metal layer (9), and the resist mask (13) is removed as shown in FIG. 6 (B). Figure 6
As shown in (C), the plating metal and the substrate (1) are etched using the metal layer (9) as a mask to separate the substrate (1) into individual chips (14).

[0005]

However, in the above manufacturing method, the chips are individually separated at the stage when the PHS metal layer (9) is formed. Therefore, it cannot be treated as a wafer in the wafer check process in which a probe is brought into contact with each bonding pad (5) (6) (7) to measure the electrical characteristics of the element. There was a drawback that the support plate (11) had to be replaced on the back side of 1).

[0006]

The present invention has been made in view of the above-mentioned drawbacks, and includes a step of forming a groove (15) on a dicing line after forming an element on the surface of a substrate (1),
With the support plate attached to the surface of the substrate (1), the groove (1
Polishing the back surface of the substrate (1) until 5) is exposed,
The step of forming the PHS metal layer (9) on the entire surface of the substrate (1), the substrate (1) is peeled from the support plate (11), and the groove (1
And a step of separating the individual layers into individual chips by dicing the metal layer (9) through (5), thereby providing a method for producing a compound semiconductor device that can be handled as a wafer until the final stage of device production. Is.

[0007]

According to the present invention, since the PHS metal layer (9) connects the individual chips and maintains the mechanical strength, it can be handled as a wafer. Further, since the GaAs wafer is separated at the stage when the back lap (polishing) of the back surface of the substrate (1) is completed, and the dicing only cuts the metal layer (9), the wafer is not cracked or chipped at the time of dicing.

[0008]

An embodiment of the present invention will be described in detail below with reference to the drawings. 1 to 4 are GaAsME of the present invention
FIG. 6 is a cross-sectional view for explaining a method for manufacturing an SFET step by step. First, referring to FIG. 1 (A), a GaAs substrate (1)
Form a source gate drain on the surface and MESFE
A T element is formed. (8) is an N-type active layer formed by diffusion which becomes an active region of the MESFET. At this stage, the substrate (1) has a thickness of 400 to 500 μm, and if it has such a thickness, it can be handled as a wafer in the production line. The surface of the element is covered with a final passivation film, and openings for probe contact and wire connection are provided on the surfaces of the bonding pads (5), (6) and (7).

Referring to FIG. 1 (B), a resist mask (14) is formed on the surface of the substrate (1), and wet etching is performed so that the final substrate thickness is formed on a portion of the surface of the substrate (1) which will be a dicing line. A groove (15) having a depth of 5 to 10 μm is formed. Referring to FIG. 1C, a wax (12) is applied to the surface of the substrate (1) and the surface of the substrate (1) is attached to a support plate (11). The support plate (11) plays a role of maintaining the mechanical strength of the thin-walled substrate (1) in the process and facilitating the processing such as handling.

Referring to FIG. 2A, the back surface of the substrate (1) is polished so that the thickness of the substrate (1) is 10 to 30 μm. If the depth of the groove (15) is made larger than the thickness of the substrate (1), the bottom surface of the groove (15) is exposed by this processing, so that the substrate (1) is separated into chips for each element. Each chip is held by the support plate (11). Groove (1
5) Since the inside is filled with the wax (12), the surface of the wax (12) is exposed by polishing.

Referring to FIG. 2B, a resist mask (16) is formed on the back surface side of the substrate (1), and the substrate (1) under the active layer (8) is etched by 5 to 25 μm by wet etching. Then, a recess (17) is formed. This processing is
The distance from the active layer to PHS is further shortened to improve heat dissipation efficiency. In addition, the substrate (1) is penetrated and PH
When forming a via hole for directly connecting S and the source electrode, etching processing is performed before and after this step.

Referring to FIG. 2C, after removing the resist mask (16), a Ti / Au electrode (18) having a thickness of several hundred to several thousand Å is formed on the entire back surface of the substrate (1) by a sputtering method.
To form. Referring to FIG. 3A, a resist mask (19) is formed again on the surface of the Ti / Au electrode (18), and gold (20) is selectively formed only in the recesses (17) formed in the previous step. To plate. This plating is performed until the gold (20) in the recess (17) has a thickness enough to bury the recess (17).

Referring to FIG. 3B, the resist mask (19) is removed, and gold plating is performed again to form a metal layer (9) to be PHS on the entire back surface of the substrate (1). The metal layer (9) and the gold (20) inside the recess (17) are integrated. Since the chips are already divided into individual pieces, the film thickness of the metal layer (9) is such that the individual chips can be connected by themselves and the wafer state can be maintained. 1
If the film thickness is 0 to 30 μ, it can be handled as a wafer. However, one of the conditions is that the thickness is such that dicing is possible.

Referring to FIG. 3C, the substrate (1) divided into each chip is separated from the support plate (11) and the wax (12) is removed. Each substrate (1) is kept in a wafer state by the metal layer (9). Referring to FIG. 4, after the quality of the element is judged (wafer check) using the bonding pads (5), (6) and (7) on the surface of the substrate (1), the metal layer (9) is diced. The chip (21) is attached, and the metal layer (9) is cut through the groove (15) by a dicing blade to separate the chips for each substrate (1).

According to the manufacturing method of the present invention, the GaAs substrate (1) is already separated at the time of dicing by forming the groove (15) in the substrate (1) in advance, and the dicing blade is a metal layer. Since only (9) is cut, no cracks, chips, etc. will occur when the GaAs substrate (1) is cut. On the other hand, since each chip keeps the wafer state by the metal layer (9) even after the back lap (polishing) of the substrate (1), the handling becomes easy even in the wafer checking step. Then, by etching the portion corresponding to the active layer on the back surface of the substrate (1),
The thermal resistance of the device is reduced to improve the device characteristics.

Although this embodiment has been described by taking the GaAs MESFET as an example, the diode using the GaAs substrate, the MI.
It is also applicable to C, MMIC and the like.

[0017]

As described above, according to the present invention, it is possible to provide a manufacturing method capable of preventing the cracking or chipping of a GaAs wafer during dicing. Further, there is an advantage that a manufacturing method capable of handling each chip in a wafer state until just before dicing in the manufacturing process can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 3 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 4 is a cross-sectional view for explaining the manufacturing method of the present invention.

5 (A) is a plan view and FIG. 5 (B) is a sectional view showing a GaAs power-MESFET.

FIG. 6 is a cross-sectional view for explaining a conventional manufacturing method.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 23/34 A 29/44 B 7376-4M 29/784 27/095 7376-4M H01L 29/80 E

Claims (2)

[Claims] 1. A step of forming a plurality of circuit elements on a main surface of a semi-insulating substrate, a step of etching a substrate surface on a dicing line for dividing the plurality of circuit elements into individual chips to form a groove, A step of adhering a main surface of the substrate to a holding plate; a step of grinding the back surface of the substrate until the groove is exposed; a step of attaching a metal material having a thickness sufficient to hold the plurality of chips to the entire back surface of the substrate A step of separating the substrate from the support plate and dicing the metal material located in the groove into individual chips, the method of manufacturing a compound semiconductor device. 2. A step of forming a plurality of circuit elements on a main surface of a semi-insulating substrate, a step of etching a substrate surface on a dicing line dividing the plurality of circuit elements into individual chips to form a groove, A step of adhering the main surface of the substrate to a holding plate; a step of shaving the back surface of the substrate until the groove is exposed; and a recess formed by partially etching the back surface of the substrate corresponding to the active region of the circuit element. A step of selectively depositing a metal material and burying the concave portion with the metal material, a metal material having a thickness sufficient to hold the plurality of chips is attached to the entire back surface of the substrate, and the metal of the concave portion is Integrating the material, separating the substrate from the support plate, and dicing the metal material located in the groove into individual chips. Method of manufacturing a compound semiconductor device which.