JPH06334133A - Mos semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent the electrostatic breakdown of a gate oxide film by a simple constitution when an overvoltage is applied to a gate electrode regarding a MOS semiconductor device which constitutes a CMOS inverter and regarding its manufacturing method. CONSTITUTION:A MOS semiconductor device is provided with a gate electrode 4 which passes the boundary part between channel regions 8, 9 between source electrodes 10, 11 and a drain electrode 12 and a field oxide film 2 which decides the channel regions 8, 9. The MOS semiconductor device is constituted in such a way that the boundary part between the channel regions 8, 9 on a face on which the gate electrode 4 has been formed and the field oxide film 2 is flat.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device such as a CMOS inverter and a method of manufacturing the same. Since the MOS type semiconductor device has a simple structure and a simple manufacturing method and can be highly integrated, it is often used for devices that do not require high speed.

However, since the MOS type semiconductor device is easily destroyed by static electricity, it is required to surely prevent electrostatic breakdown of the gate oxide film by a simple structure especially when an overvoltage is applied to the gate electrode.

[0003]

2. Description of the Related Art A conventional MOS semiconductor device will be described by taking a CMOS inverter as an example. FIG. 5 shows an equivalent circuit of a CMOS inverter, in which the P-channel transistor 14 connected to the power supply VDD and the N-channel transistor 15 connected to the power supply VSS are turned on / off by the input voltage to the input terminal Vin. The output signal from the output terminal Vout is controlled by switching.

FIG. 6 is a CMO represented by the equivalent circuit of FIG.
It is a figure for demonstrating the actual structure of S inverter,
FIG. 6A is a plan view, and FIG. 6B is A- in FIG.
It is an A'sectional view. The CMOS inverter is shown in FIG.
As shown in, the P-channel region 28 forming the P-channel transistor and the N-channel forming the N-channel transistor are formed.
And a channel region 29.

A gate electrode 24 connected to a wiring 27 serving as an input terminal Vin is commonly formed in each of the P-channel and N-channel regions 28 and 29, and a source electrode 30 connected to a power supply VDD. And a source electrode 31 connected to the power supply VSS and the output terminal V
A drain electrode 32, which is out, is formed commonly in both regions.

FIG. 6 (b) shows a cross section of the gate electrode portion of FIG. 6 (a) to clarify the structure thereof. The P channel region 2 is formed on the silicon substrate 21.
The field oxide film 22 is provided so as to form the 8 and N channel regions 29, and the gate oxide film 23 is provided on the P channel region 28 and the N channel region 29.

A gate electrode 24 is formed so as to communicate with the field oxide film 22 and the gate oxide film 23.
Further, a through hole 26 is partially provided in the upper layer to form an interlayer insulating film 25. A wiring 27 made of aluminum or the like for applying an input voltage is connected to the gate electrode 24 through a through hole 26.

In the CMOS inverter having the above-described structure, by applying a predetermined voltage from the wiring 27 to the gate electrode 24, either one of the P-channel transistor and the N-channel transistor is brought into the conductive state, and the output terminal Vout is supplied. It controls the presence or absence of output signals. However, when an overvoltage is applied to the gate electrode, electric charges are concentrated on the step portion formed by the field oxide film, and the gate oxide film under the charge may be electrostatically destroyed.

In order to prevent such electrostatic breakdown of the gate oxide film, a protection circuit 33 is provided as shown in FIG.
A MOS inverter is used. This is because the first diode 34 is connected between the input terminal Vin and the power supply VDD in the forward direction when viewed from the input terminal Vin side, and the second diode is connected in the reverse direction between the input terminal Vin and the ground VSS. By connecting the diode 35, it is possible to prevent an overvoltage from being applied to the gate electrode of the CMOS inverter.

[0010]

As described above, in the MOS semiconductor device shown in FIG. 6, when an overvoltage is applied to the gate electrode 24, a step portion (a portion indicated by a dotted circle) formed by the field oxide film 22 is formed. ), The electric charges are concentrated on the gate oxide film 23) and the gate oxide film 23 thereunder is electrostatically destroyed.

Further, even in the CMOS inverter having the protection circuit 33 as shown in FIG. 7, it is difficult to completely prevent the overvoltage to the gate electrode 24. That is, the parasitic resistance 3 in series with the first and second diodes 34 and 35, respectively.
Since there are 6, 37, between Vin-VDD or Vin
When a surge voltage having a steep rising edge is applied from −V SS to the outside, a large voltage drop occurs at this location due to these parasitic resistors 36 and 37. Due to this voltage drop, electric charges are concentrated on the stepped portion of the gate electrode 24, and electrostatic breakdown of the gate oxide film 23 occurs.

[0012]

According to the present invention for solving the above problems, the channel regions 8 and 9 between the source electrodes 10 and 11 and the drain electrode 12 and the field oxide film 2 that determines the channel regions 8 and 9 are provided. In a MOS semiconductor device having a gate electrode 4 that passes through a boundary between the channel region 8 and the channel region 8 on the surface where the gate electrode 4 is formed,
The boundary between the field oxide film 9 and the field oxide film 2 is flat.

[0013]

According to the present invention as described above, when an overvoltage is applied to the gate electrode, the gate electrode is also flattened due to the flattening of the field oxide film, so that charges are locally applied to a part of the gate electrode. Never concentrate. Therefore, the possibility of electrostatic breakdown of the gate oxide film is reduced.

[0014]

EXAMPLES Examples of the present invention will be described below. Figure 1
1A and 1B are views showing a structure of a CMOS semiconductor device of this embodiment, FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along the line AA ′ of FIG. In this embodiment, the circuit constitutes the CMOS inverter shown in FIG. 5, which has been described in the section of the prior art.

The CMOS inverter has an N-channel transistor and a P-channel transistor which respectively connect a gate electrode, a source electrode, and a drain electrode,
By alternately turning on and off both transistors,
It is configured to control the output signal. In this embodiment, as shown in FIG. 1A, there is a P-channel region 8 that constitutes a P-channel transistor and an N-channel region 9 that constitutes an N-channel transistor. A gate electrode 4 is formed, a source electrode 10 connected to a power supply VDD is formed in the P channel region 8, and a source electrode 11 connected to a power supply VSS is formed in the N channel region 9. Further, the drain electrode 12 commonly connected to the output terminal Vout is provided on the opposite side of the source electrodes 10 and 11 sandwiching the gate electrode 4 in each region.
Are formed.

An aluminum wiring 7 serving as an input terminal Vin is connected to the end of the gate electrode 4. As described above, in the plan view as described with reference to FIG. 1A, this embodiment is the same as the conventional structure. Figure 1 (b)
1A is a sectional view taken along the line AA ′ of FIG. 1A in which a gate electrode 4 is formed, and shows a feature of the present invention.

The P channel region 8 and the N channel region 9 described above are formed on the silicon substrate 1 in an island shape by being divided by the field oxide film 2, and the gate oxide film 3 is formed on each of the channel regions 8 and 9. Has been formed. The gate electrode 4 is formed on the field oxide film 2 and the gate oxide film 3 so as to communicate with each other. The surface on which the gate electrode 4 is formed is flattened in advance to form a flat surface without unevenness. I am doing it. Therefore, the upper gate electrode 4
Is flat with no irregularities. The specific flattening process will be described later.

Further, an interlayer insulating film 5 is formed on the entire surface of the upper layer of the gate electrode 4 so as to partially have a through hole 6 for establishing conduction with the gate electrode 4. And
An aluminum wiring 7 is formed through the through hole 6 which is electrically connected to the gate electrode 4 and serves as the input terminal Vin. As described above, since the surfaces of the field oxide film 2 and the gate oxide film 3 forming the gate electrode 4 are flat, the step difference that causes the concentration of charges is not formed on the gate electrode 4.

Next, a method of manufacturing the MOS type semiconductor device in the above embodiment will be described with reference to FIGS. 2 and 3 are cross-sectional views of the gate electrode portion showing each step of the manufacturing method of this embodiment. First, an island-shaped silicon portion is left by forming a thick field oxide film 2 of about 1 μm in a predetermined field region on the silicon substrate 1 by using a selective oxidation method. The remaining silicon portions become P-channel and N-channel regions 8 and 9, respectively.

In the P channel region 8 and the N channel region 9 as described above, a P channel transistor and an N channel (not shown) are provided.
The channel transistor is manufactured by a known technique. Then, a thin gate oxide film 3 of about 0.02 μm is formed on each of the P-channel region 8 and the N-channel region 9 in which the P-channel transistor and the N-channel transistor are formed. [FIG. 2A] Although not shown, when forming the gate oxide film 3, a film having a similar thickness is actually formed on the field oxide film 2. This is the same oxide film and does not hinder the function of the field oxide film 2, so that it remains as it is.

Next, after applying a resist on the entire surface from the state shown in FIG. 2A, a P channel region 8 and an N channel region 9 are formed.
Between the entire area of the field oxide film and the inner portions of the field oxide film at both ends of each of the channel regions 8 and 9, that is, by removing only the resist of the portion of the field oxide film where the gate electrode is formed. Mask 1
3 is formed. [FIG. 2B] By performing etching using the resist mask 13 thus formed, a predetermined region of the field oxide film 2 is removed by a predetermined thickness. In this case, the etching thickness is set such that the surface of the field oxide film 2 after etching is at the same height as the surface of the gate oxide film 3, and the surfaces of the field oxide film 2 and the gate oxide film 3 are made flat. After etching, the resist mask is removed. [FIG. 2 (c)] Incidentally, when the oxide film is etched at room temperature, there is a direct proportional relationship between the etching film thickness and the etching time. For example, as shown in the graph of FIG. It takes 1 minute to do. By setting a predetermined etching time in consideration of this relationship, it is possible to easily perform the planarization process. In this example, 0.4 μm
That is, in order to remove a film thickness of about 4000Å, an etching time of about 80 seconds is required.

After that, polysilicon is applied to the entire surface to a thickness of about 0.03 μm, and the gate electrode 4 is formed by leaving the polysilicon only in a predetermined portion by using a normal photolithography technique. [FIG. 3 (d)] In this case, the gate electrode 4 is in a state of being buried in the recess formed in the previous planarization step, but the resist mask used here is set to be smaller than the recess.
The polysilicon is etched just inside the recess.
Therefore, although not shown in the drawing, the formed gate electrode 4 actually has a gap without being in close contact with the wall portion of the recess.

By adopting the above method, the gate electrode 4 can be formed only on the flat portion. Then, P is formed so as to have a through hole 6 in a part on the gate electrode 4.
The interlayer insulating film 5 of about 1 μm is formed by SG. [FIG. 3 (e)] Finally, after applying aluminum having a thickness of about 0.05 μm to the entire surface, using the usual photolithography technique,
An aluminum wiring 7 that is connected to the gate electrode 4 through the through hole 6 is formed. [FIG. 3 (f)] By the method as described above, a CMOS inverter having a flat gate electrode can be realized.

Although the CMOS inverter in this embodiment has a structure like the equivalent circuit shown in FIG. 5, if the protection circuit 33 shown in FIG. 7 is provided, the gate oxide film can be more reliably destroyed. Can be prevented. Further, although the CMOS inverter has been described as an example in the present embodiment, the present invention is not limited to this and can be applied to all MOS type semiconductor devices.

[0025]

According to the present invention, since the gate electrode formed in the upper layer is flat by flattening the field oxide film, even when an overvoltage is applied to the gate electrode,
The electric charges are not locally concentrated on a part of the gate electrode. Therefore, it is possible to prevent electrostatic breakdown of the gate oxide film, which is caused by local concentration of charges.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing a MOS semiconductor device of the present invention.

FIG. 2 is a sectional view (1) for explaining the method for manufacturing the MOS semiconductor device of the present invention.

FIG. 3 is a sectional view (2) for explaining the method of manufacturing the MOS semiconductor device of the present invention.

FIG. 4 is a graph showing etching characteristics of a field oxide film according to the present invention.

FIG. 5 is an equivalent circuit of a conventionally used CMOS inverter.

6A and 6B are a plan view and a cross-sectional view showing a conventional MOS semiconductor device.

FIG. 7 is a CM including a protection circuit that has been conventionally used.
It is an equivalent circuit of an OS inverter.

Claims (2)

[Claims] 1. A boundary between a channel region (8, 9) between a source electrode (10, 11) and a drain electrode (12) and a field oxide film (2) defining the channel region (8, 9). M having a gate electrode (4) passing through
In the OS type semiconductor device, the boundary between the channel region (8, 9) and the field oxide film (2) on the surface where the gate electrode (4) is formed is flat. Semiconductor device. 2. A boundary between a channel region (8, 9) between a source electrode (10, 11) and a drain electrode (12) and a field oxide film (2) defining the channel region (8, 9). M having a gate electrode (4) passing through
In the method of manufacturing an OS type semiconductor device, a first step of forming a field oxide film (2) for determining a channel region (8, 9) on a semiconductor substrate (1), the channel region (8, 9) ), A gate oxide film (3) is formed on a part of the gate oxide film (3), and the boundary portion between the field oxide film (2) and the channel region (8, 9) is removed by etching. Step 2, a third step of forming a gate electrode (4) on the field oxide film (2) and the gate oxide film (3) so as to pass through the flattened boundary portion, and an interlayer insulating film ( And a fourth step of forming an input voltage applying wiring (7) connected to the gate electrode (4) through the through hole (6) of 5). Manufacturing method.