JPH06332727A - Interruption requesting method - Google Patents

Abstract

PURPOSE:To make it unnecessary for a processor to write its own ID each time by allowing a processing system which issues an interrupting request to identify and store the processor which writes a signal for permitting the interrupting request based on the protocol of a bus. CONSTITUTION:When a processor 1n being one of processors 1a-1c transmits a bus using request signal to a bus arbiter 4, and the bus arbiter 4 transmits a usage permission signal, a DMA control circuit 3 receives the content, and specifies the processor 1n which is permitted to use the bus. Then, the DMA control circuit 3 judges whether or not the processor 1n writes a signal for permitting the interrupting request when a specific interrupting factor (m) is generated in an interruption accepting register 3a, and sets a code for specifying the interrupting factor (m) of an interruption ID register 3b as 1 when the signal is written, and stores a number (n) being the ID of the processor 1n. It is not necessary for the processor to write its own ID in the processing system which issues the interrupting request each time, and it is possible to save writing one time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt request method for a system (multiprocessor system) having a plurality of processing systems that permit interrupt requests.

[0002]

2. Description of the Related Art A direct memory access (DMA) system including a multiprocessor as shown in FIG. 3 is assumed. In the same system, a processing system that issues an interrupt request, for example, a DMA control circuit
When a change in state, elapse of a predetermined time, etc.) occurs, an interrupt request is issued to the processor that receives the interrupt request. At this time, since it is necessary to decide in advance which processor to interrupt, in preparation for this case, each processor writes an interrupt enable factor into a predetermined area of the DMA control circuit and has its own ID (identification number). ) Also writes.

When a specific interrupt factor actually occurs, the DMA control circuit specifies the interrupt request destination corresponding to the factor and issues an interrupt request to the processor.

[0004]

However, in the above-mentioned method, the processing system that receives the interrupt request, that is, the processor needs to write its own ID to the processing system that issues the interrupt request each time. For this reason, there arises a disadvantage that the interrupt enable factor and the ID must be written twice.

In particular, when the processing system that accepts interrupt processing changes frequently in a multiprocessor system, even if the time required for one writing (500 nsec to 1 μsec) is small, the number of writing increases, and As a result, a lot of time is spent on writing, resulting in an increase in bus traffic, which is a problem.

Therefore, an object of the present invention is to solve the above-mentioned technical problems, and a processing system which accepts an interrupt request does not need to write its own ID to the processing system which issues an interrupt request each time. It is to provide a request method.

[0007]

According to a first aspect of the present invention, there is provided an interrupt request method, wherein a processor, which is a processing system permitting an interrupt request, interrupts a signal permitting an interrupt request. When writing to a predetermined area of the processing system that issues a request, the processing system that issues an interrupt request identifies and stores the processor that wrote the request based on the bus protocol, and when an interrupt factor occurs, This is a method of issuing an interrupt request to the identified processor.

[0008]

According to the above configuration, the processing system which permits the interrupt request performs a process of writing its own ID in the processing system which issues the interrupt request when writing a signal permitting the interrupt request. You don't have to.

[0009]

Embodiments will be described in detail below with reference to the accompanying drawings showing embodiments. The system of FIG. 1 has a plurality of processors 1a, 1
b, 1c, ... And a plurality of memories 2a, 2b, 2c ,.
, A bus arbiter 4 that adjusts the bus use right of the processors 1a, 1b, 1c, ... And a DMA control circuit 3.
The interrupt acceptance register 3a for storing the interrupt enable signals from a, 1b, 1c, ... And the IDs of the processors 1a, 1b, 1c, ... corresponding to the interrupt enable signals are stored for each interrupt factor. And an interrupt ID register 3b.

The DMA control circuit 3 functions as a processing system for issuing an interrupt request, and the processor 1
, a, 1b, 1c, ... Each function as a processing system that permits an interrupt request. The interrupt control procedure by the above system will be described with reference to the flowchart (FIG. 2).

In the above system, any one of the processors 1a, 1b, 1c, ... (Nth processor 1n
When the bus arbiter 4 sends a bus use request signal to the bus arbiter 4 and the bus arbiter 4 sends a use permission signal, DM
The A control circuit 3 listens to the contents (step S
1) Specify the processor 1n permitted to use the bus (step S2).

Then, it is judged whether the processor 1n has written a signal for permitting an interrupt request into the interrupt acceptance register 3a when a specific interrupt factor m occurs (step S3). When it is written in the interrupt acceptance register 3a, the code for specifying the interrupt factor m in the interrupt ID register 3b is set to 1 and the number n which is the ID of the processor 1n is stored (step S4).

When the interrupt factor m occurs due to the termination of DMA or the like (step S5), an interrupt request is issued to the processor 1n having the ID (step S6). By adopting the above procedure, the processors 1a, 1
Even if b, 1c, ... Do not write their own ID in the register, the DMA control circuit 3 issues the interrupt permission to the processor 1
Since a, 1b, 1c, ... Can be specified, one writing can be saved.

The present invention is not limited to the above embodiment. For example, in the embodiment, the processing system that issues the interrupt request was the DMA control circuit 3, but other processing systems,
For example, it may be an I / O circuit that interfaces with a memory or the like.

[0015]

As described above, according to the interrupt request method of the present invention, the processing system that issues an interrupt request monitors the bus arbitration to identify the processing system that receives the interrupt request, that is, the processor. it can. Therefore, the processor does not need to write its own ID to the processing system that issues the interrupt request each time, and the writing can be saved once.

Therefore, in a system with a large number of writes, the time spent for writing is reduced as a whole,
As a result, the effect of improving the bus usage efficiency can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an interrupt request method including a plurality of processors, a plurality of memories, a bus arbiter, and a DMA control circuit.

FIG. 2 is a flowchart outlining an interrupt operation procedure of the system.

FIG. 3 illustrates a DMA (direct memory) including a multiprocessor.
access) system configuration diagram.

[Explanation of symbols]

 1a, 1b, 1c Processor 2a, 2b, 2c Memory 3 DMA control circuit 3a Interrupt acceptance register 3b Interrupt ID register 4 Bus arbiter

Claims (1)

[Claims] 1. A system in which a plurality of processors, which are processing systems that permit interrupt requests, a processing system that issues interrupt requests, and a bus arbiter that adjusts the bus usage right of the processors, are coupled by a bus. When a signal that allows an interrupt request is written in a predetermined area of the processing system that issues an interrupt request, the processing system that issues the interrupt request identifies the processor that wrote the signal based on the bus protocol. A method of requesting an interrupt, characterized by storing and issuing an interrupt request to the identified processor when an interrupt factor occurs.