JPH06326932A - Solid state image pickup element and its driving method - Google Patents

Abstract

PURPOSE:To select optional shutter time by connecting the 1st control gate between respective photodiodes and connecting the 2nd control gate between one end of a photodiode string and an overflow drain area. CONSTITUTION:A platinum silicide layer 8 is formed on the surface of a p-type silicone base 1. An n-type diffusion layer is arranged on the periphery of the layer 8. An n<+> type source area 5 is formed so as to come into contact with the layer 8. Thus respective photoelectric conversion elements are arranged like a string while being mutually insulated by a channel stopper 2. On the other hand, a vertical CCD register is arranged in parallel with the photoelectric conversion element string. The 1st control gate (a control gate area 7 and the 1st control electrode 12-11) is connected between respective photodiodes and the 2nd control gate (the area 7 and the 2nd control gate electrode 12-2) is connected between one end of the photodiode string and an overdrain area 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a driving method thereof.

[0002]

2. Description of the Related Art A conventional solid-state image pickup device and its driving method will be described with reference to examples.

FIG. 8 is a plan view showing a conventional interline charge-coupled solid-state image pickup device, and FIG. 9 is a time chart when the solid-state image pickup device shown in FIG. 8 is operated as a shutter in interlace drive of frame accumulation.

This conventional example has a Schottky photodiode as a photoelectric conversion element.

A platinum silicide layer 8 is formed on the surface of a p-type silicon substrate. An n-type diffusion layer 4 (guard ring) is provided around the platinum silicide layer 8. Further, n + type source region 5 is provided in contact with platinum silicide layer 8. Such photoelectric conversion elements are arranged in rows and insulated from each other by the channel stopper 2. Further, a vertical CCD register is arranged in parallel with the photoelectric conversion element array. The vertical CCD register has an n-type buried channel 6 and
The transfer electrode group includes transfer electrode groups, and the transfer electrode groups are configured by alternately arranging first transfer electrodes and second transfer electrodes. 11
-1C and 11-3C are first transfer electrodes (second layer polysilicon film (in the case shown) or first layer polysilicon film), and 11-2C and 11-4C are second transfer electrodes (second layer). 1
It is a layer polysilicon film (in the illustrated case) or a second layer polysilicon film). The signal charges accumulated in the photoelectric conversion element are read out to the vertical CCD register via the transfer gate (the transfer gate region 3 and a part of the second transfer electrode) and transferred in the vertical direction. Reference numeral 9 is an overflow drain region for sweeping out electric charges, and 12 is a control gate electrode for controlling the timing for sweeping out electric charges.

Referring to FIG. 9, the photodiode stages to be read out for each field are switched between an odd stage and an even stage. When a ternary pulse is applied to the vertical CCD register, the transfer gate becomes conductive when the level is high, and the charge of the photodiode is read out. The voltages applied to the even-numbered and odd-numbered photodiodes are φV1, φV3, and the voltage applied to the control gate electrode 12 is φCG. By turning φV3 to high level at timing t1, the signal charges accumulated in the odd-numbered photodiodes are read out to the vertical CCD register, and then transferred at high speed in the direction of the overflow drain region 9 in period T1, and φCG is set to high level. Then, it is swept out through the control gate (12) which is in a conductive state.
During this period, the photodiode is accumulating charge, and at time t2, φV3 is set to a high level to read the charge into the vertical CCD register, and the output is taken out by the normal transfer in the period T2. The shutter period is the time from t1A to t2. The reading of the output of the even-numbered photodiode is performed in the next field, but the operation is the same except that φV3 is replaced with φV1 in the above description.

FIG. 10 is a plan view showing another conventional solid-state image pickup device, and FIG. 11 is a time chart when the solid-state image pickup device shown in FIG.

In this conventional example, each photodiode is connected to the overflow drain region 9 via the control gate. The control gate electrode 16-1 (connected to the control gate electrode wiring 17-1) is arranged adjacent to the even-numbered photodiodes,
Adjacent to the odd-numbered photodiodes, the control gate electrode 16-2 (control gate electrode wiring 17-2
Is connected). 7a is a control gate region.

Referring to FIG. 11, the applied pulses for reading the even-numbered and odd-numbered photodiodes are φV1 and φV3, respectively, and the voltages applied to the control gates of the corresponding photodiodes are even and odd-numbered, respectively. Let φCG1 and φCG3. Φ at timing t1
With CG1 at a high level, the charges of the even-numbered photodiodes are swept out to the overflow drain 9, and the charges are accumulated from t2. By setting φV1 to a high level at t3, the data is read out to the vertical CCD register and the output is taken out by normal transfer. The shutter period is t2 to t3. The same applies to reading of odd-numbered stages.

The case where the electric charge of one pixel is directly output has been described above. However, as shown in FIG. 12, in the interlace drive of field accumulation, two vertical shift registers are used.
It is also possible to add the charges of the pixels. The electric charges of the even-numbered photodiodes are read at t1, transferred to the vertical CCD register adjacent to the odd-numbered photodiodes by t2, and the electric charges of the odd-numbered photodiodes are read and added by the vertical CCD register at t2.

[0011]

In the conventional example described with reference to FIGS. 8 and 9, the high-speed transfer for sweeping out charges cannot be arbitrarily performed at high speed in consideration of deterioration of transfer efficiency.
It must be done within the vertical blanking period and cannot be made longer than that. That is, the shutter time cannot be arbitrarily selected. 10 and 1
In the conventional example described with reference to FIG. 1, the shutter time can be arbitrarily selected, but it is necessary to provide a control gate and an overflow drain in the unit pixel, and further, in order to make the potentials of the photodiodes at reset uniform, It is necessary to secure a certain size for the size of, and this leads to a decrease in the fill factor. Further, in the driving method in which the charges of two pixels are added as in the interlacing operation of field accumulation, the transfer gate provided for each photodiode is one of the causes of the decrease in the fill factor.

[0012]

A solid-state image pickup device according to the first invention of the present application comprises a plurality of photoelectric conversion element arrays in which a plurality of photoelectric conversion elements are arranged in a row, and a vertical scanning register coupled to the photoelectric conversion element arrays. A first control gate provided between the two photoelectric conversion elements adjacent to each other in the column direction, an overflow drain provided near one end of the photoelectric conversion element row, and a photoelectric conversion element at the one end. Second provided between the overflow drain and the overflow drain
It has a control gate of.

According to a second aspect of the present invention, there is provided a method of driving a solid-state image pickup device, wherein a channel potential of the second control gate of the solid-state image pickup device of the first invention is set to a channel potential of the first control gate at a predetermined timing. A means for resetting the potential of the photoelectric conversion element by raising the potential of the overflow drain to a value higher than that of the overflow drain.

In the solid-state image pickup device of the third invention of the present application, a plurality of photoelectric conversion device arrays in which a plurality of photoelectric conversion devices are arranged in a row and a photoelectric conversion device of the photoelectric conversion device array are provided with transfer gates every other. It has a vertical scanning register coupled via a photoelectric conversion element array and a control gate provided between adjacent photoelectric conversion elements of the photoelectric conversion element array.

According to a fourth aspect of the present invention, there is provided a method for driving a solid-state image pickup device, wherein the control gates of the solid-state image pickup device according to the third aspect of the invention are made conductive at every other predetermined timing so that two adjacent photoelectric conversion elements are formed. It has a means for adding the accumulated charges.

[0016]

According to the first and second aspects of the invention, the first control gate between the photoelectric conversion elements and the second control gate between the photoelectric conversion element and the overflow drain are all brought into conduction, whereby the photoelectric conversion elements are accumulated. The generated charge can be swept to the overflow drain.
Since the vertical scanning register is not used at the time of sweeping out the charges, the shutter time is arbitrary, and since the overflow drain is not formed in the unit pixel, the fill factor is not reduced. Furthermore, since the potential of the photodiode at the time of reset is aligned with the channel potential of the second control gate, the dimensional accuracy of the first control gate between the photoelectric conversion elements can be relaxed, and the fill factor is improved. it can.

According to the third and fourth aspects of the invention, by setting every other control gate between the photoelectric conversion elements to be in the conductive state, the charge between the adjacent pixels can be added by the photoelectric conversion elements and all the pixels can be added. The fill factor can be improved without the need to form a transfer gate.

[0018]

EXAMPLE An example of the first invention will now be specifically described. FIG. 1 is a plan view showing an embodiment of the solid-state imaging device of the first invention, FIG. 2 (a) is an enlarged cross-sectional view taken along the line AA of FIG. 1, and FIG. 2 (b) is a line BB of FIG. It is a line expansion sectional view.

This embodiment has a Schottky photodiode as a photoelectric conversion element.

A platinum silicide layer 8 is formed on the surface of the p-type silicon substrate 1. An n-type diffusion layer 4 (guard ring) is provided around the platinum silicide layer 8. Further, n ⁺ type source region 5 is provided in contact with platinum silicide layer 8. Such photoelectric conversion elements are arranged in rows and insulated from each other by the channel stopper 2. Further, a vertical CCD register is arranged in parallel with the photoelectric conversion element array. The vertical CCD register has an n-type buried channel 6
And a transfer electrode group, and the transfer electrode group is configured by alternately arranging first transfer electrodes and second transfer electrodes.
11-1 and 11-3 are the first transfer electrodes, and 11-
2, 11-4 are second transfer electrodes.

The difference from the conventional solid-state imaging device shown in FIG. 8 is that a first control gate (comprising a control gate region 7 and first control gate electrodes 12-11 ...) Is provided between photodiodes. The second control gate (consisting of the control gate region 7 and the second control gate electrode 12-2) is provided between one end of the photodiode array and the overflow drain region 9.

The first transfer electrodes 11-1 and 11-3 are the first
Layer polysilicon film, first control gate electrode 12
-11, 12-12, ... Are second-layer polysilicon films, second
The transfer electrodes 11-2 and 11-4 are formed of a third-layer polysilicon film. The first and second control gate electrode wirings and the second transfer electrode wirings pass through the channel stopper between the photodiodes and are drawn out in the horizontal direction, and the first transfer electrode wirings 15-1 and 15-3 are on the vertical scanning register. Through in the vertical direction. First transfer electrode wiring 15-
1, 15-3 are the interlayer insulating film 14 and the silicon oxide film 1.
3 are respectively connected to the first transfer electrodes 11-1 and 11-3 via the connection hole C1 penetrating therethrough. Reference numeral 10 is a silicon oxide film between the surface of the silicon substrate and the first-layer polysilicon film. Further, although the case where the first and second control gate regions 7 are formed in a part of the element isolation region which is in contact with the long side of the photodiode is shown, the entire element isolation region described above is used as the control gate region. Of course it is possible. Such element isolation is called field shield isolation, but since the element isolation width can be made narrower than that by LOCOS oxidation, the fill factor is improved. Although the present embodiment has been described with respect to the case of the charge coupled device, it can be applied to a MOS type image pickup device and the like. This is common to the following second to fourth inventions.

FIG. 3 is a plan view showing a modification of this embodiment.

The first transfer electrodes 11-1a, 11-3a,
Second transfer electrodes 11-2a, 11-4a, first control gate electrode 16-1, second control electrode 1
The wiring to 6-2 is made of metal such as aluminum and is connected by the active area contact C1 or C2, and the metal wiring 15-1a, 15-2, 15-3a, 15-4, 15 is connected.
-6, 15-71, 15-72, ... Draw out in the horizontal direction through the photodiodes and the like. This modification can be applied to a device that irradiates the back surface, such as an infrared image sensor, but has low wiring resistance and is suitable for high-speed operation.

Next, an embodiment of the method for driving the solid-state image pickup device of the first invention, which is the second invention, will be described with reference to FIGS. 4 and 5.

FIG. 4 shows a time chart of the applied voltage, and FIG. 5 shows the potential in the photodiode column direction at each time.

In the case of the charge coupled device, the transfer electrode of the vertical scanning register connected to the transfer gate region is formed to include the transfer gate electrode, and the transfer gate is controlled by applying a ternary pulse to the transfer electrode. At a high level, the transfer gate becomes conductive and the charges of the photodiode can be read out to the vertical scanning register. An applied pulse for reading the photodiodes of even and odd stages is φV, respectively.
1, φV3, φCG _FD and φCG _OFD are voltages applied to the first and second control gate electrodes, and φOFD is a voltage applied to the overflow drain region.
At t1, φCG _FD and φCG _OFD are set to a high level to bring the first and second control gates into a conductive state, so that the charges accumulated in the photodiodes are swept out to the overflow drain region 9 through the photodiode rows. At t2, φOFD is set to low level to inject charges into the photodiode, and at t3, φOFD is set to high level. At this time, the channel potential of the second control gate connected to the overflow drain is prevented from becoming higher than the channel potential of the first control gate between the photodiodes, and is set higher than the potential of the overflow drain region 9 to photo. The diode potential is reset to the former channel potential. The channel potential is controlled by the voltage applied to the gate electrode and the impurity concentration of the channel. Since the second control gate connected to the overflow drain is located around the image area, the size of the second control gate is not so limited, and the size variation due to the process can be suppressed. Therefore, it is possible to reset all the photodiodes to the same potential. At t4, the first and second control gates are closed, and at the same time, the charges generated by photoelectric conversion are accumulated in the photodiode, and at t5, the transfer gate is turned on and the charges of the even-numbered photodiodes are read to the vertical scanning register. ing. t4 to t5
Is the shutter time, but that time can be freely selected except the time required for sweeping out and resetting the charges. The same applies to reading out the photodiodes in odd stages. Although the above-mentioned embodiment shows the case of the frame accumulation, it can be similarly applied to the case of the field accumulation.

Next, an embodiment of the third invention will be described. FIG. 6 is a plan view showing an embodiment of the solid-state image sensor of the third invention.

The control gate 51 (consisting of the control gate electrode 12a and the control gate region 7) includes the photodiode 101 (n-type diffusion layer 4a, platinum silicide layer 8a) and the photodiode 10.
2 (n-type diffusion layer 4b, platinum silicide layer 8b), 103
And 104, ..., and the second control gate 52
The photodiodes 102 and 103, 104 and 101, ... Are connected to each other (composed of the second control gate electrode 12b and the control gate region 7).
This embodiment is different from the conventional example shown in FIGS. 8 and 10 in that photodiodes are connected via control gates. As described with reference to FIG. 12, in the field storage interlace method, addition of pixels in odd-numbered stages and even-numbered stages is performed in the vertical scanning register, but in the case of this embodiment, it is performed in photodiodes. Transfer gate (first transfer electrode 11-
1, every other transfer gate region 3) is formed. The shape of the photodiode differs between the pixel with the transfer gate and the pixel without the transfer gate, but the area is the same in order to maintain vertical resolution. Since the reset gate potential of the photodiode is determined by the channel potential of the transfer gate, it is necessary to secure a certain level in order to suppress the variation. On the other hand, if the channel potential of the control gate between the photodiodes is set higher than the channel potential of the transfer gate, the two connected photodiodes are reset to the same potential. Therefore, the variation does not matter. That is, as the transfer gates decrease, the filter factor increases. In FIG. 6, the control gate is formed in a part of the element isolation region in contact with the long side of the photodiode, but it is of course possible to use the entire element isolation region as the control gate. Such element isolation is called field shield isolation, but since the element isolation width can be made narrower than that by LOCOS oxidation,
The filter factor is improved.

Next, an embodiment of a method of driving the solid-state image pickup device of the third invention, which is the fourth invention, will be described with reference to FIG. FIG. 7 shows the timing of the applied voltage.

In the case of the charge coupled device, the transfer electrode (11-1) of the vertical scanning register connected to the transfer gate
Is formed so as to include the transfer gate electrode, and the transfer gate is controlled by applying a ternary pulse to the transfer electrode. When the transfer gate is at a high level, the transfer gate becomes conductive and the charge of the photodiode is vertically It can be read into the shift register. The applied voltage for reading out the charges from the photodiodes 102, 104, ... Is φV1, and the control gate electrodes 12a, 12b.
The voltages to be applied to ΦCG1 and ΦCG2, respectively.
When φCG2 is at a high level, φV1 is set to a high level to read charges from all the photodiodes and reset, and at t2, φCG2 is set to a low level to make each photodiode independent, and at t3, φCG1 is set to a high level and the photodiodes 101 are provided. The charges of 102, 103 and 104, ... Are added and read out to the vertical shift register at t4 and all photodiodes are reset. At t5, φCG1 is set to a low level to make each photodiode independent, and at t6, φCG2 is set to a high level to add charges to the photodiodes 102 and 103, 101 and 104, ... And read to the vertical shift register at t7. In this way, φCG1 and φCG2 are alternately set to a high level for each field, and the addition is changed to a combination for performing the field storage interlacing operation. By making the channel potential between the photodiodes higher than the channel potential Vch _TG of the transfer gate while φV1 is at a high level,
The photodiode can be reset to Vch _TG .

In the above description, the four-phase transfer pulses φV1 to φV
No. 4 is not specifically shown because it is known, except for the ternary pulse for reading out the charge from the photodiode, but it will be apparent to those skilled in the art.

[0033]

According to the first and second aspects of the invention, a solid-state imaging device and a driving method thereof can be obtained in which charges accumulated in the photoelectric conversion device can be swept out to the overflow drain through the photoelectric conversion device. Since the charge is swept out without going through the vertical scan register, any shutter time can be selected without being restricted by the sweep time or the vertical blanking time, and since the overflow drain is not formed in the unit pixel, the fill factor can be changed. It does not decrease. Furthermore, since the drive voltage is adjusted so that the electric potential of the photoelectric conversion element at the time of reset is aligned with the channel electric potential of the control gate connected to the overflow drain, the dimensional accuracy of the control gate of the photoelectric conversion element can be relaxed and the fill factor is improved. it can.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the first invention.

2 is an enlarged sectional view taken along the line AA (FIG. 2A) and an enlarged sectional view taken along the line BB of FIG. 1 (FIG. 2B).

FIG. 3 is a plan view showing a modification of the first embodiment of the invention.

FIG. 4 is a time chart for explaining an embodiment of the second invention.

FIG. 5 is a potential diagram for explaining one embodiment of the second invention.

FIG. 6 is a plan view showing an embodiment of the third invention.

FIG. 7 is a time chart for explaining an embodiment of the fourth invention.

FIG. 8 is a plan view showing an example of a conventional solid-state image sensor.

FIG. 9 is a chime chart for explaining an example of a driving method when a shutter operation is performed as an example of a conventional solid-state imaging device.

FIG. 10 is a plan view showing another example of a conventional solid-state image sensor.

FIG. 11 is a chime chart for explaining an example of a driving method when another example of the conventional solid-state imaging device is operated as a shutter.

FIG. 12 is a time chart for explaining an example of a driving method when a conventional solid-state imaging device is operated in a field storage interlace mode.

[Explanation of symbols]

1 p-type silicon substrate 2 channel stopper 3 transfer gate region 4, 4a, 4b n-type diffusion layer 5, 5a, 5b n ⁺ type source region 6 n-type buried channel 7, 7a control gate region 8, 8a, 8b platinum silicide layer 9 Overflow drain region 10 Silicon oxide film 11-1, 11-1a, 11-1c, 11-3, 11-
3a, 11-3b, 11-3c 1st transfer electrode 11-2, 11-2a, 11-2c, 11-4, 11-
4a, 11-4c 2nd transfer electrode 12, 12a, 12b Control gate electrode 12-11, 12-3, 12-12, 12-13 1st control gate electrode 12-2, 12-4 2nd control Gate electrode 13 Silicon oxide film 14 Interlayer insulating film 15-1, 15-1a, 15-3, 15-3a 1st
Transfer electrode wiring 15-2, 15-4 second transfer electrode wiring 15-71, 15-72, 15-73 metal wiring 16-1 first control gate electrode 16-2 second control gate electrode 51th 1 control gate 52 2nd control gate 101, 102, 103, 104 Photodiode

Claims (4)

[Claims] 1. A plurality of photoelectric conversion element arrays in which a plurality of photoelectric conversion elements are arranged in a row, a vertical scanning register coupled to the photoelectric conversion element arrays, and between two photoelectric conversion elements adjacent to each other in the column direction. A first control gate provided in each of the photoelectric conversion elements, an overflow drain provided in the vicinity of one end of the photoelectric conversion element array, and a second control provided between the photoelectric conversion element at the one end and the overflow drain. A solid-state imaging device having a gate. 2. A plurality of photoelectric conversion element arrays in which a plurality of photoelectric conversion elements are arranged in a row, a vertical scanning register coupled to the photoelectric conversion element arrays, and between two photoelectric conversion elements adjacent to each other in the column direction. A first control gate provided in each of the photoelectric conversion devices, an overflow drain provided near one end of the photoelectric conversion device array, and a second drain provided between the photoelectric conversion device at the one end and the overflow drain in. In the solid-state imaging device having a control gate, the channel potential of the second control gate is made higher than the potential of the overflow drain without exceeding the channel potential of the first control gate at a predetermined timing, and the photoelectric conversion element is provided. A method for driving a solid-state image sensor, comprising: means for resetting the electric potential of the device. 3. A plurality of photoelectric conversion element arrays in which a plurality of photoelectric conversion elements are arranged in a row, and a vertical scanning register which is coupled to every other photoelectric conversion element of the photoelectric conversion element array via a transfer gate. A solid-state imaging device, comprising: a control gate provided between photoelectric conversion devices adjacent to each other in the photoelectric conversion device array. 4. A plurality of photoelectric conversion element arrays in which a plurality of photoelectric conversion elements are arranged in a row, a vertical register which is coupled to every other photoelectric conversion element of the photoelectric conversion element array via a transfer gate, In a solid-state imaging device having a control gate provided between adjacent photoelectric conversion devices of a photoelectric conversion device array, the control gates are made conductive at every other predetermined timing to form two adjacent photoelectric conversion devices. A method for driving a solid-state image pickup device, comprising a means for adding accumulated charges.