JP2605728B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device.

[Summary of the Invention]

The present invention divides a vertical transfer section composed of a charge-coupled element into a plurality of packets composed of a plurality of and the same number of gate electrode sections, and divides a signal charge obtained in a light-receiving element into one or two light-receiving elements. A so-called self-service that is designed to read out and transfer to predetermined packets among packets
In a scan-type solid-state imaging device, signal charges from a light receiving element to a predetermined packet are read out within a horizontal blanking period, thereby avoiding solid pattern noise caused by supplying a read pulse during a horizontal effective period. It is something that can be done.

[Conventional technology]

Conventionally, a solid-state imaging device as shown in a schematic plan view in FIG. 14 has been proposed.

This solid-state imaging device employs a so-called interline transfer method. In FIG. 14, (1)
Denotes a P-type silicon substrate, and (2) denotes a light receiving element composed of photodiodes formed in a matrix on the surface side of the P-type silicon substrate (1). A corresponding signal charge is generated, and the signal charge is accumulated in each of the light receiving elements (2).

Further, (3) shows a vertical transfer section comprising a charge-coupled device (CCD) vertically arranged for each column of the light receiving element (2). The signal charge stored in the light receiving element (2) is, for example, one field. Each horizontal line is simultaneously read out to the vertical transfer unit (3), and is transferred to the horizontal transfer unit (4) provided on the output side of the vertical transfer unit (3) for each horizontal line. The horizontal transfer section (4) is composed of a charge-coupled device, and converts the signal charges transferred through the vertical transfer section (3) to a signal charge detection section (5) provided on the output side of the horizontal transfer section (4). Transfer to The signal charge detection section (5) is constituted by, for example, a floating diffusion amplifier, detects the signal charge transferred through the horizontal transfer section (4), and converts the signal charge into an electric video signal. I do.
(6) is an output terminal from which this video signal is output.

On the one hand, the solid-state imaging device adopting such an interline transfer method has an advantage of low noise, but on the other hand, the saturation charge amount of the vertical transfer unit (3) is small, so that a high dynamic range is required. The disadvantage was that it could not be obtained. In this case, it is conceivable to increase the dynamic range by increasing the area of the vertical transfer section (3), that is, the channel width. However, in this case, the aperture ratio of the light receiving element (2) decreases, and There has been an inconvenience that the size and resolution of the imaging device cannot be increased.

Therefore, recently, as a solid-state imaging device that solves such a disadvantage, a solid-state imaging device using a so-called charge sweeping method (Image Sensor with a Charge Sweep Device) has been proposed (Technical Report of the Institute of Television Engineers of Japan, February 1985). Published on March 27, Vol. 18, No. 44, TEBS101-6, ED841).

In this solid-state imaging device, the vertical transfer unit is configured by a charge sweeping device, and the vertical transfer unit is used as one large potential well, in which only signal charges accumulated in a single light receiving element are read. It is what we did.

According to such a solid-state imaging device, a large amount of signal can be transferred even when the channel width of the charge sweeping element constituting the vertical transfer unit is narrowed. Can be achieved.

However, in such a solid-state imaging device, all the smear charges generated in the charge sweeping element are mixed with the signal charges and transferred.
r).

Therefore, as a solution to such a problem,
Line / Address / CCD / Image Sensor (Line-Addre)
ss CCD Image Sensor) has been proposed (International Solid State Circuit Conference [Inte] published February 25, 1987).
rnational Solid-State Circuit Conference.ISSCC)
Proceedings).

In this solid-state imaging device, the vertical transfer unit is formed of a charge-coupled device, and a smear charge absorption unit is provided on the output side of the vertical transfer unit. The packet is divided into a plurality of packets each including an electrode portion, a plurality of potential wells are formed in the packet, for example, over three gate electrode portions, and signal charges obtained in one light receiving element are read out to the potential well of the packet. Move the potential well,
The signal charges are transferred to the horizontal transfer unit in packet units.
In this case, a plurality of potential wells formed in a plurality of packets move to the horizontal transfer unit during one horizontal period, but only one of the plurality of potential wells has a signal charge. Used to transfer

Therefore, in this solid-state imaging device, potential wells other than the potential well for transferring signal charges are used to transfer smear charges, and smear charges transferred by potential wells other than the potential well for transferring these signal charges are used. Are swept out to the smear charge absorbing portion to constitute a vertical transfer portion having a high charge transfer capability, and effectively suppress the influence of smear charge generated in the vertical transfer portion.

[Problems to be solved by the invention]

However, in this solid-state imaging device, in order to maintain the periodicity of the movement of the potential well formed in packet units, the reading of the signal charge from the light receiving element to the vertical transfer unit is not necessarily performed every horizontal period. Without
In one horizontal period, the horizontal effective period and the horizontal blanking period are distinguished appropriately. Here, the signal charge is read from the light receiving element to the vertical transfer section by reading a signal having a higher voltage than the clock pulse, for example, from 12 [V] to 15 V, to a read gate section provided between the light receiving element and the vertical transfer section.
This is performed by supplying a read pulse of [V].
For this reason, in this solid-state imaging device in which the signal charge is read from the light receiving element to the vertical transfer unit during the horizontal effective period, that is, while the signal charge detection unit is reading the signal charge, the signal charge detection unit reads the signal charge. During this period, the potential of the substrate fluctuates and a clock pulse is generated, resulting in the inconvenience that fixed pattern noise (appearing as horizontal stripes on the reproduction screen) is generated.

In view of the above, an object of the present invention is to provide a solid-state imaging device that does not generate such fixed pattern noise.

[Means for solving the problem]

A solid-state imaging device according to the present invention includes, as shown in FIGS. 1 to 13, a light receiving element (11) arranged in a matrix in a vertical direction and a horizontal direction on a semiconductor substrate (10). A vertical transfer section (12) for vertically transferring signal charges obtained to the light receiving element (11), and a signal charge for transferring the signal charges to the vertical transfer section (12). Horizontal transfer unit (13) for transferring data in the horizontal direction, a memory unit (20) provided between the output side of the vertical transfer unit (12) and the horizontal transfer unit (13), and the horizontal transfer unit (13). ), And a signal charge detecting section for detecting the signal charges transferred. The vertical transfer section (12) includes a plurality of packets each including a plurality of gate electrode sections G ₁ , G ₂ ‥‥ G _8. P ₁ , P ₂ ‥‥
P ₇ , and the signal charge obtained by the light receiving element (11) is divided into a predetermined packet among the plurality of packets P ₁ , P ₂ ‥‥ P ₇ for each of one or two light receiving elements (11). In a solid-state imaging device in which signal charges are read out and transferred to the horizontal transfer unit (13) via the memory unit (20), the signal charges are transferred to the memory unit (20). And reading of the signal charge from the light receiving element (11) to the predetermined packet and transfer of the signal charge from the memory section (20) to the horizontal transfer section (13) are performed by horizontal blanking. This is done within the period.

[Action]

According to the present invention, the signal charge is read out from the light receiving element (11) into a predetermined packet during the horizontal blanking period. Therefore, the signal charge is detected in the horizontal effective period, that is, the signal charge detection unit (14). During the detection, the potential of the substrate is not fluctuated by the read pulse, the clock pulse is not swung, and the memory section (20) can be stored only when the signal charge is transferred. Only the signal charges read from the light receiving element (11) are accumulated in (20). Therefore, the fixed pattern noise generated by supplying the read pulse during the horizontal effective period can be avoided, and the effect of the smear charge generated in the vertical transfer section (12) can be effectively suppressed.

〔Example〕

Hereinafter, an embodiment of the solid-state imaging device according to the present invention will be described with reference to FIGS.

1 and 2 are a schematic plan view and a schematic partial enlarged plan view, respectively, of the solid-state imaging device according to the present embodiment. In FIGS. 1 and 2, (10) shows that the P-type impurity is relatively thin. A diffused P ^- type silicon substrate, and (11) shows a light receiving element composed of a photodiode. The light receiving element (11)
504 (vertical) x 760 (horizontal) units are provided in a matrix on the surface side of the P ^- type silicon substrate (10).

Further, a vertical transfer section (12) is provided for each column of the light receiving elements (11) via a read gate section (15). The vertical transfer section (12) is composed of a buried channel type charge-coupled device (BCCD) as shown in FIG. That is, an N-type region (16) forming a signal charge transfer path is provided on the surface side of the P-type silicon substrate (10), and an insulating layer (17) made of SiO ₂ is provided on the N-type region (16).
520 gate electrodes g ₁ , g ₂ ‥‥ g ₈ are provided. These gate electrodes g _1, g ₂ ‥‥ g ₈ are each the vertical transfer section (12) is provided in common across and ninth from the 512-th gate electrode g _1, g ₂ ‥‥ g ₈ is one electrode is provided so as to correspond to one light receiving element in the vertical transfer unit (12). The gate electrodes g ₁ , g ₂ ‥‥ g ₈ are supplied with vertical scanning signals φ _V1 , φ _V2 ‥‥ φ _{V8 shown} in FIG.
The ninth to 512th gate electrodes g ₁ , g ₂ ‥‥ g ₈
Are also used as the gate electrodes of the read gate section (15), and the ninth through 521st gate electrodes g
₁ , g ₂ ‥‥ g ₈ are supplied with a signal charge readout pulse φ _{ROG in} addition to the vertical scanning signals φ _V1 , φ _V2 ‥‥ φ _V8 .

This vertical transfer unit (12) is, as shown in FIG.
It is composed of 10 blocks B ₁ , B ₂ ‥‥ B ₁₀ . The first block B ₁ from the ninth block B ₉ here consists respective seven packets _{P 1, P 2 ‥‥ P 7} , 10th block B ₁₀ is composed of two packets P _1, P ₂ You. And
One packet is composed of eight gate electrode portions G ₁ , G ₂ ‥‥ G ₈ .

1 and 2, reference numeral (18) denotes a vertical transfer drive circuit for driving the vertical transfer unit (12), and the vertical transfer drive circuit (18) includes the packets P ₁ , P ₂上述P ₈ ‥‥ P
_It comprises 65 packet driver circuits PD ₁ , PD ₂ ‥‥ PD ₈ ‥‥ PD ₁ , PD ₂ provided corresponding to ₁ and P ₂ . These packet driver circuits PD ₁ , PD ₂ ‥‥ PD ₈ ‥‥
PD ₁ and PD ₂ are vertical scanning signals φ _V1 and φ _{V2 2} shown in FIG. 5, respectively.
It has eight output terminals to output φ _V8.
The output terminals of this book are the gate electrodes g ₁ and g of the corresponding packet, respectively.
₂ ‥‥ g ₈ each connected.

FIG. 6 shows the vertical scanning signals φ _V1 and φ _V2 shown in FIG.
‥‥ phi _V8 is a change in the potentiometer Shan level of the vertical transfer path (16) when it is supplied to the gate electrode _{g 1, g 2 ‥‥ g 8} , second
The portion of the block B ₂ and the third block B ₃ is shown as an example. That is, at T = t ₀ shown in FIG. 5, potential wells extending from the first gate electrode portion G ₁ to the seventh gate electrode portion G ₇ at each packet P ₁ , P ₂ ‥‥ P ₇ as shown in FIG. Is formed. Then, in this potential well is T = t ₁ 6
It changes as shown in the figure, as shown in FIG. 6C at T = t ₂ , and as shown in FIG. 6D at T = t ₀ + 1 / 7H, and the first gate electrode portion of each packet. potential well formed over the seventh gate electrode portion G ₇ from G ₁ is moves from the first gate electrode portion G ₁ packet next to the seventh gate electrode portion G _7. Therefore, during one horizontal period (H), it moves by seven packets, that is, by one block. The solid-state imaging device according to the present embodiment intends to transfer signal charges and smear charges by utilizing the movement of the potential well.

1 and 2, reference numeral (19) denotes a line address shift register for supplying a signal charge read pulse φ _ROG to the read gate section (15).
The address shift register (19) has 504 output terminals, and these output terminals are the ninth to 512th gate electrodes g provided for the light receiving element (11).
₁ , g ₂ ‥‥ g ₈ are connected. For example, as shown in FIG. 5, the signal charge readout pulse φ _ROG has a voltage value higher than the high level voltage of the vertical scanning signal, and this readout pulse φ _ROG is supplied to the read gate unit (15). Can read the signal charges accumulated in the light receiving element (11) to the vertical transfer path (16). The line address shift register (19) supplies a signal charge read pulse φ _ROG to the gates G ₁ , G ₂ ‥‥ G ₈ so that a so-called field read can be performed. The supply of the signal charge readout pulse φ _ROG is performed during the horizontal blanking period, for example, at T = t ₀ in FIG.

In this example, a horizontal transfer section (13) is provided on the output side of the vertical transfer section (12) via a memory section (20) and a vertical read gate section (21). As shown in FIG. 3, the memory unit (20) includes an N ^- type region (22) forming a memory gate region and an N ^- type region forming a memory region following the N-type region (16) of the vertical transfer unit (12). provided with a region (23), these N ^-
Electrodes (24) and (25) are provided on the mold region (22) and the N-type region (23) via an insulating layer (17). These electrodes (24) and (25) are supplied with a memory control signal φ _MC . Vertical read gate (21)
, Following the N-type region (23) of the memory unit (20) N ^- provided with a type region (26), the N ^- type region (26) via an insulating layer (17) on the electrode (27) Is provided. The vertical read gate signal φ _VOG is supplied to this electrode (27).

Here, when the signal charge is not transferred to the memory section (20), a low level voltage is supplied to its electrode as shown in FIG. 7A, and a potential barrier is formed in the memory gate area (22). To the off state (OFF), but as shown in FIG. 7B, the signal charge Qsig is changed to the first block B _1.
First when the first gate electrode portion G ₁ of the packet P ₁ comes transferred to the seventh gate electrode portion G ₇ of the electrode (24) and (25)
A high-level voltage is supplied to the memory section (20), the memory section (20) is turned on (ON), and the potential level of the memory gate area (22) and the memory area (23) is changed to a high level voltage. By making the potential deeper than the potential level of the path (16), the signal charges transferred as shown in FIG. 7E through the processes shown in FIGS. 7C and 7D are stored in the memory area (23). When the accumulation is completed, the seventh
As shown in FIG. F, a low level voltage is supplied to the memory electrodes (24) and (25), and the memory section (20) is turned off (OF
F) state, the potential level of the memory gate area (22) is made shallower than the potential level of the signal charge transfer path (16) to which the high-level voltage is supplied, and the signal charges accumulated in the memory area (23) Hold Qsig. Then, during the horizontal blanking period, a high-level voltage is supplied to the gate electrode (27) of the vertical read gate section (21), and the vertical read gate section (21) is turned on (ON), and the memory area ( The signal charges accumulated and held in 23) are transferred to the horizontal transfer section (13).

The horizontal transfer section (13) is composed of a so-called two-phase drive type charge-coupled device which is well known in the art. In FIG. 2, S
_t1 and T _r1 is a storage electrode and a transfer electrode one of the drive pulses phi _H1 of each 2-phase drive pulses phi _H1 and _H2 are supplied, S _t2 and T _r2 are each other drive pulse phi _H2 is supplied A storage electrode and a transfer electrode.

The signal charge detection unit (1) is connected to the output side of the horizontal transfer unit (13).
4) is provided. The signal charge detection section (14) is constituted by a floating diffusion amplifier, detects a signal charge transferred to the horizontal transfer section (13), and converts the signal charge into an electric video signal. Incidentally, (28) is an output terminal to which this video signal is output.

In the present embodiment, the first block first first gate electrode portion G ₃ packets P ₁ of B ₁ of the vertical transfer portion (12) 6
Smear drain region via smear control gate portion (29) adjacent to the gate electrode unit G ₆ (30) is provided. Smear control gate (29),
As shown in FIG. 8, a P-type region (31) is provided adjacent to an N-type region (16) forming a vertical transfer path, and a gate is formed on the P-type region (31) via an insulating layer (17). It is constituted by providing an electrode (32). This gate electrode (32)
A control gate signal φ _SCG is supplied. The smear drain region (30) is adjacent to the P-type region (31) of the smear control gate portion (29), and is an N-type region (3).
3) is provided. Here smear control gate section (29), FIG. 9 signal charge Qsig as shown in A third gate electrode portion G ₃ sixth gate electrode of the first packet P ₁ of the first block B ₁ while passing through the G ₆ is low level voltage is supplied to the gate electrode (32),
Make the potential level shallower than the potential level of the signal charge transfer section (16) to which the high level signal is supplied, and turn it off (OFF) so that the signal charge Qsig is not swept out to the smear / drain region (30). To Further, the signal charge Qsig is between the first third gate electrode portion G ₃ packets P ₁ of the first block B ₁ is not being passed through the sixth gate electrode portion G _6, the high level voltage to the gate electrode (32) As shown in FIG. 9B, the potential level is made deeper than the potential level of the signal charge transfer path (16) to which the high-level signal is supplied, and the potential is turned on.
The transferred smear charge Qsm can be swept out to the smear / drain region (30). In FIG. 2,
(34) is a channel stopper region.

Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIGS.

FIG. 10 is a diagram showing the timing at which the signal charge readout pulse φ _ROG is supplied, and FIG. 11 schematically shows the transfer of the signal charge at the time of the odd field.
In FIG. 11, the solid line X indicates the potential level of the vertical transfer path (16) at the time when the signal charge readout pulse φ _ROG is supplied (at time T = t _{0 in} FIG. 5), and the hatched portion Indicates a signal charge read at that time, and a portion indicated by a dotted pattern indicates a signal charge which has already been read and is being transferred. Q _k , _{k + 1}
Represents signal charges read from the k-th horizontal line and the (k + 1) -th horizontal line.

First, in the first horizontal period (H) of the odd field, no signal charges are read out, and only the vertical scanning signals φ _v1 , φ _v2 ‥‥ φ _v3 shown in FIG. 5 are applied to the gate electrodes g ₁ , g ₂ ‥‥ g. Supplied to ₈ . Therefore, each packet P _1, P ₂ ‥‥ P ₇ potential well extending over the first gate electrode portion G ₁ to the seventh gate electrode portion G ₇ are formed as shown in FIG. 6, which is the output side To one block. At this time, the potential well transfers only the smear charge.
Since the memory section (20) is turned off (OFF) and the smear control gate section (29) is turned on (ON), the transferred smear charge is swept out to the smear / drain region. Subsequent second horizontal period, third horizontal period
(4) The same operation is performed in the eighth horizontal period. As described above, only the transfer and the sweep of the smear charge generated in the signal charge transfer path (16) are performed during the first to eighth horizontal periods.

In the ninth horizontal period, as shown in FIG. 10, the first horizontal blanking period, that is, T = T in FIG.
Line address shift register at time t ₀ (19)
To the first gate electrode of the second packet P ₂ of the first block B ₁
g ₁ , that is, a signal charge read pulse φ _ROG is supplied to the gate electrode corresponding to the light receiving element (11) on the first horizontal line,
As shown in FIG. 10, the signal charge Q ₁ accumulated in the light receiving element of the first horizontal line (11) is a second packet of the first block B ₁
It is read out to the P _2. Then, the potential well formed in each packet during the ninth horizontal period moves to the output side by one block. In this case, the memory unit (20), the signal charges as shown in FIG. 7 is transferred from the first gate electrode portion G ₁ of the first packet P ₁ of the first block B ₁ to the seventh gate electrode portion G ₇ when have is turned on (oN) state, the other is turned off (oFF) state, also smear control gate section (29) the first signal charges of the first block B ₁ 1
Sixth gate electrode portion from the third gate electrode portion G ₃ packets P ₁
While passing through the G ₆ is turned off (OFF) state, while the other is in such an on (ON) state, stored in the light receiving element (11), the first block B ₁ second 2 packets
The signal charges Q ₁ read to P ₂ is stored in the memory unit (20), the first block B ₁ second packet P ₂ other packets
P _1, P ₃ is the incoming smear charges transferred by to P ₇ are swept out smear drain regions (30). Next, in the tenth horizontal period, the signal charges Q ₂ , ₃ are read out and transferred as described above. As described above, the signal charges Q _k and _{k + 1} are read in accordance with the signal charge read pulse φ _ROG shown in FIG.

The signal charge is read out and transferred in this way,
For example, in the 32nd horizontal period, the signal charges Q ₄₆ , ₄₇ stored in the light receiving elements on the 46th horizontal line and the 47th horizontal line.
Reads the the first block seventh packet P ₇ of B _1,
The signal charges Q ₄₈ , ₄₉ stored in the light receiving elements of the 48th horizontal line and the 49th horizontal line are transferred to the first packet P ₁ of the second block B ₂ .
To be read. In this case, FIGS. 12A and 12B
At T = t ₀ ′, a read pulse φ _ROG is supplied to the seventh gate electrode g ₇ and the eighth gate electrode g ₈ of the seventh packet P ₇ of the first block B ₁ as shown in FIG. As shown, the signal charges accumulated in the light receiving elements on the 46th horizontal line and the 47th horizontal line
Q ₄₆ and ₄₇ are read into the seventh packet P ₇ of the first block B ₁ .
With this manner, the signal charge is T = t ₁ 'in the first 13 first gate electrode portion G ₁ from the seventh gate electrode portion G ₇ of the seventh packet P ₇ of the first block B ₁ as shown in Figure B Is accumulated in the potential well formed in the substrate. Then, next, at T = t ₂ ′, a readout pulse φ _ROG is supplied to the _first gate electrode g ₁ and the second gate electrode g ₂ of the first packet P ₁ of the second block B ₂ , and
Reading out the signal charge Q _{48, 49} stored in the light receiving element of the first 48 horizontal line and the 49 horizontal lines as shown in Figure C of the first packet P ₁ of the second block B _2. With this manner, the signal charge is T = t ₃ 'in the first 13 first electrode portions G ₁ from the seventh gate electrode portion G ₇ of the first packet P ₁ of the second block B ₂ as shown in Figure D
Is accumulated in the potential well formed in the substrate. Since then
These signal charges are respectively transferred toward the memory area. Thus, when reading the signal charge to be read to the last seventh packet P ₇ of the n blocks to the seventh packet, the (n + 1) same horizontal first signal charges to be read out first packet P ₁ block Read during the blanking period.

In this solid-state imaging device, signal charges are read out and transferred by the above-described operations.
That is, the signal charge Q ₅₀₄ of the light receiving element on the 504th horizontal line is
It is read out during the horizontal period, and the horizontal transfer unit (1
3) is forwarded. In the even field, the tenth
As shown in the figure, signal charges are not read out during the nine horizontal periods from the 261st horizontal period to the 270th horizontal period, transfer and sweeping of smear charges are performed, and when the 271st horizontal period is reached, the first horizontal period is started. The same operation as in the case of the odd field is performed except that the signal charges accumulated in the light receiving elements of the line and the second horizontal line are read out.

According to the solid-state imaging device of this example, the vertical transfer unit (12)
Is divided into _ten blocks B ₁ , B ₂ ‥‥ B ₁₀ as shown in FIG. 4, and the _first to ninth blocks B ₁ to B ₉ are divided into seven packets P ₁ , P ₂ ‥‥ P consist of _7, 10 block B ₁₀ is composed of two packets P _1, P _2, is one packet composed of eight gate electrode portions G _1, G ₂ ‥‥ G _8, the light receiving element ( The signal charge obtained in 11) is read out into one packet in one block for each of one or two light receiving elements (11), transferred by a potential well formed in packet units, and other than the potential well for transferring the signal charge. The potential well is used to transfer the smear charge, and the smear charge is discharged to the smear / drain region (30), so that the charge transfer capability of the vertical transfer section (12) can be improved. Along with this vertical transfer unit (12)
In this case, the effect of smear charge can be effectively suppressed.

Further, according to the solid-state imaging device of the present example, the reading of the signal charges from the light receiving element (11) to the packets P ₁ , P ₂行 わ P ₇ is performed during the horizontal blanking period. During the detection of the signal charge in the charge detection section (14), the potential of the substrate is not fluctuated by the signal charge readout pulse φ _ROG and no clock pulse is swung.

Therefore, according to the solid-state imaging device of this example, it is possible to avoid fixed pattern noise generated by supplying the signal charge readout pulse φ _ROG during the horizontal effective period.

In the above embodiment, the case where the gate electrode is arranged so that one pixel corresponds to one electrode has been described. Alternatively, two electrodes may correspond to one pixel. Further, the number of blocks, the number of packets, and the number of gate electrode portions are not limited to the above-described cases.

In the above embodiment, the P-type silicon substrate (1
0), but instead of N
A P-well may be formed on the surface side of the N-type silicon substrate using a type silicon substrate, and a light receiving element, a vertical transfer section, and the like may be formed in the P-well.
The same operation and effect as described above can be obtained.

In addition, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

〔The invention's effect〕

According to the present invention, the potential of the substrate is not fluctuated by the read pulse during the horizontal effective period, that is, during the detection of the signal charge in the signal electrode detector (14), and the voltage of the clock pulse is varied during this period. Because there is no
The fixed pattern noise caused by supplying the read pulse during the horizontal valid period can be avoided.
Further, according to the present invention, since the memory section (20) can be stored only when signal charges are transferred, only the signal charges read from the light receiving element (11) are stored in the memory section (20). As a result, the effect of smear charge generated in the vertical transfer section (12) can be effectively suppressed.

[Brief description of the drawings]

1 and 2 are a schematic plan view and a schematic partial plan view, respectively, showing an embodiment of the solid-state imaging device of the present invention, FIG. 3 is a sectional view of a vertical transfer unit, and FIG. FIG. 5 is a waveform diagram showing a vertical scanning signal, FIG. 6 is a diagram showing a change in potential level of a vertical transfer path, and FIG. 7 is a memory gate region, a memory region and a vertical read gate. FIG. 8 is a sectional view showing a smear control gate portion and a smear drain region, and FIG. 9 is a sectional view showing a smear control gate region and a smear drain region. FIG. 10 is a diagram showing the supply timing of the signal charge readout pulse, FIG. 11 is a diagram schematically showing the transfer state of the signal charge in the odd field, FIG. 12 and FIG. The waveform diagram and a potential diagram illustrating a read of the signal charge in each 32 horizontal period, FIG. 14 is a schematic plan view showing an example of a conventional solid-state imaging device. (10) is a P-type silicon substrate, (11) is a light receiving element, (12)
Is a vertical transfer section, (13) is a horizontal transfer section, (14) is a signal charge detection section, (15) is a read gate section, (18) is a vertical transfer drive circuit, and (19) is a line address shift register. , (20) is the memory section, (21) is the vertical read gate section, (29) is the smear control gate section, (30)
Is a smear / drain region, B ₁ , B ₂ ‥‥ B ₁₀ are blocks, P ₁ , P ₂ ‥‥ P ₇ are packets, G ₁ , G ₂ ‥‥ G ₈ are gate electrode portions, g ₁ , G ₂ g ₂ ‥‥ g ₈ is the gate electrode, PD ₁ , PD ₂ 々
‥ PD ₇ is a packet driver circuit, φ _V1 , φ _V2 ‥‥ φ
_V8 is a vertical scanning signal.

Continuation of the front page (72) Inventor Maki Sato 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-62-122383 (JP, A)

Claims (2)

(57) [Claims] A light-receiving element arranged in a matrix in a vertical direction and a horizontal direction on a semiconductor substrate, and a charge-coupled element;
A vertical transfer unit for transferring signal charges obtained to the light receiving element in the vertical direction; a horizontal transfer unit comprising a charge-coupled device and transferring the signal charges transferred from the vertical transfer unit in the horizontal direction; A memory unit provided between the output side of the transfer unit and the horizontal transfer unit; and a signal charge detection unit for detecting the signal charge transferred from the horizontal transfer unit, wherein a plurality of the vertical transfer units are provided. And dividing the signal charge obtained in the light receiving element into a predetermined packet of the plurality of packets for each of one or two light receiving elements. In the solid-state imaging device configured to transfer the signal charge read out to the horizontal transfer unit via the memory unit, the memory unit can store the signal charge only when the signal charge is transferred. And reading out the signal charge from the light receiving element to the predetermined packet and transferring the signal charge from the memory unit to the horizontal transfer unit within a horizontal blanking period. Imaging device. 2. The solid-state imaging device according to claim 1, wherein a smear / drain region is provided on the output side of said vertical transfer unit via a smear control gate unit, and the signal charge is not passed. Wherein the smear control gate is turned on to discharge electric charges to the smear / drain region.