JPH06325991A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JPH06325991A
JPH06325991A JP5109691A JP10969193A JPH06325991A JP H06325991 A JPH06325991 A JP H06325991A JP 5109691 A JP5109691 A JP 5109691A JP 10969193 A JP10969193 A JP 10969193A JP H06325991 A JPH06325991 A JP H06325991A
Authority
JP
Japan
Prior art keywords
wafer
silicon
substrate
oxide film
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5109691A
Other languages
Japanese (ja)
Inventor
Kazuo Matsuzaki
一夫 松崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP5109691A priority Critical patent/JPH06325991A/en
Publication of JPH06325991A publication Critical patent/JPH06325991A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device that uses a thinned silicon wafer of which the thickness is selected at a requisite minimum, and that further secures a mechanical strength required for a step in a wafer process, and that is finally finished as a chip piece having an optimum thickness. CONSTITUTION:A silicon substrate 3 is joined to a silicon wafer 1 having a specific thickness determined by the specifications of a semiconductor device via a silicon oxide film 2, and this substrate having an join structure is brought into a wafer process to make devices 5 in the silicon wafer 1. Thereafter, the wafer is diced to the silicon oxide film 2 along scribe lines and further this silicon substrate 3 is plasma-etched, so that the silicon oxide film 2 is removed by hydrofluoric acid cleaning to cut it into individual pieces.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子の製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】周知のように、通常の半導体素子は、シ
リコンウェーハに一連のウェーハプロセスを施してウェ
ーハに多数の素子を作り込んだ後、ウェーハをダイシン
グしてチップ個片に分割するようして製造される。ま
た、半導体素子には、DRAMに代表されるようなウェ
ーハの表面部分を活性領域として素子を作る表面デバイ
ス、およびMOSFETで代表されるようにバルクをフ
ルに活用した縦方向デバイスなどがあるが、これら半導
体素子に用いるウェーハには、素子のオン抵抗,放熱特
性などの面から決まる適正な厚さが要求され、理想的に
は半導体素子の活性領域を形成する必要最小限の厚さに
することが望ましい。
2. Description of the Related Art As is well known, a normal semiconductor device is manufactured by subjecting a silicon wafer to a series of wafer processes to form a large number of devices and then dicing the wafer into individual chips. Manufactured. In addition, semiconductor elements include surface devices such as DRAMs that make elements using the surface portion of a wafer as an active region, and vertical devices that make full use of the bulk as represented by MOSFETs. Wafers used for these semiconductor elements are required to have an appropriate thickness that is determined by aspects such as the on-resistance and heat dissipation characteristics of the element, and ideally the minimum thickness required to form the active region of the semiconductor element. Is desirable.

【0003】しかしながら、ウェーハプロセスの工程間
で行うウェーハのハンドリング、および熱処理,成膜処
理による熱的ストレスなどに起因したウェーハの割れ,
欠けを回避して必要な機械的強度を確保するために、現
実的にはある程度厚さに余裕をもった肉厚の厚いシリコ
ンウェーハをウェーハプロセスに投入して製造を行って
いるのが現状である。また、半導体素子の生産性を高め
るために、昨今でのウェーハはますます大口径化する傾
向にあるが、一方では必要な機械的強度を確保するため
にウェーハの大口径化に伴ってウェーハの厚さも増加す
る。
However, the handling of the wafer between the steps of the wafer process, and the cracking of the wafer due to the thermal stress due to the heat treatment and the film forming process,
In order to avoid chipping and secure the necessary mechanical strength, in reality, thick silicon wafers with a certain thickness allowance are put into the wafer process for manufacturing. is there. In addition, in order to increase the productivity of semiconductor devices, the diameter of wafers is becoming larger and larger in recent years, but on the other hand, in order to secure the necessary mechanical strength, the diameter of wafers has become larger. The thickness also increases.

【0004】[0004]

【発明が解決しようとする課題】ところで、大口径のウ
ェーハより製造された半導体素子は、ウェーハの厚さが
厚い分だけダイシングにより細断されたチップ個片は、
チップサイズに対して相対的にチップの厚さが大とな
り、見掛け上でチップがサイコロ状を呈するようにな
る。そのために、チップをセラミック基板上にマウント
した状態ではチップと基板側の導体パターンとの間の高
低差が大きく、ワイヤボンディングの際にワイヤループ
の垂れなどでワイヤがチップに接触するなどの不具合が
生じ易い。
By the way, in a semiconductor element manufactured from a large-diameter wafer, a chip piece cut into pieces by dicing by the thickness of the wafer is
The thickness of the chip becomes relatively large with respect to the chip size, and the chip looks like a dice in appearance. Therefore, when the chip is mounted on the ceramic substrate, there is a large difference in height between the chip and the conductor pattern on the substrate side, and there are problems such as the wire coming into contact with the chip due to dripping of wire loops during wire bonding. It is easy to occur.

【0005】かかる点、従来ではセラミック基板の上面
に凹所を掘り込み、この凹所内にチップをマウントして
チップのボンディングパッドと導体パターンの高低差を
縮小するか、あるいはサンドブラスト法などによりチッ
プの厚さを薄くするなどの方法を採用して対処している
が、これらの方法は工数,手間がかかることからその改
善策が望まれている。
In this regard, conventionally, a recess is dug in the upper surface of the ceramic substrate, and the chip is mounted in the recess to reduce the height difference between the bonding pad of the chip and the conductor pattern, or by sandblasting or the like. This is dealt with by adopting methods such as reducing the thickness, but since these methods require man-hours and labor, improvement measures are desired.

【0006】本発明は上記の点にかんがみなされたもの
であり、その目的は前記課題を解決し、厚さを必要最小
限に選んだ肉薄なシリコンウェーハを使用し、しかもウ
ェーハプロセスでは工程上から要求される機械的強度を
確保しつつ、最終的に最適な厚さのチップ個片に仕上げ
ることができるようにした半導体素子の製造方法を提供
することにある。
The present invention has been made in view of the above points, and an object thereof is to solve the above-mentioned problems, to use a thin silicon wafer whose thickness is selected to be a necessary minimum, and in the wafer process, from the viewpoint of steps. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is capable of finally finishing into individual chips having an optimum thickness while ensuring the required mechanical strength.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明の製造方法においては、半導体素子の仕様か
ら決まる所定厚さのシリコンウェーハにシリコン酸化膜
を介してシリコン基板を貼り合わせ、この貼り合わせ構
造の基板をウェーハプロセスに投入して前記シリコンウ
ェーハに素子を作り込んだた後に、該ウェーハをスクラ
イブラインに沿ってシリコン酸化膜に達するまでダイシ
ングし、さらに前記のシリコン基板, シリコン酸化膜を
除去して個々のチップに分断するものとする。
In order to achieve the above object, in the manufacturing method of the present invention, a silicon substrate is bonded to a silicon wafer having a predetermined thickness determined from the specifications of semiconductor elements via a silicon oxide film, After the substrate having this bonded structure is put into a wafer process to form elements on the silicon wafer, the wafer is diced along the scribe line until it reaches a silicon oxide film, and then the silicon substrate, the silicon oxide The film shall be removed and divided into individual chips.

【0008】また、前記製造方法の実施に際しては、シ
リコン基板をプラズマエッチングにより除去する方法、
およびシリコン酸化膜をフッ酸液洗浄により除去する方
法がある。
In carrying out the manufacturing method, a method of removing the silicon substrate by plasma etching,
Another method is to remove the silicon oxide film by cleaning with a hydrofluoric acid solution.

【0009】[0009]

【作用】上記の製造方法において、ウェーハプロセスに
おいては、シリコンウェーハと補強用のシリコン基板を
シリコン酸化膜を介して貼り合わせた構造の基板を投入
するようにしたので、プロセス工程の処理上で要求され
る機械的強度が確保される。そして、ウェーハプロセス
を経てシリコンウェーハに素子を作り込んだウェーハに
対し、次のダイシング工程でシリコンウェーハを前記の
ウェーハ酸化膜に達するまで切り溝を入れてスクライビ
ングした後、さらにシリコンウェーハの裏面側からSF
6 ガスによるプラズマエッチングなどによりシリコン基
板を除去し、続いてフッ酸(HF)液の洗浄でシリコン
酸化膜を除去することにより、ウェーハが個々のチップ
個片に分割される。ここで、ウェーハから分断してチッ
プ化されたチップ個片は既に前工程でシリコンウェーハ
に貼り合わせたシリコン基板,シリコン酸化膜が除去さ
れているので、最終的にオン抵抗,放熱特性などの面か
ら要求される最適な厚さに仕上がる。
In the above-mentioned manufacturing method, in the wafer process, since the substrate having the structure in which the silicon wafer and the reinforcing silicon substrate are bonded to each other through the silicon oxide film is put in, it is required in the processing of the process step. The mechanical strength is ensured. Then, with respect to the wafer in which the elements are formed on the silicon wafer through the wafer process, after the silicon wafer is scribed and scribed until the wafer oxide film is reached in the next dicing process, the silicon wafer is further scribed from the back surface side. SF
The wafer is divided into individual chips by removing the silicon substrate by plasma etching with 6 gas, and then removing the silicon oxide film by cleaning with a hydrofluoric acid (HF) solution. Here, since the silicon substrate and the silicon oxide film bonded to the silicon wafer in the previous step have already been removed from the chip pieces that are separated from the wafer and made into chips, the surface such as on-resistance and heat dissipation characteristics is finally obtained. Finished to the optimum thickness required by

【0010】[0010]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。まず、ウェーハプロセスに投入する基板構造を図
1に示す。図において、1は半導体素子の種類,仕様な
どから決定される必要最小限の厚みを有するシリコンウ
ェーハ、2はシリコン酸化膜(SiO2 )、3はシリコン
ウェーハ1の支持基板となる補強用のシリコン基板であ
り、該シリコン基板3はシリコン酸化膜2を介してシリ
コンウェーハ1の裏面に貼り合わされている。なお、図
中に記した数値は基板の具体的な厚さ寸法を表してい
る。また、図3は前記の貼り合わせ基板に対し、一連の
ウェーハプロセスを経てシリコンウェーハ1に作り込ま
れた素子の断面構造を示す。なお、図3で示すように、
素子を作り込んだ後にシリコンウェーハ1の表面には、
後記のフッ酸洗浄液から保護するように、ボンディング
パッドを除く領域が耐蝕性に優れた窒化シリコン膜(Si
−N)で完全に被覆され、またボンディングパッド部は
フッ酸(HF)液に侵されない銅(Cu) で形成されてい
る。
Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 shows a substrate structure to be put into a wafer process. In the figure, reference numeral 1 denotes the type of semiconductor device, a silicon wafer having a minimum thickness determined from such specifications, 2 silicon oxide film (SiO 2), 3 silicon reinforcing as the supporting substrate of the silicon wafer 1 The substrate is a substrate, and the silicon substrate 3 is bonded to the back surface of the silicon wafer 1 via the silicon oxide film 2. The numerical values shown in the figures represent specific thickness dimensions of the substrate. Further, FIG. 3 shows a cross-sectional structure of an element formed on a silicon wafer 1 through a series of wafer processes on the above-mentioned bonded substrate. In addition, as shown in FIG.
After the device is built in, the surface of the silicon wafer 1
In order to protect it from the hydrofluoric acid cleaning solution described later, the silicon nitride film (Si
-N) is completely covered, and the bonding pad portion is formed of copper (Cu) which is not attacked by the hydrofluoric acid (HF) solution.

【0011】次に、図1(a)〜(e)により、図2に
示した貼り合わせ構造の基板をウェーハプロセスに投入
してチップ個片を得るまでの製造工程を説明する。ま
ず、(a)では図2で述べた貼り合わ構造の基板をウェ
ーハプロセスに投入し、シリコンウェーハ1の面上に図
3に表した素子を碁盤目状に配列して多数個作り込む。
1 (a) to 1 (e), a manufacturing process for obtaining a chip piece by introducing the substrate having the bonded structure shown in FIG. 2 into a wafer process will be described. First, in (a), the substrate having the bonded structure described in FIG. 2 is put into a wafer process, and a large number of the elements shown in FIG. 3 are arranged on the surface of the silicon wafer 1 in a grid pattern.

【0012】次に、ウェーハプロセスの終了した基板に
対して、(b)のダイシング工程では、シリコンウェー
ハ1の側からスクライブライン(ストリート)に沿って
シリコン酸化膜2に達するまでの深さに切り溝4を入れ
て素子5を細断するようにダイシングする。続く(c)
のエッチング工程では基板を裏返した上で、SF6 ガス
によるプラズマエッチングによりシリコン基板3を除去
した後、さらに(d)のフッ酸液による洗浄工程でシリ
コン酸化膜2を除去する。なお、このフッ酸液洗浄の際
には、先記した耐蝕性の高い窒化シリコン膜(Si−
N),銅(Cu) で素子を保護する。そして、シリコン酸
化膜2が除去されると、(e)で示すようにチップ6が
各個片に分断され、最終的にシリコンウェーハ1の厚さ
に相応した最適な厚さのチップに仕上がる。
Next, in the dicing step (b), the substrate after the wafer process is cut to a depth from the side of the silicon wafer 1 to the silicon oxide film 2 along the scribe line (street). Dicing is performed so that the groove 4 is formed and the element 5 is shredded. Continued (c)
In the etching step, the substrate is turned upside down, the silicon substrate 3 is removed by plasma etching with SF 6 gas, and then the silicon oxide film 2 is removed in the cleaning step with the hydrofluoric acid solution in (d). During the cleaning with the hydrofluoric acid solution, the above-mentioned silicon nitride film with high corrosion resistance (Si-
N), protect the device with copper (Cu). Then, when the silicon oxide film 2 is removed, the chip 6 is divided into individual pieces as shown in (e), and finally the chip having an optimum thickness corresponding to the thickness of the silicon wafer 1 is finished.

【0013】[0013]

【発明の効果】以上述べたように、本発明によれば、半
導体素子の仕様から決まる所定厚さのシリコンウェーハ
にシリコン酸化膜を介してシリコン基板を貼り合わせ、
この貼り合わせ構造の基板をウェーハプロセスに投入し
て前記シリコンウェーハに素子を作り込んだた後に、該
ウェーハをスクライブラインに沿ってシリコン酸化膜に
達するまでダイシングし、さらに前記のシリコン基板,
シリコン酸化膜を除去して個々のチップに分断したこと
により、ウェーハプロセスの工程上から要求される機械
的強度を確保しつつ、最終的にチップを最適な厚さに仕
上げることができ、オン抵抗,放熱性なとの面でデバイ
ス性能の高い半導体素子が得られる。
As described above, according to the present invention, a silicon substrate having a predetermined thickness determined by the specifications of semiconductor elements is bonded to a silicon substrate via a silicon oxide film,
After the substrate having this bonding structure is put into a wafer process to form an element on the silicon wafer, the wafer is diced until it reaches a silicon oxide film along a scribe line, and further the silicon substrate,
By removing the silicon oxide film and dividing it into individual chips, it is possible to finally finish the chips to the optimum thickness while ensuring the mechanical strength required from the wafer process step, and the on-resistance. A semiconductor element with high device performance in terms of heat dissipation is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例による半導体素子の製造工程の
説明図であり、(a)はウェーハプロセスに投入する基
板の構造図、(b)はダイシング工程図、(c)はシリ
コン基板を除去するエッチング工程図、(d)はシリコ
ン酸化膜を除去するフッ酸液洗浄工程図、(e)は分断
されたチップの個片を表す図
FIG. 1 is an explanatory view of a semiconductor device manufacturing process according to an embodiment of the present invention, in which (a) is a structural diagram of a substrate to be put into a wafer process, (b) is a dicing process diagram, and (c) is a silicon substrate. Etching process diagram for removal, (d) process diagram of hydrofluoric acid solution cleaning process for removing silicon oxide film, (e) diagram showing individual chip pieces

【図2】ウェーハプロセスに投入する貼り合わせ基板の
構造図
FIG. 2 is a structural diagram of a bonded substrate to be put into a wafer process.

【図3】図2の貼り合わせ基板に作り込まれた素子の構
造断面図
FIG. 3 is a structural cross-sectional view of an element built in the bonded substrate stack of FIG.

【符号の説明】[Explanation of symbols]

1 シリコンウェーハ 2 シリコン酸化膜 3 シリコン基板 4 切り溝 5 素子 6 チップ 1 silicon wafer 2 silicon oxide film 3 silicon substrate 4 kerf 5 element 6 chip

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体素子の仕様から決まる所定厚さのシ
リコンウェーハにシリコン酸化膜を介してシリコン基板
を貼り合わせ、この貼り合わせ構造の基板をウェーハプ
ロセスに投入して前記シリコンウェーハに素子を作り込
んだた後に、該ウェーハをスクライブラインに沿ってシ
リコン酸化膜に達するまでダイシングし、さらに前記の
シリコン基板, シリコン酸化膜を除去して個々のチップ
に分断したことを特徴とする半導体素子の製造方法。
1. A silicon substrate having a predetermined thickness determined from the specifications of a semiconductor device is bonded to a silicon substrate via a silicon oxide film, and the substrate having this bonding structure is put into a wafer process to form a device on the silicon wafer. After that, the wafer is diced along the scribe line until it reaches the silicon oxide film, and further, the silicon substrate and the silicon oxide film are removed and divided into individual chips. Method.
【請求項2】請求項1記載の製造方法において、シリコ
ン基板をプラズマエッチングにより除去することを特徴
とする半導体素子の製造方法。
2. A method of manufacturing a semiconductor device according to claim 1, wherein the silicon substrate is removed by plasma etching.
【請求項3】請求項1記載の製造方法において、シリコ
ン酸化膜をフッ酸液洗浄により除去することを特徴とす
る半導体素子の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon oxide film is removed by cleaning with a hydrofluoric acid solution.
JP5109691A 1993-05-12 1993-05-12 Method of manufacturing semiconductor device Pending JPH06325991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5109691A JPH06325991A (en) 1993-05-12 1993-05-12 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5109691A JPH06325991A (en) 1993-05-12 1993-05-12 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPH06325991A true JPH06325991A (en) 1994-11-25

Family

ID=14516755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5109691A Pending JPH06325991A (en) 1993-05-12 1993-05-12 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH06325991A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1427018A1 (en) * 2002-07-24 2004-06-09 Disco Corporation Method for processing soi substrate
JP2006339481A (en) * 2005-06-03 2006-12-14 Oki Electric Ind Co Ltd Cutting method and chip for bonded substrate
KR100828025B1 (en) * 2007-06-13 2008-05-08 삼성전자주식회사 Method of cutting a wafer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1427018A1 (en) * 2002-07-24 2004-06-09 Disco Corporation Method for processing soi substrate
EP1427018A4 (en) * 2002-07-24 2006-08-02 Disco Corp Method for processing soi substrate
JP2006339481A (en) * 2005-06-03 2006-12-14 Oki Electric Ind Co Ltd Cutting method and chip for bonded substrate
JP4694263B2 (en) * 2005-06-03 2011-06-08 Okiセミコンダクタ株式会社 Bonding substrate cutting method
KR100828025B1 (en) * 2007-06-13 2008-05-08 삼성전자주식회사 Method of cutting a wafer

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