JPH06325913A - Manufacture of chip resistor - Google Patents

Manufacture of chip resistor

Info

Publication number
JPH06325913A
JPH06325913A JP5136482A JP13648293A JPH06325913A JP H06325913 A JPH06325913 A JP H06325913A JP 5136482 A JP5136482 A JP 5136482A JP 13648293 A JP13648293 A JP 13648293A JP H06325913 A JPH06325913 A JP H06325913A
Authority
JP
Japan
Prior art keywords
layer
marking
resistor
pattern
photosensitive resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5136482A
Other languages
Japanese (ja)
Inventor
Zenichi Tamaki
善一 玉木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP5136482A priority Critical patent/JPH06325913A/en
Publication of JPH06325913A publication Critical patent/JPH06325913A/en
Pending legal-status Critical Current

Links

Landscapes

  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Non-Adjustable Resistors (AREA)
  • Details Of Resistors (AREA)

Abstract

PURPOSE:To prevent the generation of a blur, a disappearance or the like of a marking by a method wherein a chip resistor is marked by a photolithography method and this marking is covered with a transparent or semitransparent resin protective layer. CONSTITUTION:A resistor layer 2 and an electrode layer 5 are provided on an insulative substrate 1 and after that, the layer 2 is trimmed by a laser or the like and while a trimming groove 7 is formed, the resistance value of the layer 2 is adjusted. Then, a photosensitive resin layer 6 is provided on the layer 2 in such a way that its film thickness is 1 to 10mum or thereabouts. Then, this layer 6 is exposed to light using a mask formed with a prescribed marking pattern, the layer 6 is developed with a prescribed developing solution to leave a marking pattern layer 3 and the layer 6 is removed. A transparent or semitransparent resin protective layer 4 is provided in such a way as to cover the layer 3 and the exposed part of the layer 2. Thereby, even a microscopic marking is made possible a sharp notation and a chip resistor, on which a blur, a disappearance or the like of the marking is never generated, can be manufactured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、チップ抵抗器の製造方
法に関し、より詳しくはチップ状の薄膜抵抗器及び厚膜
抵抗器の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a chip resistor, and more particularly to a chip-shaped thin film resistor and a method of manufacturing a thick film resistor.

【0002】[0002]

【従来の技術】一般にチップ抵抗器(薄膜抵抗器及び厚
膜抵抗器)の表面には、抵抗値識別等のための文字、マ
ーク等の標印が施されている。従来より上記標印は、絶
縁性基板上に設けられた抵抗体層を覆うガラスの保護層
上に、スクリーン印刷等の印刷、転写等によって設けら
れている。
2. Description of the Related Art Generally, the surface of a chip resistor (thin film resistor and thick film resistor) is provided with a mark such as a character or mark for identifying a resistance value. Conventionally, the mark is provided by printing such as screen printing, transfer, etc. on a protective layer of glass covering the resistor layer provided on the insulating substrate.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、最近ま
すます進む電子部品の小型化につれて上記チップ抵抗器
も小型化されてきており、従来の標印形成方法である印
刷、転写等では対応しきれなくなってきている。
However, with the recent miniaturization of electronic components, the chip resistors have also been miniaturized, and the conventional mark forming methods such as printing and transfer cannot be used. Is coming.

【0004】例えば、形状寸法が1.6×0.8mmの
チップ抵抗器では、実際の標印箇所は1.0×0.6m
m程度以下となり、幅50μm程度以上の細線では表記
が不明確となる。しかしながら、上記印刷又は転写は、
微細な標印には不適合で、幅50μm程度以下の細線を
形成しようとするとぼやけ又はかすれが生じてしまうの
である。
For example, in a chip resistor having a shape dimension of 1.6 × 0.8 mm, the actual marking location is 1.0 × 0.6 m.
If the width is about m or less and the width is about 50 μm or more, the description becomes unclear. However, the printing or transfer is
It is unsuitable for fine markings, and blurring or blurring occurs when trying to form a fine line with a width of about 50 μm or less.

【0005】また、上記標印は、保護層の表面に設けら
れているために、標印面が露出状態となる。よって、標
印が上記のような細線による微細なものでは、製造工程
における標印後の工程、例えばチップ抵抗器の製造工程
で通常行われるブレーキング工程、メッキ工程等或いは
搬送時等において、各種製造機器、ケース等との接触又
は擦れ、或いは部品同士による擦れによって、標印がか
すれたり消失したりするのである。
Further, since the mark is provided on the surface of the protective layer, the mark surface is exposed. Therefore, if the mark is fine by the thin line as described above, various kinds of marks are used in the process after the mark in the manufacturing process, for example, in the braking process or plating process or the like which is usually performed in the manufacturing process of the chip resistor. The mark may be faint or disappear due to contact or rubbing with a manufacturing device, a case, or the like, or rubbing between parts.

【0006】更に、標印が最上層に設けられるめに、チ
ップ抵抗器表面には標印部の凹凸が生じることとなる。
チップ抵抗器の寸法が小さくなると上記凹凸が実装時の
吸着コレットの吸着力を低下させ、実装不良の原因とな
るのである。
Further, since the mark is provided on the uppermost layer, the unevenness of the mark portion is generated on the surface of the chip resistor.
When the size of the chip resistor is reduced, the unevenness reduces the suction force of the suction collet at the time of mounting and causes mounting failure.

【0007】本発明は、上記問題を解消し、微細な標印
でもシャープな表記を可能とし、標印のかすれ、消失等
が生じることのないチップ抵抗器の製造方法を提供する
ことを目的とする。
It is an object of the present invention to solve the above problems and to provide a method for manufacturing a chip resistor which enables sharp marking even with a fine marking and does not cause fading or disappearance of the marking. To do.

【0008】[0008]

【課題を解決するための手段】本発明者は、上記技術の
現状に鑑み鋭意研究を重ねた結果、チップ抵抗器におけ
る標印をフォトリソグラフィ法により行い、該標印を透
明乃至半透明の樹脂保護層で覆うときは、標印のパター
ンがシャープで読み取れ易く、標印のかすれ、消失等が
生じることなく、しかもチップ抵抗器の表面を平滑にで
きることを見出した。
The present inventor has conducted extensive studies in view of the above-mentioned state of the art, and as a result, the marking of the chip resistor is performed by a photolithography method, and the marking is made of a transparent or translucent resin. It has been found that when covered with a protective layer, the pattern of the mark is sharp and easy to read, the mark does not fade or disappear, and the surface of the chip resistor can be made smooth.

【0009】即ち、本発明は、以下のチップ抵抗器の製
造方法に係るものである。
That is, the present invention relates to the following method of manufacturing a chip resistor.

【0010】(1)抵抗体層が形成された絶縁性基板上
に感光性樹脂を塗布し、所定の標印パターンが形成され
たマスクにより上記感光性樹脂を露光処理し、現像して
標印パターンを形成し、上記抵抗体層及び標印パターン
を覆うように透明乃至半透明の樹脂保護層を設けること
を特徴とするチップ抵抗器の製造方法。
(1) A photosensitive resin is applied on an insulating substrate having a resistor layer formed thereon, the photosensitive resin is exposed to light by a mask having a predetermined marking pattern formed thereon, and the mark is developed. A method of manufacturing a chip resistor, comprising forming a pattern, and providing a transparent or semitransparent resin protective layer so as to cover the resistor layer and the marking pattern.

【0011】(2)絶縁性基板上に抵抗体層を形成する
工程と、抵抗体層をトリミングして抵抗値を調整する工
程と、上記抵抗体層を含む上記絶縁性基板上に感光性樹
脂を塗布する工程と、所定のパターンが形成されたマス
クにより上記感光性樹脂を露光処理し現像して上記トリ
ミングにより形成されるトリミング溝を覆う保護パター
ンと標印パターンとを形成する工程と、上記抵抗体層、
保護パターン及び標印パターンを覆うように透明乃至半
透明の樹脂保護層を設ける工程とを含むことを特徴とす
るチップ抵抗器の製造方法。
(2) A step of forming a resistor layer on the insulating substrate, a step of trimming the resistor layer to adjust the resistance value, and a photosensitive resin on the insulating substrate including the resistor layer. And a step of forming a protective pattern and a mark pattern for covering the trimming groove formed by the trimming by exposing and developing the photosensitive resin with a mask on which a predetermined pattern is formed, Resistor layer,
And a step of providing a transparent or semi-transparent resin protective layer so as to cover the protective pattern and the marking pattern.

【0012】[0012]

【作用】フォトリソグラフィ法により標印を行うので、
1μmオーダーの幅の細線であってもぼやけのない明確
な表記が可能となる。
[Function] Since the marking is performed by the photolithography method,
Even with a thin line having a width of the order of 1 μm, clear notation without blurring is possible.

【0013】感光性樹脂を低粘度に調整することで、標
印形成と同時にトリミング溝を確実に埋めることができ
る。
By adjusting the photosensitive resin to have a low viscosity, the trimming groove can be surely filled at the same time when the mark is formed.

【0014】透明乃至半透明の樹脂保護層を設けるので
標印のかすれ又は消失が生じず、しかも表面を平滑にす
ることができる。
Since the transparent or semi-transparent resin protective layer is provided, the mark does not fade or disappear, and the surface can be made smooth.

【0015】[0015]

【実施例】以下、本発明の製造方法をチップ状の厚膜抵
抗器に適用した場合の実施例を、図面を参照しつつ説明
するが、本発明はこれら実施例に限定されることはな
い。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments in which the manufacturing method of the present invention is applied to a chip-shaped thick film resistor will be described with reference to the drawings, but the present invention is not limited to these embodiments. .

【0016】図1乃至図3は、本発明の実施例を示す図
であり、図1は本発明の方法により得られる厚膜抵抗器
の断面図を示し、図2は本発明の方法を説明する平面図
である。これら図において、符号1は絶縁性基板を、2
は抵抗体層を、3は標印パターン層を、4は樹脂保護層
を、5は電極層を、6は感光性樹脂層を示す。
1 to 3 are views showing an embodiment of the present invention, FIG. 1 shows a cross-sectional view of a thick film resistor obtained by the method of the present invention, and FIG. 2 explains the method of the present invention. FIG. In these figures, reference numeral 1 denotes an insulating substrate, and 2
Is a resistor layer, 3 is a marking pattern layer, 4 is a resin protective layer, 5 is an electrode layer, and 6 is a photosensitive resin layer.

【0017】図1において、標印パターン層3は、抵抗
体層2上に設けられる。ここでは、上記標印パターン層
3は、抵抗体層2上に設けられているが、標印パターン
層3の一部乃至全部が絶縁性基板1上に掛かるように設
けられてもかまわない。そして上記標印層3は、抵抗体
層2の露出部と共に透明乃至半透明の樹脂保護層4で覆
われている。
In FIG. 1, the marking pattern layer 3 is provided on the resistor layer 2. Here, the marking pattern layer 3 is provided on the resistor layer 2, but it is also possible that a part or all of the marking pattern layer 3 is provided on the insulating substrate 1. The marking layer 3 is covered with the exposed portion of the resistor layer 2 and a transparent or semitransparent resin protective layer 4.

【0018】次に、本実施例を図2(a)〜(d)に基
づきより具体的に説明する。
Next, this embodiment will be described more specifically with reference to FIGS. 2 (a) to 2 (d).

【0019】図2(a)に示すように、絶縁性基板1上
に抵抗体層2及び電極層5を設け、その後レーザ等によ
り抵抗体層2をトリミングしてトリミング溝7を形成し
つつ抵抗値が調整される。
As shown in FIG. 2A, a resistor layer 2 and an electrode layer 5 are provided on an insulating substrate 1, and then the resistor layer 2 is trimmed by a laser or the like to form a trimming groove 7 and a resistor. The value is adjusted.

【0020】図2(b)に示すように、感光性樹脂層6
を上記のようにして設けられた抵抗体層2上に膜厚1〜
10μm程度となるように設ける。感光性樹脂層6は、
例えば感光性樹脂をスピンコート、ロールコート等によ
り塗布し、仮乾燥を行うことにより設けることができ
る。上記感光性樹脂としては、公知のネガ型及びポジ型
のフォトレジストの他、光(紫外線を含む)により上記
フォトレジストにおけるネガ型及びポジ型と同様の作用
を発現する樹脂類を限定されることなく広く使用でき、
より具体的には感光性ポリイミド樹脂等が例示できる。
また、上記感光性樹脂層6は、下地となる層とのコント
ラストが高くなるように顔料等で着色されるのが好まし
い。
As shown in FIG. 2B, the photosensitive resin layer 6
On the resistor layer 2 provided as described above with a film thickness of 1 to
It is provided to have a thickness of about 10 μm. The photosensitive resin layer 6 is
For example, it can be provided by applying a photosensitive resin by spin coating, roll coating, or the like, and performing temporary drying. As the photosensitive resin, in addition to known negative and positive photoresists, resins that exhibit the same action as the negative and positive photoresists in the photoresist by light (including ultraviolet rays) are limited. Can be widely used without
More specifically, a photosensitive polyimide resin or the like can be exemplified.
Further, the photosensitive resin layer 6 is preferably colored with a pigment or the like so as to have a high contrast with the underlying layer.

【0021】次に、図2(c)に示すように、上記感光
性樹脂層6に所定の標印パターンの形成されたマスクを
用いて感光処理し、所定の現像液、例えばアルカリ系有
機溶剤等で現像処理して必要な部分(標印パターン層
3)を残して感光性樹脂層6を除去する。上記感光処理
で標印パターン層3の硬化が不十分なときは、上記現像
処理後に再度光を照射して更に硬化を促進させてもよ
い。
Next, as shown in FIG. 2 (c), the photosensitive resin layer 6 is exposed to light using a mask having a predetermined marking pattern formed thereon, and a predetermined developing solution such as an alkaline organic solvent is used. And the like, and the photosensitive resin layer 6 is removed leaving a necessary portion (marking pattern layer 3). When the marking pattern layer 3 is not sufficiently cured by the above-mentioned photosensitizing process, the mark pattern layer 3 may be irradiated with light again after the developing process to further accelerate the curing.

【0022】本実施例では、トリミング溝7上の感光性
樹脂層6を除去したが、図3に示すようにトリミング溝
7を埋めるように感光性樹脂層6を残し、標印パターン
層3とともに保護パターン層3aを形成してもよい。こ
の時、感光性樹脂層6は低粘度に調整され塗布されるの
が好ましく、このようにすることでトリミング溝7を隙
間なく覆うことができ、上記樹脂保護層4を設けたとき
にトリミング溝7中の空気よりピンホールが生じたり、
トリミング溝7から外気に通じる隙間が生じたりするこ
とがなくなり、より確実に水分浸入等による抵抗体層2
への悪影響を防止し得る。
In this embodiment, the photosensitive resin layer 6 on the trimming groove 7 is removed, but the photosensitive resin layer 6 is left so as to fill the trimming groove 7 as shown in FIG. The protective pattern layer 3a may be formed. At this time, the photosensitive resin layer 6 is preferably adjusted to have a low viscosity and applied. By doing so, the trimming groove 7 can be covered without a gap, and when the resin protective layer 4 is provided, the trimming groove is provided. Pinholes are created from the air in 7,
There will be no gap from the trimming groove 7 to the outside air, so that the resistance layer 2 can be more reliably filled with moisture or the like.
Can be prevented from being adversely affected.

【0023】また、図2(c)では、標印部の感光性樹
脂層6を残すように標印パターン層3を設けているが、
標印部のみを除去してその周囲の感光性樹脂層6を残す
ようにしてもよい。
Further, in FIG. 2C, the marking pattern layer 3 is provided so as to leave the photosensitive resin layer 6 of the marking portion,
It is also possible to remove only the mark portion and leave the photosensitive resin layer 6 around it.

【0024】そして、図2(d)に示すように、標印パ
ターン層3及び抵抗体層2の露出部を覆うようにスクリ
ーン印刷法、フォトリソ法等により透明又は標印パター
ン層3の表示色とは異なる半透明の樹脂保護層4を設け
る。
Then, as shown in FIG. 2D, a transparent or display color of the marking pattern layer 3 is formed by screen printing or photolithography so as to cover the exposed portions of the marking pattern layer 3 and the resistor layer 2. A semitransparent resin protective layer 4 different from the above is provided.

【0025】以上本発明の方法を厚膜抵抗器について説
明したが、本発明の方法は薄膜抵抗器の製造においても
適用できる。
Although the method of the present invention has been described with reference to a thick film resistor, the method of the present invention can be applied to the manufacture of a thin film resistor.

【0026】[0026]

【発明の効果】本発明の製造方法は、以下のような効果
を奏するものである。
The manufacturing method of the present invention has the following effects.

【0027】(1)小型のチップ部品であっても標印が
明確に行うことができる。
(1) The marking can be clearly performed even with a small chip component.

【0028】(2)標印にぼやけ、かすれ又は消失が生
じることがない。
(2) The mark is not blurred, blurred, or lost.

【0029】(3)抵抗体層の保護と標印の保護とを同
一の保護層で行うことができる。
(3) The resistor layer and the mark can be protected by the same protective layer.

【0030】(4)チップ抵抗器の表面を平滑にするこ
とができ、吸引コレットによる吸着性を改善し得るので
確実な実装を行うことができる。
(4) Since the surface of the chip resistor can be made smooth and the suction property by the suction collet can be improved, reliable mounting can be performed.

【0031】(5)標印と同一工程でトリミング溝を確
実に埋めることができ、信頼性の高いチップ抵抗器を得
ることができる。
(5) The trimming groove can be surely filled in the same step as the marking, and a highly reliable chip resistor can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例により得られるチップ抵抗器の
断面図である。
FIG. 1 is a sectional view of a chip resistor obtained according to an embodiment of the present invention.

【図2】本発明の実施例を説明するための工程図であ
る。
FIG. 2 is a process drawing for explaining the embodiment of the present invention.

【図3】本発明の他の実施例により得られるチップ抵抗
器の断面図である。
FIG. 3 is a cross-sectional view of a chip resistor obtained according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁性基板 2 抵抗体層 3 標印パターン層 3a 保護パターン層 4 樹脂保護層 5 電極層 6 感光性樹脂層 7 トリミング溝 1 Insulating Substrate 2 Resistor Layer 3 Marking Pattern Layer 3a Protective Pattern Layer 4 Resin Protective Layer 5 Electrode Layer 6 Photosensitive Resin Layer 7 Trimming Groove

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 抵抗体層が形成された絶縁性基板上に感
光性樹脂を塗布し、所定の標印パターンが形成されたマ
スクにより上記感光性樹脂を露光処理し、現像して標印
パターンを形成し、上記抵抗体層及び標印パターンを覆
うように透明乃至半透明の樹脂保護層を設けることを特
徴とするチップ抵抗器の製造方法。
1. A marking pattern formed by applying a photosensitive resin on an insulating substrate having a resistor layer formed thereon, exposing the photosensitive resin to light with a mask having a predetermined marking pattern, and developing the photosensitive resin. And a transparent or semi-transparent resin protective layer is provided so as to cover the resistor layer and the marking pattern.
【請求項2】 絶縁性基板上に抵抗体層を形成する工程
と、抵抗体層をトリミングして抵抗値を調整する工程
と、上記抵抗体層を含む上記絶縁性基板上に感光性樹脂
を塗布する工程と、所定のパターンが形成されたマスク
により上記感光性樹脂を露光処理し現像して上記トリミ
ングにより形成されるトリミング溝を覆う保護パターン
と標印パターンとを形成する工程と、上記抵抗体層、保
護パターン及び標印パターンを覆うように透明乃至半透
明の樹脂保護層を設ける工程とを含むことを特徴とする
チップ抵抗器の製造方法。
2. A step of forming a resistor layer on an insulating substrate, a step of trimming the resistor layer to adjust a resistance value, and a photosensitive resin on the insulating substrate including the resistor layer. A step of applying, a step of exposing and developing the photosensitive resin with a mask having a predetermined pattern to form a protective pattern and a mark pattern for covering a trimming groove formed by the trimming, and the resistance. And a step of providing a transparent or translucent resin protective layer so as to cover the body layer, the protective pattern and the marking pattern.
JP5136482A 1993-05-14 1993-05-14 Manufacture of chip resistor Pending JPH06325913A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5136482A JPH06325913A (en) 1993-05-14 1993-05-14 Manufacture of chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5136482A JPH06325913A (en) 1993-05-14 1993-05-14 Manufacture of chip resistor

Publications (1)

Publication Number Publication Date
JPH06325913A true JPH06325913A (en) 1994-11-25

Family

ID=15176179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5136482A Pending JPH06325913A (en) 1993-05-14 1993-05-14 Manufacture of chip resistor

Country Status (1)

Country Link
JP (1) JPH06325913A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1269540A1 (en) * 2000-03-09 2003-01-02 Silverbrook Research Pty. Limited Modular printhead alignment system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1269540A1 (en) * 2000-03-09 2003-01-02 Silverbrook Research Pty. Limited Modular printhead alignment system
EP1269540A4 (en) * 2000-03-09 2005-03-30 Silverbrook Res Pty Ltd Modular printhead alignment system

Similar Documents

Publication Publication Date Title
EP1632991A4 (en) Exposure method, exposure device, and device manufacturing method
CN114913558B (en) Preparation method of microlens array imaging assembly
JP3019503B2 (en) Manufacturing method of printed wiring board
JPH06325913A (en) Manufacture of chip resistor
JP3031042B2 (en) Printed wiring board for surface mounting
JP2587548B2 (en) Manufacturing method of printed wiring board
JP2743100B2 (en) Manufacturing method of printed circuit board, photo solder resist and solder resist ink
JPH04174586A (en) Printed wiring board
JP2897365B2 (en) Manufacturing method of wiring board
JPH1027950A (en) Printed wiring board
JP2687616B2 (en) Manufacturing method of printed wiring board
JP2723744B2 (en) Manufacturing method of printed wiring board
JP2636531B2 (en) Manufacturing method of printed wiring board
JPH07106103A (en) Manufacture of chip resistor
JPS61139089A (en) Manufacture of printed wiring board
JP2589470B2 (en) Method for manufacturing semiconductor device
JPH0725129A (en) Printed wiring board
JPH05152722A (en) Forming method of printed wiring pattern
JPH06255232A (en) Manufacture of printed wiring board
JPH02186692A (en) Manufacture of printed wiring board
JP2583365B2 (en) Manufacturing method of printed wiring board
JPH0239485A (en) Manufacture of printed wiring board printed with eye mark
JPH03166792A (en) Screen mask and manufacturing method thereof
JP2717841B2 (en) Pattern formation method
JPH01321683A (en) Manufacture of printed wiring board