JPH06324867A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the capacity of hardware without lowering the performance of an integer computing element in an information processor. CONSTITUTION:The information processor 100 is constituted of a selector 101, a first instruction register 102, a second instruction register 103, a first computing element 104a provided with a function to execute all the integer arithmetic operations other than a branch instruction instead of the same function on plural integer computing elements, a second computing element 105 provided with an execution function for all the integer arithmetic operations including the branch instruction, a first decoder 106, a second decoder 107, a program counter 110, a parallel execution decision circuit 108, and a register file 111, etc., and the instruction code of the branch instruction is distributed to the second computing element 105 provided with the branch execution function via the selector 101 of the instruction code, and it is decoded, thereby, the arithmetic operation can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, the present invention relates to a technique effectively applied to a control technique of each integer arithmetic unit in a superscalar system information processing apparatus including a plurality of integer arithmetic units.

[0002]

2. Description of the Related Art When executing a branch instruction in a pipeline-controlled information processing apparatus, the pipeline shown in FIG. 3 will be described as an example. The branch instruction 34 is executed in the following steps. It is the instruction read stage (Instr
function fetch) 30, a decode stage (Decode) 31 for decoding an instruction, and a branch instruction 3
A calculation stage (Executio) that performs branch determination of 4
n) 32, and a write stage (Wri
te) 33.

If the branch is taken, the branch destination instruction 3
7 starts execution from the instruction read stage 38 of the branch destination instruction. At this time, since the two instructions subsequent to the branch instruction 34, which are the invalidated instructions 35 and 36, have already been read by the time the branch destination instruction 37 is read, the invalidation cycle occurs for those two instructions. It will be.

The architecture of the system called the delayed branching technique was devised in order to effectively use this invalidation cycle and improve the performance of the information processing apparatus. The delay branching technique uses an instruction called a delay slot. This instruction will be described with reference to FIG.

The delay slot instruction is a succeeding instruction located next to the branch instruction, and is an instruction executed in a cycle which is an invalidation cycle in the example of FIG.

In the pipeline, n + 1 cycles are allocated to the execution cycle of the delay slot instruction 41.

First, the branch instruction 40 is executed, and then the delay slot instruction 41 is executed. Then, the n + 2 cycle becomes the invalidated instruction 42, and the branch destination instruction 43 is started to be executed from the instruction reading stage 44 of the n + 3 cycle.

According to this method, the number of invalidation cycles is reduced from two cycles in the method not using the delayed branch to one cycle.

However, in a superscalar type information processing apparatus having a plurality of arithmetic units, delay slot rows may be lost.

Pipeline processing in the case where a two-instruction parallel superscalar system is adopted for the pipeline shown in FIG. 4 will be described with reference to FIG.

In this pipeline processing, the branch instruction 60
2 and the delay slot instruction 61 can be executed in parallel, and the branch instruction calculation stage 62 is completed.
The cycle, the n + 1 cycle and the n + 2 cycle become invalidation cycles.

In other words, with respect to branch instructions, this superscalar system loses the merit of the delay slot instruction and does not improve the performance.

In a conventional superscalar system information processing apparatus having a plurality of integer arithmetic units, each arithmetic unit has the same instruction execution function. This scheme requires the same control logic and data path for each integer unit.

Next, this conventional method will be described with reference to FIG.

For each instruction in the first instruction register 102 and the second instruction register 103, the first decoder 1
06, the second decoder 107, and the first arithmetic unit 104,
A second calculator 105 is provided.

The parallel execution determination circuit 108 determines whether or not two instructions in the first instruction register 102 and the second instruction register 103 have no dependency relationship and can be executed in parallel.

If parallel execution is possible, the first arithmetic unit 1
04 and the second instruction valid signal 112 of the second arithmetic unit 105 are set to 1, the second instruction valid signal 113 of the second arithmetic unit 105 is set to 0, and only the instruction of the first instruction register 102 is executed first. In the next cycle, the instruction in the second instruction register 103 is executed.

In order to execute a branch instruction in both the first and second arithmetic units 104 and 105, the program counter 11
The data path 1 of the instruction address for inputting the instruction address required for calculating the branch destination address relative to the program counter from 0 to both the first arithmetic unit 104 and the second arithmetic unit 105
14 is required.

The operand data used for the calculation in the first arithmetic unit 104 and the second arithmetic unit 105 is the register file 1
11 is read out and the operation result is stored again in the register file 111.

For example, when the first instruction register 102 has a branch instruction and the second instruction register 103 has a delay slot instruction, if they can be executed in parallel, they are decoded by the first decoder 106 and the second decoder 107, respectively. , The first computing unit 104 and the second computing unit 105.

Further, if the first instruction register 102 has AD
If parallel execution is possible even when there is a branch instruction in the D instruction and the second instruction register 103, the first instruction independently
The control information 115 and 116 decoded by the decoder 106 and the second decoder 107 are passed to the first arithmetic unit 104 and the second arithmetic unit 105, and are transferred to the first arithmetic unit 104 and the second arithmetic unit 105. Is executed.

That is, both the first arithmetic unit 104 and the second arithmetic unit 105 of this system have a function of executing a branch instruction and other integer arithmetic instructions, respectively.

Further, because of the invalidation cycle that occurs in the branch control of the superscalar system described in FIG. 5,
Even if the branch instruction is sequentially processed for two cycles such as n cycles and the delay slot instruction is the next n + 1 cycle, there is no performance deterioration. Further, as shown in the pipeline processing of FIG. The n-cycle second arithmetic unit 105 side, and the delay slot instruction 7
Similarly, even if 2 is limited to the second computing unit 105 side of n + 1 cycle so that it is sequentially processed only on the second computing unit 105 side, there is no performance deterioration.

[0024]

However, in the prior art as described above, it is sufficient that only one side is sufficient even if the branch instructions cannot be executed in both the first, second and both arithmetic units. Providing the branch execution function in the arithmetic unit has a drawback in that the amount of hardware is wasted.

Therefore, the superscalar type information processing apparatus using the delay slot instruction has a problem that the amount of hardware increases due to the superscalar type although the branch performance is not improved.

Therefore, an object of the present invention is to execute an instruction by combining an integer arithmetic unit in which an execution function of a branch instruction is omitted and an integer arithmetic unit in which the branch instruction is not executed, so that the hardware quantity can be reduced without degrading the performance. An object is to provide an information processing device that can be reduced.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0028]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the information processing apparatus of the present invention is a pipeline type information processing apparatus that includes a plurality of integer arithmetic units and processes instructions in parallel, and has a function of executing all integer operations including branch instructions. An integer arithmetic unit and an integer arithmetic unit having a function of executing all integer arithmetic operations other than branch instructions are provided, and the integer arithmetic units are combined to perform parallel processing of a plurality of instructions.

Further, the information processing apparatus of the present invention distributes the instruction code of the branch instruction to the integer arithmetic unit having a branch instruction execution function, decodes the instruction, and performs the arithmetic operation by the integer arithmetic unit.

The information processing apparatus of the present invention comprises a branch instruction detecting means for judging whether the instruction to be executed is a branch instruction.

Further, the information processing apparatus of the present invention comprises a branch instruction selecting means for distributing the instruction code of the branch instruction to the integer arithmetic unit having a branch instruction execution function.

Further, the information processing apparatus of the present invention is provided with the instruction address input means for inputting the instruction address from the program counter only to the integer arithmetic unit having the branch instruction executing function, and the instruction address is inputted only to the integer arithmetic unit. The instruction address is input by the input means to calculate the branch destination address.

The information processing apparatus of the present invention comprises one integer arithmetic unit having a branch instruction execution function among a plurality of integer arithmetic units, and the instruction address input means is provided only to the arithmetic unit having the branch instruction execution function. It is equipped with one.

[0035]

According to the information processing apparatus described above, the branch instruction detecting means detects the branch instruction, and the branch instruction selecting means further outputs the instruction code of the branch instruction as an integer having the function of executing all integer operations including the branch instruction. The branch instruction can be executed by passing it to the arithmetic unit.

Then, all the integer arithmetic units have all the integer arithmetic functions, but execute the integer arithmetic units having the execution function of all the integer arithmetic operations including the branch instruction and all the integer arithmetic operations other than the branch instruction. By including an integer arithmetic unit having a function and performing arithmetic operations in combination, it is possible to reduce the amount of hardware without degrading performance.

Further, since only the integer arithmetic unit having the branch instruction execution function is provided with the instruction address input means, it is not necessary to provide the other integer arithmetic units, and the quantity of the instruction address input means can be reduced.

As a result, in all integer arithmetic units,
Without the hardware for performing branch instructions,
Moreover, the amount of hardware can be reduced without lowering the performance, and the device can be downsized and the cost can be reduced.

[0039]

EXAMPLES Examples of the present invention will be described in detail below.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a schematic explanatory diagram showing a pipeline of a branch instruction and its subsequent instruction control in the arithmetic unit configuration of the present embodiment. Is.

First, the configuration of the information processing apparatus of this embodiment will be described with reference to FIG.

The information processing apparatus 100 of this embodiment is, for example, a pipeline type information processing apparatus capable of parallel processing of instruction execution, and a selector 101 (branch instruction selecting means).
, The first instruction register 102, and the second instruction register 10
3, a first arithmetic unit 104a, a second arithmetic unit 105, a first decoder 106, a second decoder 107, a parallel execution determination circuit 108, a branch instruction detection circuit 109 (branch instruction detection means), and a program The instruction stored in the first and second instruction registers 102 and 103, which includes the counter 110 and the register file 111, is decoded by the first and second decoders 106 and 107, and the first and second arithmetic units 1
Calculations are executed at 04a and 105.

The first arithmetic unit 104a has a function of executing all integer operations other than branch instructions, and the second arithmetic unit 105a.
Has the function of executing all integer operations including branch instructions.

For each instruction in the first instruction register 102 and the second instruction register 103, the first decoder 1
06, the second decoder 107, and the first arithmetic unit 104a and the second arithmetic unit 105 are provided.

When the first instruction register 102 has a branch instruction, the information processing apparatus 100 has a branch instruction detection circuit 109.
Output of the first instruction register 10 by the selector 101.
The second side is selected, the instruction code of the branch instruction is input to the second decoder 107, and the second arithmetic unit 105 executes the instruction code.

The parallel execution determination circuit 108 determines whether or not two instructions in the first instruction register 102 and the second instruction register 103 have no dependency relationship and can be executed in parallel. If parallel execution is possible, the first arithmetic unit 104
a and the first and second instruction valid signals 112 and 113 of the second arithmetic unit 105 are set to 1. Program counter 1
10 holds the instruction address to be executed next.

Next, the operation of this embodiment will be described.

The case where the first instruction register 102 has a branch instruction will be described below.

First, the parallel execution determination circuit 108 sets the first instruction valid signal 112 of the first arithmetic unit 104a to 0,
The second instruction valid signal 113 of the arithmetic unit 105 is set to 1. The instruction code of the branch instruction is sent to the second decoder 107 through the selector 101.

Next, the second arithmetic unit 105 is controlled by the control information 116 output from the second decoder 107. Similarly in the next cycle, the first instruction valid signal 112 of the first arithmetic unit 104a is set to 0 and the second instruction valid signal 113 of the second arithmetic unit 105 is set to 1.

Then, the delay slot instruction in the second instruction register 103 is executed by the second arithmetic unit 105. In other words, this branch instruction and delay slot instruction are 2
Sequential processing is performed in cycles.

Further, the instruction address output from the program counter 110 is input to the second arithmetic unit 105 from the instruction address data path 114 (instruction address input means) and used for calculating the branch destination address relative to the program counter 110. . First calculator 104a and second calculator 10
In 5, the operand data used for the calculation is read from the register file 111, and the calculation result is stored in the register file 111 again.

As described above, when the first arithmetic unit 104a having no branch instruction execution function and the second arithmetic unit 105 having the branch instruction execution function are provided, the branch instruction execution control can be performed.

Next, a pipeline in the case where the first instruction register 102 has a branch instruction and the second instruction register 103 has an ADD instruction will be described with reference to FIG.

First, the branch instruction 21 is set to the second instruction in n cycles.
This is executed on the computing unit 105 side. Then, a branch determination is made at the operation stage of the branch instruction 21 and the next n + 1
In the cycle, the ADD instruction 22 is also sent to the second arithmetic unit 105.
Run on the side. In the n + 2 cycle, since the branch determination has not been decided yet, it becomes an invalidation cycle, and in the n + 3 cycle, the SUB instruction 23 and the AND instruction 24 at the branch destination are read and the execution of these two instructions is started.

That is, when this method is used, the branch instruction is executed only on the side of the second arithmetic unit 105. Therefore, it is sufficient to provide only one side such as a decoder or control logic for decoding the branch instruction and performing an operation. As the first decoder 106
Therefore, the hardware quantity of the first arithmetic unit 104a can be reduced.

Furthermore, the data path 114 of the instruction address for inputting the instruction address necessary for calculating the branch destination address input from the program counter 110 is also the first arithmetic unit 1
Since it is not necessary in 04a, it can be deleted.

Therefore, even in an information processing apparatus having a configuration in which integer arithmetic units with the branch instruction execution function removed are mixed, the branch instructions are effectively distributed and executed, thereby reducing the amount of hardware and lowering the performance. You can build a system that does not have it.

Therefore, according to the information processing apparatus 100 of this embodiment, the branch instruction detection circuit 109 detects the branch instruction, and the selector 101 determines that the integer arithmetic unit capable of executing the branch instruction is the second arithmetic unit 105. By executing the operation in the arithmetic unit, parallel processing of instructions can be realized without providing the hardware amount for executing the branch instruction in the first arithmetic unit 104a, and the hardware amount can be reduced and the apparatus can be downsized. And the cost can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the case where two integer arithmetic units of the above-mentioned embodiment are provided has been described, but the present invention is not limited to the above-mentioned embodiment and is widely applicable to the case where three or more integer arithmetic units are provided. .

If a plurality of integer arithmetic units are provided,
Only one integer arithmetic unit having a branch instruction execution function is required.

[0063]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, according to the present invention, an integer arithmetic unit capable of determining whether an instruction to be executed is a branch instruction by the branch instruction detecting means and the branch instruction selecting means and executing the branch instruction when the instruction is a branch instruction. A branch instruction can be executed by passing control to.

Further, the instruction address input means conventionally provided for each arithmetic unit need only be provided in the integer arithmetic unit having the branch instruction execution function, and the physical quantity of the instruction address input unit can be reduced.

Furthermore, by combining an integer arithmetic unit having a branch instruction execution function and an integer arithmetic unit not having a branch instruction execution function, instructions can be executed in parallel as in the conventional case. The execution function of can be omitted in a plurality of integer arithmetic units.

As a result, the amount of hardware can be reduced without degrading the performance of the information processing apparatus, and the information processing apparatus can be downsized and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus that is an embodiment of the present invention.

FIG. 2 is a schematic explanatory diagram showing a pipeline of a branch instruction and its subsequent instruction control in the arithmetic unit configuration of the present embodiment.

FIG. 3 is a schematic explanatory diagram showing branch instruction control in a single pipeline system.

FIG. 4 is a schematic explanatory diagram showing a pipeline of a branch instruction and a delay slot instruction control in a single pipeline method and an instruction execution order.

FIG. 5 is a schematic explanatory diagram showing a pipeline of a branch instruction and a delay slot instruction control in the superscalar method.

FIG. 6 is a block diagram showing a configuration of a conventional information processing device.

FIG. 7 is a schematic explanatory diagram showing a pipeline of a branch instruction and a delay slot instruction control in the second arithmetic unit.

[Explanation of symbols]

21, 34, 40, 60, 71 Branch instruction 22 ADD instruction 23 SUB instruction 24 AND instruction 30, 44 Instruction read stage (iF) 31 Decode stage (D) 32 Operation stage (E) 33 Write stage (W) 35, 36 , 42 Invalidated instructions 37, 43 Branch destination instruction 38 Instruction read stage (iF) 41 of branch destination instruction 41, 61, 72 Delay slot instruction 62 Branch operation stage (E) 100 Information processing device 101 Selector (branch instruction Selection means) 102 first instruction register 103 second instruction register 104, 104a first arithmetic unit 105 second arithmetic unit 106 first decoder 107 second decoder 108 parallel execution determination circuit 109 branch instruction detection circuit (branch instruction detection means) 110 Program counter 111 register File 112 First command valid signal 113 Second command valid signal 114 Command address data path (command address input means) 115, 116 Control information

Claims (6)

[Claims] 1. A pipeline type information processing apparatus having a plurality of integer arithmetic units and processing a plurality of instructions in parallel, the integer arithmetic unit having a function of executing all integer arithmetic operations including branch instructions; An information processing apparatus comprising: an integer arithmetic unit having a function of executing all integer arithmetic operations other than instructions, and performing parallel processing of the plurality of instructions by combining the integer arithmetic units. 2. The instruction code of a branch instruction is distributed to an integer arithmetic unit having a branch instruction execution function, the branch instruction is decoded, and the arithmetic operation is performed by the integer arithmetic unit. Information processing equipment. 3. The information processing apparatus according to claim 1, further comprising branch instruction detecting means for determining whether or not the instruction to be executed is a branch instruction. 4. The information processing apparatus according to claim 1, further comprising branch instruction selecting means for distributing the instruction code of the branch instruction to integer arithmetic units having a branch instruction execution function. 5. An instruction address input means for inputting an instruction address from a program counter is provided only in the integer arithmetic unit having the branch instruction execution function, and the instruction address input means is used in the integer arithmetic unit only for the instruction. The information processing apparatus according to claim 1, wherein an address is input and a branch destination address is calculated. 6. The integer arithmetic unit having the branch instruction execution function is provided in the plurality of integer arithmetic units, and the instruction address input means is provided only in the integer arithmetic unit having the branch instruction execution function. The information processing apparatus according to claim 1, wherein: