JPH06301534A - Information processor - Google Patents

Abstract

PURPOSE:To return a state of an execution pipeline to an original state by simple control, even in the case a branch prediction fails. CONSTITUTION:A computing element 11 is provided with a first execution pipeline consisting of arithmetic parts 111, 112 and 113, and registers 114A, 115A and 116A, and a second execution pipeline consisting of the arithmetic parts 111, 112 and 113, and registers 114B, 115B and 116B. In the course of executing an instruction before a branch instruction, a first execution pipeline is used, and in the case of executing a preceding execution instruction after the branch instruction, a second execution pipeline is used. Its switching is executed by a decoder 17, a control part 18, a flag 19, a flag control part 20 and an OR circuit 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which operations are pipelined and instructions are executed in advance by static or dynamic branch prediction.

[0002]

2. Description of the Related Art In recent years, in information processing devices such as microprocessors, in order to increase the execution speed of instructions, not only the entire device is pipelined, but also the arithmetic unit is pipelined.

As an information processing apparatus having such a pipeline type arithmetic unit, for example, "i860 Micr
oprocessor Architectur, pages 44-48 ".

In this microprocessor, the floating point arithmetic unit is pipelined. Specifically, a 32-bit single precision floating point adder and multiplier are realized by a three-stage pipeline.

In this microprocessor, a pipeline instruction is prepared as an instruction for controlling the above-mentioned arithmetic unit.

When this pipeline instruction is executed, the execution pipeline of the arithmetic unit is advanced by one stage. After this, the execution pipeline is not advanced again until the pipeline instruction using the corresponding arithmetic unit is executed again. In this case, an instruction that does not use the corresponding arithmetic unit proceeds without affecting the state of this pipeline.

In the above microprocessor, the execution result of the previously executed pipeline instruction is stored in the destination register designated by the operand of each pipeline instruction, not the execution result of the pipeline instruction. To be done.

FIG. 2 shows an example of the operation of the adder according to the pipeline instruction. In the illustrated example, the execution pipeline has the configuration shown in FIG.

FIG. 2A shows the contents of the registers f2 to f16 before executing the instruction sequence. FIG. 7B shows the state of the execution pipeline (addition pipeline) in the first execution cycle E1 of each instruction when the instruction sequence shown in FIG. 3A is executed with respect to the registers f2 to f16 having this content. Show.

In FIG. 2B, pfadd indicates a pipeline instruction designating addition. This add instruction has three operands. Here, the first operand and the second operand indicate a source register for addition, and the third operand indicates a destination register.

The register f0 is a register that always holds 0. Therefore, when this register f0 is designated as the destination register, the output of the execution pipeline is discarded.

As shown in FIG. 2B, the execution pipeline is advanced by one stage each time each add instruction is executed. In this case, the execution pipeline is not satisfied until the third add instruction is executed. Therefore, the output of the execution pipeline until the third add instruction is executed is discarded.

The execution result of the first addition instruction is output from the execution pipeline in the first execution cycle of the fourth addition instruction. Therefore, this execution result is stored in the destination register f12 designated by the third operand of the fourth add instruction.

Similarly, the execution result of each addition instruction is as follows.
It is stored in the destination register designated by the add instruction after the number of stages of the execution pipeline is 3 minutes.

As described above, in the case of continuously executing the instructions that do not depend on the execution result of the previous instruction, the pipeline instruction is used to enable the high-speed operation.

In the case of the pipeline method, a pipeline delay caused by the execution of a branch instruction, that is, a branch penalty becomes a problem.

As a method for reducing this branch penalty, there are a delay branch method and a branch prediction method. The latter is described in, for example, "Information Processing Society of Japan Material, Computer Architecture 86-3: Branch Pipeline of DSN Superscalar Processor Prototype".

Here, the delayed branch method is provided with one or more delay slots behind the branch instruction, and the instruction inserted in this delay slot (hereinafter, referred to as "delay slot" until the branch is confirmed). It is the one that executes an instruction.

On the other hand, the branch prediction method is to dynamically or statically predict the branch direction, execute an instruction in the predicted direction until the branch is determined, and execute the executed instruction when the prediction fails. Is invalidated.

This branch prediction method includes a dynamic branch prediction method and a static branch prediction method. Here, the dynamic branch prediction method is a method of predicting a branch direction every time a branch instruction is taken out. On the other hand, the static branch prediction method is a method in which the compiler predicts the branch direction in advance.

In the microprocessor described above,
The delayed branch method is adopted. In this case, a delay slot is always provided for the unconditional branch instruction and the call instruction. In contrast, conditional branch instructions may or may not have a delay slot.

When a branch is taken as a result of the execution of a branch instruction having a delay slot (hereinafter referred to as "delayed branch instruction"), the execution of the delay slot instruction is valid, and when the branch is not taken, it is invalid. It The compiler can optimize the code by properly using such instructions.

However, in the microprocessor having the pipeline type arithmetic unit as described above, if the total number of pipeline stages is increased, the determination as to whether or not the branch is taken is relatively delayed.

As a result, if the delay branch method is adopted as the branch penalty mitigation method, the number of delay slots increases. As a result, it is very difficult for the compiler to fill all delay slots with valid instructions.
Therefore, it is more effective to adopt the branch prediction method in the microprocessor as described above.

[0025]

However, if the branch prediction method is adopted in the microprocessor as described above, if the branch prediction fails, the control of the execution pipeline becomes complicated and the hardware increases. Occurs.

That is, in the branch prediction method, if the branch prediction fails, it is necessary to invalidate the instruction that was executed in advance (hereinafter referred to as "preceding execution instruction").

However, in the microprocessor as described above, when the preceding execution instruction is a pipeline instruction, in order to invalidate the preceding execution instruction, the execution pipeline advanced by that is returned by that number. There must be.

This will be described with reference to FIGS. 4, 5 and 6.

FIG. 4 shows an instruction sequence including branch instructions. Here, pfgt is a comparison instruction. This comparison instruction is the first
The contents of the register specified by the operand are compared with the contents of the register specified by the second operand. If the former is larger than the latter, the condition flag cc is set. Also, bc.t is a conditional branch instruction. This conditional branch instruction branches to the label label when the condition flag cc is set, and does not branch when the condition flag cc is reset.

FIG. 5 shows the contents of the registers before executing the instruction sequence of FIG.

FIG. 6 is a diagram showing the state of the execution pipeline (addition pipeline) in the first execution cycle E1 of each instruction when the instruction sequence of FIG. 4 is executed.

In the case of the instruction sequence shown in FIG. 4, it is determined from the execution result of the instruction (7) whether or not the branch is taken. In this case, if the branch is taken, the instruction (12) is executed,
If the branch is not taken, the instruction (8) is executed.

In FIG. 6, the pipeline state after the instruction (12) shows the state when the branch is taken, and the pipeline states of the instructions (8) to (11) do not take the branch. The case is shown.

Now, let us consider an information processing apparatus which is determined when the branch by the branch instruction (7) enters the first execution cycle E1 of the instruction (10). In this case, a 3-cycle branch penalty occurs until it is determined whether or not the branch is taken.

Branch mitigation is performed to reduce this branch penalty. FIG. 7 shows a case where the branch prediction fails, for example, when the instructions (8), (9), and (10) are executed in advance by this branch prediction.

When the state of the pipeline after the instruction (12) in FIG. 7 is compared with the state of the pipeline after the instruction (12) in FIG. 6, the two states are different. This is because in the case of FIG. 7, the operation results of the instructions (8), (9) and (10) are reflected in the execution pipeline. Therefore,
In the case of FIG. 7, in order to obtain the same result as in FIG. 6, it is necessary to return the number of execution pipelines advanced by the preceding execution of the instructions (8), (9) and (10).

As described above, in the microprocessor as described above, when the branch prediction method is adopted as the branch penalty mitigation method, when the branch prediction fails, the state of the execution pipeline advanced by the execution of the preceding execution instruction is taken into account. Need to return to. This complicates the control of the execution pipeline and increases the hardware.

The present invention has been made in order to cope with the above situation, and provides an information processing apparatus capable of returning an execution pipeline to the original state by a simple control even when a branch prediction fails. With the goal.

[0039]

In order to achieve the above object, the present invention has two execution pipelines, and by executing pipeline instructions, the execution pipeline becomes one.
Provided are arithmetic means for advancing by stages, and pipeline switching means for switching and using the two execution pipelines depending on whether an instruction before a branch instruction is executed or a preceding execution instruction after a branch instruction is executed. It was done like this.

[0040]

In the above structure, one of the two execution pipelines is used when the instruction before the branch instruction is executed.
On the other hand, when the preceding execution instruction is executed after the branch instruction, the other execution pipeline is used.

As a result, the state of the execution pipeline when the instruction before the branch instruction is executed is saved in one of the execution pipelines. So even if the branch prediction fails, you can just switch the execution pipeline from the other execution pipeline to the one
The state of the execution pipeline can be restored.

[0042]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Note that FIG. 1 representatively shows a case where the present invention is applied to an information processing apparatus having a pipeline having the configuration shown in FIG.

In FIG. 1, reference numeral 11 is a pipeline type arithmetic unit for performing arithmetic operations such as addition and subtraction based on pipeline instructions. The arithmetic unit 11 has two three-stage execution pipelines, the details of which will be described later.

Reference numeral 12 is a register file having a plurality of registers for storing data necessary for the arithmetic operation of the arithmetic unit 11 and the arithmetic result of the arithmetic unit 11. Reference numerals 13 and 14 are registers that hold the data read from the register file 12 and supply the data to the arithmetic unit 11.

Reference numeral 15 is a future file having the same structure as the register file 12. The future file 15 stores the calculation result output from the arithmetic unit 11 when the preceding execution instruction is executed. This stored content is stored in the register file 1 when the branch prediction is successful.
2 is copied.

Reference numeral 16 is an instruction register for storing an instruction fetched from a main memory (not shown). Reference numeral 17 is a decoder which decodes the instruction stored in the instruction register 16. When the decoded instruction is a branch instruction, the decoder 17 also has a function of notifying the flag control unit 20 of that fact.

A control unit 18 controls a gate group (not shown) for exchanging data based on the decoding result of the decoder 17. This control unit 18
Further, it has a function of determining whether or not a branch has been determined at the time of execution of a branch instruction and notifying the flag control unit 20 of the determination result, which will be described later, and a function of determining whether or not the branch prediction is successful.

Reference numeral 19 is a flag indicating whether the instruction currently being executed is an instruction before the branch instruction or a preceding execution instruction after the branch instruction. A flag control unit 20 controls setting and resetting of the flag 19.

When the flag controller 20 receives a notification from the decoder 12 that the decode instruction is a branch instruction,
When the flag 19 is set in the first execution cycle E1 of the next instruction (first preceding execution instruction) and the notification that the branch is confirmed from the control unit 18, the flag 17 is reset in the cycle next to this determination cycle. To do.

Reference numeral 21 denotes the output S1 of the flag 19 and the control unit 1.
It is an OR circuit that takes the logical sum of the branch prediction determination outputs S2 of 8.

The output S1 of the control flag 19 is set to 0 at the time of reset and 1 at the time of set, for example.
Is set to. Further, the branch prediction determination output S of the control unit 18
2 is normally set to 0, and when it is determined that the branch is taken, it is set to 1 only during the cycle subsequent to this determination cycle.

The arithmetic unit 11 includes arithmetic units 111, 11
2, 113 and pipeline registers 114A, 114
B, 115A, 115B, 116A, 116B and selectors 117, 118.

Here, the arithmetic units 111, 112, 113
Are the first, second, and third execution cycles E of FIG. 3, respectively.
It corresponds to 1, E2 and E3. In addition, the register 114A,
115A and 116A are used when the instruction before the branch instruction is executed, and the registers 114B, 115B and 116B are
It is used when the preceding execution instruction is executed.

In the following description, the arithmetic units 111, 1
12, 113 and registers 114A, 115A, 116A
The execution pipeline configured by is referred to as a first execution pipeline, and includes the arithmetic units 111, 112, 113 and the register 1.
The execution pipeline composed of 14B, 115B, and 116B is called a second execution pipeline.

The selectors 117 and 118 are composed of a first execution pipeline and a second execution pipeline.
It is provided to share 1,112,113.

The registers 114A, 115A, 116
A is writable and set (S1 =) when the flag 19 is reset (S1 = 0).
In the case of 1), this writing is prohibited. On the other hand, the registers 114B, 115B, 116
B is always writable regardless of the state of the flag 19.

Further, the selectors 117 and 118, when the output of the OR circuit 21 is 0, register 114A, 1
When the output of 15 A is selected and when it is 1, the register 114
It is configured to select the output of B and 115B.

The operation of the above configuration will be described.

First, the instruction fetch cycle F shown in FIG.
Then, the instruction fetched in the instruction register 16 is decoded by the decoder 17 in the next instruction decode / operand read cycle D.

If the decode instruction is a branch instruction, the decoder 17 notifies the flag control unit 20 to that effect. As a result, the flag 19 is set. As a result, the arithmetic unit 11 is informed that the instruction decoded thereafter is the preceding execution instruction. On the other hand, if the decode instruction is not a branch instruction, the flag 19 is held in the reset state.

If the decode instruction is a pipeline instruction, data is read from the register file 12 in the instruction decode / operand read cycle D based on the decode result of this instruction. This data is held in the registers 13 and 14.

The data held in the registers 13 and 14 are calculated by the calculation unit 111 in the first execution cycle E1. This calculation result is written in the two registers 114A and 114B when the flag 15 is in the reset state. On the other hand, when the flag 19 is in the set state, it is written only in the register 114B. As a result, in this case, the contents of the register 111A are protected.

The contents of the registers 111A and 111B are supplied to the selector 117. In this selector 117,
When the flag 19 is in the reset state, the register 11
4A content is selected. On the other hand, when the flag 19 is in the set state, the content of the register 11B is selected.

The selected output of the selector 117 is calculated by the calculation section 112 in the second execution cycle E2. Similar to the first execution cycle E1, this operation result is written in both the registers 115A and 115B or only in the register 115B based on the state of the flag 19.

The contents of the registers 115A and 115B are supplied to the selector 118, and depending on the state of the flag 19,
Either one is selected. This selection output is calculated by the calculation unit 113 in the third execution cycle E3. The result of this operation is based on the state of the flag 19, both of the registers 116A and 116B, or the register 116.
Only written to B.

Finally, in the write cycle W, the contents of the register 116A are written in the register file 12,
The contents of the register 116B are written in the future file 18.

As described above, when the preceding execution instruction is executed, the operation result is stored in the registers 114B, 115B, 116B.
Only through the registers 114A, 115B, 115B
The content of is protected. Therefore, when the branch prediction fails, the correct calculation result can be obtained by using the contents of the registers 114A, 115A, 115A in the subsequent calculations.

Now, the above-mentioned operation will be described in more detail.

Now, it is assumed that the instruction before the branch instruction is being executed. In this case, the output S1 of the flag 19 is set to 0. As a result, the registers 114A, 11
5A and 116A, the corresponding arithmetic units 111, 112,
The calculation result of 113 is written. Further, in the selectors 117 and 118, since the output of the OR circuit 21 is set to 0, the contents of the registers 114A and 115A are selected.

As a result, in this case, the pipeline instruction is executed by the first execution pipeline. The output of this first execution pipeline is written in the register file 12.

In this case, the state of the first execution pipeline, that is, the registers 114A, 115A, 11
The content of 6A is the register 11 of the second execution pipeline.
It is also written in 4B, 115B, and 116B.

Thus, when switching the execution pipeline from the first execution pipeline to the second execution pipeline, it is not necessary to replace the state of the second execution pipeline with the state of the first execution pipeline.

In this state, when the execution of the preceding execution instruction is started, the output S1 of the flag 19 is switched to 1.
As a result, writing to the registers 114A, 115A and 116A is prohibited. In the selectors 117 and 118, since the output of the OR circuit 21 is switched to 1, the contents of the registers 114B and 115B are selected.

As a result, the execution pipeline is switched from the first execution pipeline to the second execution pipeline. As a result, the execution state of the pipeline instruction before the branch instruction is stored as it is in the first execution pipeline.

In this case, as described above, the registers 114B, 115B and 116B of the second execution pipeline are used.
To the registers 114A, 1 of the first execution pipeline.
Since the contents of 15A and 116A are written, the second
It is not necessary to replace the state of the execution pipeline of the above with the state of the first execution pipeline.

When the branch is confirmed in this state, the flag 1
The output S1 of 9 is switched to 0. As a result, the execution pipeline is switched from the second execution pipeline to the first execution pipeline.

However, in this case, different switching needs to be performed depending on whether the branch prediction fails or succeeds.

That is, when the branch prediction fails, it is necessary to restore the state of the execution pipeline. Therefore, in this case, the execution pipeline may be switched as it is.

On the other hand, if the branch prediction is successful,
It is necessary to start executing subsequent instructions from the state of the second execution pipeline. Therefore, in this case, the state of the first execution pipeline is replaced with the state of the second execution pipeline. This replacement is performed by the branch prediction determination output S2 of the control unit 18.

That is, this branch prediction judgment output S2 is
If the branch prediction is successful, it becomes 1 only during the cycle next to the determination cycle. As a result, in this case, the switching timing of the selectors 117 and 118 is delayed by one cycle from the case where the branch prediction fails. as a result,
Registers 115B and 116A have registers 114B and 11
The contents of 5B are written. As a result, the state of the first execution pipeline is replaced with the state of the second execution pipeline.

FIG. 8 is a diagram showing the state of the execution pipeline when the branch prediction fails. Similarly, FIG. 9 is a diagram showing the state of the execution pipeline when the branch prediction is successful. 8 and 9 show the case where the instruction sequence of FIG. 2 (a) is executed. Further, the case where the instructions (8), (9), and (10) are executed in advance by branch prediction is shown.

As shown in FIGS. 8 and 9, when the execution of the branch instruction (7) is started, the next instruction (first preceding execution instruction) is executed.
In the first execution cycle of (8), the output S1 of the flag 19
Is switched from 0 to 1. This gives instructions (8)
The calculation result of is written only in the register 114B.

The selectors 117 and 118 select the contents of the registers 114B and 115B, respectively.
As a result, the contents of the registers 114B and 115B are written in the registers 115B and 116B.

As a result, the second execution pipeline advances by one stage. On the other hand, the execution content of the first execution pipeline is saved as it is. Similarly, every time the execution of the preceding execution instructions (9) and (10) is started, the second execution pipeline is advanced by one stage.

When the execution of the last preceding execution instruction (10) is started, the branch is determined. As a result, the output S1 of the flag 19 is switched to 0 in the next cycle. As a result, in the case of FIG. 8, the operation result of the instruction (12) is written in the registers 114A and 114B, and in the case of FIG.
4A and 114B are written.

On the other hand, the branch prediction judgment output S2 is held at 0 as it is when the branch prediction fails, and when the branch prediction is successful, the output S1 of the flag 19 is switched to 0 during the cycle. Only can be switched to 1.

As a result, if the branch prediction fails,
The selectors 117 and 118 select the contents of the registers 114A and 115A from the cycle when the flag 19 is switched to 0.

As a result, as shown in FIG.
The contents of the register 114A are written in 15A and 115B, and the register 11 is written in the registers 116A and 116B.
The contents of 5A are written. So in this case,
Execution of the instruction (12) starts from a state in which the state of the execution pipeline is restored.

On the other hand, if the branch prediction is successful,
The selectors 117 and 118 select the contents of the registers 114B and 115B until the cycle in which the flag 19 is switched to 0.

As a result, as shown in FIG. 9, the contents of the register 114B are written in the registers 115A and 115B, and the contents of the register 115B are written in the registers 116A and 116B. As a result, in this case, the execution of the instruction (11) starts from a state in which the state of the first execution pipeline is replaced with the state of the second execution pipeline.

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, the execution pipeline of the arithmetic unit 11 has a dual structure, and two cases are executed depending on whether the instruction before the branch instruction is executed or the preceding execution instruction after the branch instruction is executed.
Since the two execution pipelines are switched and used, even if the branch prediction fails, the state of the execution pipeline can be returned to the original state by the simple control of simply switching the execution pipelines.

(2) Further, when the instruction before the branch instruction is executed, the state of the first execution pipeline used in the execution of this instruction is written into the second execution pipeline one after another. When switching the execution pipeline from the first execution pipeline to the second execution pipeline, the process of replacing the state of the second execution pipeline with the state of the first execution pipeline becomes unnecessary.

(3) Further, the registers 114A and 114
Since the selector 117 for selectively selecting the contents of B and the selector 118 for selectively selecting the contents of the registers 115A and 115B are configured to switch between the two execution pipelines, the two execution pipelines are used. , The arithmetic units 111, 112, 113 can be shared.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiment.

(1) For example, in the above embodiment, the case where the state of the first execution pipeline is sequentially written to the second execution pipeline when the instruction before the branch instruction is executed has been described. However, the present invention omits this writing and replaces the state of the second execution pipeline with the state of the first execution pipeline when switching from the first execution pipeline to the second execution pipeline. You may

(2) In the above embodiment, the arithmetic unit 11
The case where 1, 112, 113 are shared by the first and second execution pipelines has been described. However, in the present invention, these may be provided independently for each execution pipeline.

(3) Furthermore, in the previous embodiment, the case where the execution pipeline is switched even when the branch prediction is successful has been described. However, the present invention may not switch the execution pipeline in such a case.

That is, when the branch prediction is successful, the execution pipeline used at that time may be used as it is, and the execution pipeline may be switched when the next branch instruction is encountered.

However, in this case, since it is not possible to predetermine the execution pipeline used in the execution of the instruction before the branch instruction and the execution pipeline used in the execution of the preceding execution instruction, for example, two execution pipelines are used. It is necessary to provide a changeover switch between the two files 12 and 15 and write the output of the pipeline executing the instruction before the branch instruction to the register file 12.

(4) Furthermore, in the above embodiment, the case where the present invention is applied to the information processing apparatus which adopts the branch prediction method as the branch penalty mitigation method has been described. However, the present invention can also be applied to an information processing apparatus that employs a certain kind of delay branch method.

That is, in the delayed branch method, when a branch instruction is encountered, a delay slot instruction that follows the branch instruction is always executed. Therefore, this method can be regarded as a kind of static branch prediction method. Moreover, this delay branch method has a method of canceling the delay slot instruction when the branch is not taken.

Such a scheme is no different from the branch prediction scheme. Therefore, even if an information processing apparatus adopting the delayed branch method is applied to the information processing apparatus adopting the method as described above, the present invention can be applied similarly to the information processing apparatus adopting the predictive branch method. You can

(5) In the above embodiment, the case where the decoder 17 dynamically determines whether the instruction is the instruction before the branch instruction or the preceding execution instruction after the branch instruction has been described. However, the present invention can also be applied to a method of predicting a branch direction by a compiler and adding a bit indicating in advance a conditional execution mode in an instruction. In this case, the decoder can statically make the determination based on the bits.

(6) In addition to this, it goes without saying that the present invention can be variously modified and implemented without departing from the scope of the invention.

[0107]

As described above in detail, according to the present invention, even if the branch prediction fails, the simple control enables
It is possible to provide an information processing device that can restore the state of the execution pipeline.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of a conventional pipeline type arithmetic unit.

FIG. 3 is a diagram showing an example of a pipeline configuration.

FIG. 4 is a diagram showing an example of an instruction sequence including a branch instruction.

5 is a diagram showing the contents of registers before the instruction sequence in FIG. 4 is executed.

FIG. 6 is a diagram showing states of an execution pipeline when a branch is not taken and when it is taken.

FIG. 7 is a diagram showing a state of an execution pipeline when branch prediction fails.

FIG. 8 is a diagram showing a state of an execution pipeline according to an embodiment when branch prediction fails.

FIG. 9 is a diagram showing a state of an execution pipeline according to an embodiment when branch prediction is successful.

[Explanation of symbols]

11 ... Arithmetic unit, 12 ... Register file, 13, 14 ...
Register, 15 ... Future file, 16 ... Instruction register, 17 ... Decoder, 18 ... Control unit, 19 ... Flag, 20 ... Flag control unit, 21 ... OR circuit, 111, 1
12, 113 ... Arithmetic unit, 114A, 114B, 115
A, 115B, 116A, 116B ... Pipeline registers 117, 118 ... Selectors.

Claims (1)

[Claims] 1. An information processing device in which an operation is pipelined and which executes instructions in advance by static or dynamic branch prediction, has two execution pipelines, and executes pipeline instructions. According to the above, the execution pipeline is switched by one stage, and the two execution pipelines are switched and used depending on whether the instruction before the branch instruction is executed or the preceding execution instruction after the branch instruction is executed. An information processing apparatus, comprising: