JP2869376B2 - Pipeline data processing method for executing multiple data processing with data dependency - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a pipeline data processing method for executing data processing by pipeline processing, and more particularly to a method of processing a plurality of data in parallel by a plurality of pipelines.

[0002]

2. Description of the Related Art In recent years, the performance of microprocessors has been significantly improved. The improvement of the clock frequency and the internal parallel processing greatly contribute to the performance improvement. In order to improve the former clock frequency, VLSI (Very Large Scale Integration) represented by process technology and high-speed circuit technology
ed) The progress of technology contributes, and the latter internal parallel processing greatly contributes to the progress of architecture technology represented by pipeline technology and superscalar technology.

[0003] In the internal parallel processing, the pipeline technique is a temporal parallel processing technique. By dividing a series of data processing into a plurality of stages (pipelining), a plurality of data processing is performed. It is a technique that overlaps. Further, the superscalar technology is a spatial parallel processing technology, in which a plurality of data processes are executed in parallel. By using these two techniques together, the performance of the microprocessor is improved.

Hereinafter, an example of a configuration in which a plurality of data processes are spatially parallel processed by applying the super scalar technique to a conventional pipeline data processing device that temporally parallel processes a plurality of data processes will be described. This will be described with reference to FIG.

[0005] In the figure, 150, 151 and 152
Are pipeline data processing circuits arranged in parallel with each other. With this parallel arrangement, three sets of data processing can be spatially executed in parallel. Each of the pipeline data processing circuits 150 to 152 has the same configuration as each other,
Hereinafter, the internal configuration of one pipeline data processing circuit 150 will be described as an example. In the pipeline data processing circuit 150, 118 and 119 are first and second input ports to which data is input, and 120 and 121 are first and second input ports that store data input to the input ports 118 and 119, respectively. Two registers, 130, input data stored in the two registers 120, 121, and a two-input adder / subtracter for adding or subtracting the two data, and 132, input the operation result 131 of the adder / subtractor 130. This is a register for storing.

The pipeline data processing circuits 150 to 150
Each of the pipelines 152 is pipelined into three stages: a data read stage, an operation execution stage for actually adding or subtracting the read data, and a data write stage for storing the operation result.
In FIG. 17, reference numerals 140a to 140f denote two-input adder / subtracters 1 of the respective pipeline data processing circuits 150 to 152.
The registers 140g to 140i previously store data supplied to the operation at 30, and the registers 140g to 140i respectively store the operation results output from the respective pipeline data processing circuits 150 to 152.

Next, the operation of the conventional pipeline data processing device shown in FIG. 17 will be described.

First, the following three types of addition processing C, D,
Regarding the execution of G, the addition processing C is performed by the first pipeline data processing circuit 150, the addition processing D is performed by the second pipeline data processing circuit 151, and the addition processing G is performed by the third pipeline data processing circuit 152. Let us consider the case where each is executed.

C = A + BD = E + FG = H + I Since there is no data dependency among the three processes, they can be executed completely independently. That is,
As shown in the operation timing of FIG. 18A, in the data reading stage, reading of data A and B, reading of data E and F, and reading of data H and I can be executed simultaneously. In the operation execution stage, A + B operation execution, E + F operation execution, and H + I
Can be executed at the same time. Further, in the data writing stage, writing of data C and data D
And writing of data G can be executed simultaneously. Thus, three types of data processing are executed in parallel by the three sets of pipeline data processing circuits 150 to 152.

[0010]

However, the conventional pipeline data processing device has the following disadvantages. Hereinafter, this disadvantage will be described in detail. That is, when the following three types of addition processing C, J, and G C = A + B J = E + C G = H + I are performed, the execution order is set in advance to the order of the processing C, the processing J, and the processing G. , Addition processing C in the first pipeline data processing circuit 150
Is executed by the second pipeline data processing circuit 151 and the addition processing G is executed by the third pipeline data processing circuit 152.

Here, there is a data dependency between the two processes C and J among the three types of processes. That is, the calculation of the second process J = E + C is performed by the first process C =
It is necessary to execute using the operation result of A + B, and therefore, the first operation C = A + B and the second operation J = E + C cannot be executed simultaneously. As a result, as shown in the operation timing of FIG.
The execution of the operation of the second process J = E + C needs to be started one cycle after the start of the operation of the first process C = A + B.

Here, the execution order of the second processing J and the third processing G is determined by two methods, ie, Out.
There are -of-Order method and In-Order method. The former method is a method that permits changing the order of execution between a plurality of data processing, and the latter method is a method that guarantees a predetermined execution order between a plurality of data processing and prohibits passing of processing. is there. Therefore, Out-of
-On the assumption of the Order method, the third processing G = H + I is performed in the second processing as shown in FIG.
It can be executed simultaneously with the calculation of the first process C, overtaking the first process J. On the other hand, when the In-Order method is premised, the change of the execution order is prohibited, so that the third process G is performed by the second process J as shown in FIG. Must be performed at the same time as the operation of the second process J, that is, one cycle after the operation of the first process C.

As described above, in the conventional pipeline data processing device, a plurality of data processes C and J having a data dependency depend on the In-Order method and the Out-of-O method.
Regardless of the der method, they cannot be executed at the same time. For this reason, conventionally, when there is a data dependency among a plurality of data processes, instructions for performing the processes C and J are simultaneously issued to the pipeline data processing circuits 150 and 151, respectively. Instead, the instruction of the second process J is issued one cycle later than the instruction of the first process C. In addition, when the In-Order method is premised, the subsequent instruction of the third processing G having no data dependency is also issued one cycle later than the time of issuing the instruction of the first processing C. Is done. As described above, the conventional pipeline data processing apparatus has a drawback that a plurality of data processes having a data dependency cannot be processed at high speed, and the processing speed is not improved.

The present invention has been made in view of the above drawbacks, and has as its object
Regardless of the n-Order method and the Out-of-Order method, even if there are a plurality of data processes having a data dependency, a plurality of instructions instructing these processes are simultaneously issued to the pipeline data processing circuit. A plurality of data processes having a data dependency can be appropriately executed by these pipelined data processing circuits, and furthermore, a data process having a data dependency is followed by a data process having no data dependency. Another object of the present invention is to provide a pipeline data processing method capable of issuing the subsequent data processing instruction at the same time as the data processing instruction having the data dependency, thereby improving the processing speed performance.

[0015]

In order to achieve the above object, according to the present invention, there is provided a pipeline data processing system in a super scalar technology which comprises a plurality of pipeline processing circuits and performs a plurality of data processing spatially in parallel. In the method, the number of stages is a plurality of stages obtained by adding a predetermined number to three stages of a data read stage, an operation execution stage, and a data write stage, and the data read stage and the operation execution stage are simultaneously performed among the plurality of stages. Data processing specified by each of a plurality of instructions to be issued
A configuration is adopted in which the stage can be moved to an arbitrary stage as appropriate depending on whether or not there is a dependency between the processes .

[0016] That is, the pipeline data processing method of the invention of claim 1, wherein, in the pipelined data processing method for executing a plurality of instructions to instruct each of the plurality of data processing at a plurality of pipelined data processing circuit, already executed Life inside
Order and multiple orders to be issued simultaneously.
Dependencies between data processing specified by each instruction
Detecting whether or not there is a plurality of detected data.
Depending on whether there is a data dependency between data processing,
For each of the multiple instructions to be issued, do nothing
A step of simultaneously issuing, to each of the plurality of pipeline data processing circuits, an instruction for instructing each data processing including information on the number of inserted cycles to each of the plurality of pipeline data processing circuits;
The pipeline data processing circuit is included in the received instruction.
at the time when only <br/> delay of several cycles equal to the number of insertion of the dummy cycle, you characterized by comprising a step of performing data processing the received instruction is an instruction.

[0017] invention 請 Motomeko 2 in that in the pipeline data processing method of claim 1, wherein the plurality of pipeline data processing circuit, respectively, the instruction is a data processing for instructing execution result as follows A plurality of pipeline data processing circuits having one or a plurality of passing stages for shifting to a plurality of pipeline stages, and after executing the data processing in the plurality of pipeline data processing circuits, a number equal to the number of inserted dummy cycles included in the received instruction. The passage stage is bypassed.

According to a third aspect of the present invention, there is provided the pipeline data processing method according to the first aspect of the present invention, wherein, for an instruction being executed and a plurality of instructions to be issued at the same time, the data processing is performed by each of the instructions. In the step of detecting whether or not there is a data dependency, if there is no data dependency between the plurality of data processes,
The number of cycles to be inserted is set to “0”.

According to a fourth aspect of the present invention, there is provided the pipeline data processing method according to the first aspect of the present invention, wherein, for an instruction being executed and a plurality of instructions to be issued at the same time, each of the instructions is designated by a data processing instruction. In the step of detecting whether or not there is a data dependency, if there is a data dependency among the plurality of data processes, the number x of dummy cycles inserted for each of the pipeline data processing circuits is expressed by the following equation. X = a + bc where a is the number of pipeline stages that execute data processing in a pipeline data processing circuit that is in charge of data processing that depends on the preceding data processing;
b is du to be inserted into the data processing of the pipeline data processing circuit responsible for the data processing dependent on the preceding data
The number of mmy cycles, c, is the cycle difference of the start cycle between two data processes having a data dependency.

According to a fifth aspect of the present invention, in the pipeline data processing method according to the first aspect, each pipeline data processing method comprises:
Whether the data processing circuit is executing a dummy cycle
By judging, each pipeline data processing circuit
Is in a state in which the instruction can be executed.
When there is no instruction, no instruction is issued to the pipeline data processing circuit.

[0021] According to a sixth aspect of the invention, in a pipeline data processing method of claim 1, wherein, prior to insertion calculate the number of dummy cycles, the whole or a part of the plurality of data processing having the dependencies, It is characterized in that it is replaced with data processing having no data dependency.

According to a seventh aspect of the present invention, in the pipeline data processing method of the first aspect, each pipeline data processing circuit determines whether or not each pipeline data processing circuit is executing a dummy cycle. It is determined whether or not the circuit is in a state in which an instruction can be executed. If it is determined that the instruction can be executed, the instruction is solely transmitted to one or more pipeline data processing circuits that are not executing a dummy cycle. Or, when issued at the same time, whether or not there is a data dependency between the data processing indicated by each of the currently executed instruction and the one or more instructions to be issued individually or at the same time. And, depending on the presence or absence of the detected data dependency, perform no operation on the one or more instructions issued individually or simultaneously at the same time. wherein the inclusion of inserting information of the number of mmy cycle.

According to the above construction, claims 1 to 5
In the pipeline data processing method described in No. 7 , a plurality (for example, three) of pipeline data processing circuits are arranged in parallel. A plurality (three) of data processes have a data dependency with each other (for example, process C = A + B, process J = E +
C, process K = H + J), a plurality of instructions for instructing the plurality of data processes are simultaneously issued to the pipeline data processing circuit. In the pipeline data processing circuit that performs the first data processing C, the dummy cycle
The number of inserted data is “0”, and the data read stage and the operation execution stage are allocated to the first and second stages . Also , in the pipeline data processing circuit that performs the second data processing J , insertion of a dummy cycle is performed.
The number is “1”, and the data read stage and the operation execution stage are allocated to the second and third stages.
You. Further , in the pipeline data processing circuit that performs the third data processing K, the number of inserted dummy cycles is “
2 ", and a data read stage and an operation execution stage are allocated to the third and fourth stages. Therefore, a plurality of data processes C, J, and K are sequentially executed, and a data dependency relationship between these data processes. , These data processes will be executed properly.

Here, the plurality of data processes C, J, K
Are issued at the same time, and the subsequent instruction (that is, the instruction instructing the fourth data processing) is issued in the second cycle. Conventionally, the fourth instruction is issued in the fourth cycle. Therefore, according to the present invention, it is possible to issue a large number of continuous instructions without delay, and to execute a plurality of data processes having a data dependency at a high speed.

In particular, in the inventions according to claims 5 and 7,
Dummy cycle in data processing of issued instruction
Is executed, that is, in a situation where execution of the next instruction is impossible,
Pipeline data during execution of this dummy cycle
The next instruction is not issued to the processing circuit and the dummy cycle
For pipeline data processing circuits that are not executing
Only the next instruction is issued. Therefore, each instruction dictates
Data processing is performed by each pipeline responsible for this data processing.
Data processing circuit without causing resource hazards.
It is executed well.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A pipeline data processing method according to an embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a processor, 2a is an instruction memory for storing an instruction program in advance, and 2b is a data memory for storing a large number of data in advance. The instruction memory 2a and the data memory 2b do not need to be separated from each other, and a large number of instructions and data may be mixed and stored in one memory.

The processor 1 comprises an instruction control unit 3 and an instruction execution unit 4 for executing instructions such as data arithmetic processing. The instruction control unit 3 includes an instruction fetch unit 5, an instruction register 6, an instruction decoding unit 7, and an instruction issuance control unit 8. The instruction fetch unit 5 generates one or more instruction addresses, sends the instruction addresses to the instruction memory 2a, and fetches one or more necessary instructions. The fetched instruction is stored in the instruction register 6 by the instruction fetch unit 5. The instruction decoding unit 7 decodes the instructions stored in the instruction register 6 for each of a plurality of (for example, three) instructions. The instruction issuance control unit 8 stores a resource corresponding to the instruction based on the decryption result.
(resource), the instruction is issued to the instruction execution unit 4 when the instruction instructs data processing, while the instruction fetch is performed when the instruction is a branch instruction that controls the flow of the instruction program. Issue to Part 5. Furthermore, when the instruction issuance control unit 8 issues an instruction to the instruction execution unit 4, the instruction issuance control unit 8 states the state of resources necessary for execution of the instruction in the instruction execution unit 4 and a plurality of instructions. A check is made to see if there is a data dependency between the data, and as a result, only the instructions that can be issued are issued to the instruction execution unit 4. The internal configuration and operation of the instruction issuance control unit 8 will be described later in detail.

The instruction execution section 4 comprises a register file 9 for temporarily storing data, an execution processing section 10 for performing data operation, and an execution control section 11. The execution control unit 11 reads (loads) data necessary for data calculation in the execution processing unit 10 from the data memory 2b, and stores the data in the register file 9 (store).
Then, when the actual operation is executed in the execution processing unit 10,
The execution processing unit 10 reads out the data stored in the register file 9 and executes an operation according to the instruction.
Is stored in the register file 9.

For the data operation by the processor 1, pipeline processing is performed. As shown in FIG. 2, this pipeline processing includes five stages. In the first stage, instruction fetching, in the second stage, instruction decoding and instruction issuing, and in the third stage, data reading from the register file 9 are performed. In the fourth stage, execution of data operation is performed, and in the fifth stage, the operation result is written in the register file 9. Note that the second and third stages may be performed in one stage.

FIG. 3 shows a specific configuration of the execution processing unit 10 in the pipeline data processing device. In the figure, reference numerals 100, 101 and 102 denote pipeline data processing circuits arranged in parallel with each other. Each of the pipeline data processing circuits 100 to 102 has the same configuration as one another. Therefore, the internal configuration of the pipeline data processing circuit 100 will be described using the pipeline data processing circuit 100 as an example. In the figure, 1
8, 19 are first and second data input ports,
The data from the register file 9 is input. 2
0 and 21 are first and second data input registers for storing data input from the data input ports 18 and 19, respectively, and 30 is the two data input registers 20, 2
This is a two-input arithmetic unit (data arithmetic circuit) for inputting data stored in 1 and adding or subtracting both data.

Further, reference numeral 40 denotes a first (intermediate) pipeline register arranged downstream of the arithmetic unit 30, and reference numeral 60 denotes a second (intermediate) pipeline register arranged downstream of the first pipeline register 40. And 70 are selectors (path switching circuits) arranged at a stage subsequent to the second pipeline register 60. The first pipeline register 40 receives and stores the data operation result 31 output from the operation unit 30. The second pipeline register 60 includes the first pipeline register 40.
Input and store the output data. Further, the selector 70 stores the data operation result 31 output from the operation unit 30 and the first and second pipeline registers 4.
Data and data stored in 0 and 60 are input, and one of them is selected and output. 81 is the selector 7
This is the final pipeline register that inputs and stores output data 80 of 0.

Each of the pipeline data processing circuits 100
-102 are the registers 20, 21, 4 included therein.
As shown in FIG. 4, 0, 60 and the selector 70 are controlled by the execution control unit 11 of FIG. 1 (only one pipeline data processing circuit 100 is shown in FIG. 4). 9a to 9i are the register files 9
Shows the registers inside.

The pipeline data processing circuit 10
0 may be configured by the pipeline data processing circuits shown in FIGS. The pipeline data processing circuit 120 shown in FIG. 5 is obtained by increasing the number of pipeline stages of the pipeline data processing circuit 100 of FIG. 4 by one. That is, in FIG. 4, another pipeline register 90 is placed between the selector 70 and the final pipeline register 81.
And another selector (path switching circuit) 91. The other pipeline register 90 is connected to the selector 7
A selection result of 0 is input and stored. The other selector 9
Reference numeral 1 denotes an operation result 31 of the operation unit 30, each intermediate (first and second) and the other pipeline registers 40, 60, and 9
The data stored in each of 0 are input, and any one of the data is selected and output. Second selector 9
The output 92 of 0 is input to the final pipeline register 81 and stored. The pipeline data processing circuit 130 shown in FIG. 6 is a circuit in which one pipeline register 30a is built in a computing unit 30 ', and performs two operations of addition or subtraction.
It is a pipeline of stages. In the pipeline data processing circuit 140 of FIG. 7, the first selector 52 is provided between the first and second pipeline registers 40 and 60.
In this configuration, a second selector 72 is arranged between the second and final pipeline registers 60 and 81. The first selector 52 inputs the operation result of the operation unit 30 and the data stored in the preceding stage (first) pipeline register 40, and selects and outputs any one of the data. The second selector 72 receives the selection result of the first selector 52 and the data stored in the preceding (second) pipeline register 60, selects any one of the data, and sends the selected data to the final pipeline register 81. Output. The arithmetic unit 30 of the pipeline data processing circuits 120 and 140 shown in FIGS.
May be configured by the arithmetic unit 30 'of the pipeline data processing circuit 130 in FIG. The three pipeline data processing circuits 100 to 102 shown in FIG. 1 may be configured by combining any one or a plurality of types of the processing circuits 120 to 140 described above. In such a case, it is necessary to use the same number of pipeline stages.

Next, before describing the operation when a plurality of operations are executed in parallel by the pipeline data processing apparatus shown in FIG. 3, first, one pipeline data processing circuit (for example, 100) alone The execution of two operations will be described. Since the basic operations of all the pipeline data processing circuits shown in FIGS. 4 to 7 are the same, a description will be given below using the pipeline data processing circuit 100 of FIG.

The pipeline data processing circuit 100 can execute data processing at three types of timings shown in FIGS. 8, 9 and 10. 8 to 10,
Each cycle for explaining the timing of pipeline processing is defined as first to fifth cycles, and each stage in hardware for explaining the flow of data in the pipeline data processing circuit 100 is defined as a data read stage and an arithmetic execution Stage, Tough Stage (1)
(First pass stage), Tough stage (2)
(2nd pass stage) and a data write stage. Data processing is basically executed by five pipeline stages. 8 to 10, the timing of the pipeline processing is associated with the actual data flow in the pipeline data processing circuit.

FIG. 8 shows the pipeline data processing circuit 10.
0 indicates the most basic operation. Data processing (eg C =
The execution of (A + B operation) is executed as follows. The selector 70 selects the output of the second pipeline register 60. In the first cycle, in the data read stage, data A and B are read and stored in the input registers 20 and 21, respectively. In the second cycle, A + B operation is executed in the operation execution stage, and the operation result C is stored in the first pipeline register 40. In the third cycle, the data (operation result C) is
After passing through the high stage (1), the value is stored in the second pipeline register 60 as it is. In the fourth cycle, the data (operation result C) passes through the Tough stage (2) and is stored in the third pipeline register 80 as it is. That is, in these two Through stages, no processing or processing is performed on the data (calculation result C), and the data merely moves to the next stage in sequence. In the fifth cycle, the operation result C is written in the data write stage. In FIG. 8, data flows through the pipeline data processing circuit 100 without delay.

FIG. 9 shows an example in which the first cycle of the five-stage pipeline is a Dummy cycle. The selector 70 selects the output of the first pipeline register 40. In the first cycle (Dummy cycle), nothing is executed and the pipeline is also held. That is, even if the timing shifts to the next second cycle, actual data does not advance from the data read stage to the next operation execution stage. In the second cycle, for the first time, data A
And B are read in the data read stage and stored in the registers 20 and 21, respectively. In the third cycle, the operation of A + B is executed in the operation execution stage, and the operation result C is stored in the first pipeline register 40. In the fourth cycle, the operation result C is Trough
(1) The signal passes through the stage and is stored in the third pipeline register 80 via the selector 70. In the fifth cycle, the operation result C is written in the data write stage. That is, the data from the Tough (1) stage (that is, the operation result C stored in the first pipeline register 40) bypasses the Tough (2) stage and proceeds to the data write stage.

Here, important matters are as follows. That is, when the first cycle is a Dummy cycle, the next data processing (for example, L = J +
Data J and K of K) cannot be input. In this case, since the data read stage is first entered in the second cycle, the data A and B currently being executed proceed to the operation execution stage, that is, shift to the third cycle, and the input of the next data J and K is performed for the first time. Becomes possible.

FIG. 10 shows that Dum is applied to the first and second cycles.
FIG. 11 is an operation explanatory diagram when a my cycle is inserted. The selector 70 selects the output of the arithmetic unit 30. First and second
In the cycle (Dummy cycle), nothing is executed and the pipeline is also held. That is, even if the timing shifts to the next third cycle, the actual data A and B are
It does not proceed from the data read stage to the operation execution stage. In the third cycle, for the first time, data A and B are read in the data read stage and stored in the input registers 20 and 21, respectively. In the fourth cycle, the operation of A + B is executed in the operation execution stage, and the operation result C is stored in the third pipeline register 80 via the selector 70. In the fifth cycle, the operation result C is written in the data write stage. That is, the data (the operation result C) from the operation execution stage proceeds to the data write stage, bypassing the Tough (1) and (2) stages.

Here, important matters are as follows. That is, when the first and second cycles are Dummy cycles, data for the next data processing cannot be input until the third cycle. In this case, since the data read stage is the first in the third cycle, the currently executing data A and B proceed to the operation execution stage, that is, shift to the fourth cycle, and the next data can be input for the first time. Become.

Next, the internal configuration of the instruction control controller 8 shown in FIG. 1 will be described. As shown in the figure, the instruction issuance control unit 8 includes a data dependency detection unit 8a and a resource hazard control unit 8b.
And an issue control unit 8c. The data dependence detection unit 8a receives the instruction decoding information from the instruction decoding unit 7 and based on the decoding information of a plurality of (three) instructions,
Data processing (for example, C = A + B,
E = C + D, G = E + F) is detected. The resource hazard control unit 8b receives a signal indicating that each of the pipeline data processing circuits 100 to 102 is executing the Dummy cycle shown in FIGS. 9 and 10 (Dummy cycle execution signal). Is determined to be a resource hazard at the time of reception, and the resource hazard signal is transmitted to the issuance control unit 8c. The issuance control unit 8
c determines whether each of the pipeline data processing circuits 100 to 102 is in a state in which an instruction can be executed,
When it is determined that execution is possible, it is determined whether or not the Dummy cycle shown in FIGS. 9 and 10 is to be inserted, and if it is, the number of Dummy cycles to be inserted is determined. The one or more instructions are added to the execution control unit 11 so that the instructions are executed by the executable pipeline data processing circuit.
Is sent to

The issue control unit 8c determines whether or not each of the pipeline data processing circuits 100 to 102 is in a state where an instruction can be executed. This is performed by determining whether or not the cycle is in progress, and if not in the Dummy cycle, it is determined that execution is possible.

Further, Dum in the issuance control unit 8c
The insertion of the my cycle and the determination of the number of inserted Dummy cycles are performed as follows. That is, first, it is determined whether there is a data dependency between the already executed data processing and the data processing to be executed this time, and between a plurality of data processing to be executed simultaneously. As a result, when there is no data dependency, the number of dummy cycles = 0, that is, it is determined not to insert a dummy cycle. On the other hand, if there is a data dependency,
The number of my cycles is determined as follows. For easy understanding, for example, as shown in FIG. 11, the execution order is C = A +
Consider the case of three data processes in the order of B, D = E + C, G = F + D. The number of dummy cycles is determined in order from the data processing to be executed first. The number of pipeline stages of the arithmetic unit 30 in the pipeline data processing circuit that executes the data processing D (or G) having a data dependency with the preceding data processing C (or D) (in the pipeline data processing circuit of FIG. 1 "," 2 "in the pipeline data processing circuit of FIG. 6) is denoted by a symbol a (hereinafter, a = 1 as an example of the pipeline data processing circuit of FIG. 4), The number of dummy cycles inserted in the data processing of the pipeline data processing circuit performing the processing C (or D) is represented by the symbol b, and the cycle of the start cycle between data processing having the data dependency (C and D, D and G) Assuming that the difference is a symbol c, the number of dummy cycles x
Is determined by the following equation: x = a + bc.

In the example shown in FIG. 11, the first data processing C = A + B does not have a preceding data processing having a data dependency, so the number of dummy cycles is “0”.
The second having the data dependency with the first data processing C
In the data processing D = E + C, the dummy cycle number b of the dependent data processing C is “0”, and the difference c between the start cycles between the two data processings is “0” (simultaneous execution). The number x is 1 + 0-0 = 1 cycle. In a third data processing G = F + D having a data dependency with the preceding data processing D, the number of dummy cycles b of the dependent data processing D
Is “1”, and the difference c between the start cycles is 0 (simultaneous execution), so that the obtained dummy cycle x is 1 + 1−0 = 2 cycles.

As can be seen from FIG. 11, for the three data processes C, D, and G having a data dependency, the first data process C is executed at the timing shown in FIG. The second data processing D possessed is executed at the timing of FIG. 9, and the third data processing G having a dependency with the preceding processing D is executed at the timing of FIG. Therefore, even if the three data processing instructions C, D, and G having these data dependencies are simultaneously issued, they can be executed without any trouble. The end of the data processing C, D, and G is guaranteed by the In-Order method.

In FIG. 1, the execution control unit 11 receives an instruction issued from the issuance control unit 8c, and performs data processing designated by the instruction in the pipeline data processing circuits 100 to 102 designated by the instruction. Let The execution control unit 11 controls the selector 70 of the designated pipeline data processing circuit, and selects d included in the corresponding instruction.
When the number of ummy cycles x is x = 0, the output of the second pipeline register 60 is used. When x = 1, the output of the first pipeline register 40 is used. 30 outputs (calculation results) are selected. Further, the execution control unit 11 controls each pipeline data processing circuit 1
When the dummy cycle is being executed in 00 to 102, a signal indicating that the dummy cycle is being executed is sent to the resource hazard control unit 8b.

Next, using a more complicated data processing sequence, the pipeline data processing method of the present embodiment will be described with reference to FIG. Consider a data processing sequence consisting of the following ten data processings.

C = A + B (1) E = C + D (2) G = E + F (3) J = H + I (4) L = J + K (5) N = L + M (6) P = N + O (7) S = Q + R (8) U = S + T (9) X = U + V (10) Of these ten data processes, all of the data processes other than (1), (4) and (8) are the same as the preceding data process. There is a data dependency between them.

In FIG. 12, first, data processing C,
The three instructions indicating E and G are decoded at the same time.
Instructions are issued simultaneously, the first data processing C is the pipeline data processing circuit 100, the second data processing E is the pipeline data processing circuit 101, and the third data processing G is the pipeline data processing circuit. Each proceeds in a circuit 102. However, there is a data dependency between the first and second data processing C and E and between the second and third data processing E and G. Since the number x of dummy cycles to be inserted into the pipeline data processing circuit 101 is a = 1, b = 0, and c = 0 in the above formula, x =
1 and the number x of dummy cycles to be inserted into the pipeline data processing circuit 102 is a
= 1, b = 1 and c = 0, so x = 2.

In the first cycle, three instructions instructing the following three data processings J, L, and N are decoded. Also,
Since the two pipeline data processing circuits 101 and 102 are each executing a dummy cycle, a resource hazard signal is generated for these processing circuits 101 and 102. As a result, only an instruction instructing the fourth data processing J is issued, and this data processing J proceeds in the pipeline data processing circuit 100. Since the fourth data processing J has no data dependency with the existing data processings C, E, and G, in the pipeline data processing circuit 100 performing the data processing J, the number of dummy cycles x is x = 0. is there.

In the second cycle, two instructions not issued in the previous cycle and an instruction designating the seventh data processing P are decoded. Pipeline data processing circuit 102
Since only the dummy cycle is being executed, a resource hazard signal is generated for the processing circuit 102. As a result, the second and third data processings L and N are designated.
One instruction is issued, and the data processing L and N proceed in the pipeline data processing circuits 100 and 101, respectively. Here, there is a data dependency between the fourth and fifth data processes J and L and between the fifth and sixth data processes L and N. Therefore, the pipeline data processing circuit 100
The number x of dummy cycles inserted into the pipeline data processing circuit 101 is x = 0 because a = 1, b = 0, and c = 1 in the above-described calculation formula.
The number of ummy cycles x is a = 1,
Since b = 0 and c = 0, x = 1.

In the third cycle, one instruction that has not been issued in the previous cycle and the eighth and ninth data processing S,
The instruction pointing to U is decoded. Since only the pipeline data processing circuit 101 is executing the dummy cycle, a resource hazard signal is generated for the processing circuit 101. As a result, the seventh and eighth data processing P, S
Are issued, and the data processing P,
S proceeds in the pipeline data processing circuits 100 and 102, respectively. Here, there is a data dependency between the sixth and seventh data processing N and P. Therefore, the number x of dummy cycles inserted into the pipeline data processing circuit 100 is a = 1, b = 1, c = 1
Therefore, x = 1. On the other hand, since there is no data dependency between the seventh and eighth data processes P and S, the dummy data inserted into the pipeline data processing circuit 102
The cycle number x is x = 0.

In the fourth cycle, one instruction not issued in the previous cycle and an instruction instructing the tenth data processing X are decoded. Pipeline data processing circuit 10
Since only 0 is performing a dummy cycle, a resource hazard signal is generated for this processing circuit 100.
As a result, two instructions instructing the ninth and tenth data processing U and X are issued, and the data processing U and X proceed in the pipeline data processing circuits 101 and 102, respectively. Here, the eighth and ninth data processing S, U
And the ninth and tenth data processing U and X have data dependency. Therefore, the number x of dummy cycles inserted into the pipeline data processing circuit 101 is a = 1, b = 0, c = 1 in the above calculation formula.
x = 0. Further, the pipeline data processing circuit 10
The number x of dummy cycles inserted in 2 is x = 1 because a = 1, b = 0, and c = 0 in the above-described calculation formula.

In this embodiment, as can be seen from FIG. 12, the time when all the ten data processing instructions are issued is the fifth cycle, and the time when all the data processing has been executed is the ninth cycle. This is the cycle cycle. On the other hand, when the above-described data processing sequence is executed by using the conventional pipeline data processing apparatus shown in FIG. 17, as shown in the timing chart of FIG. Is the eighth cycle, and the point at which execution of all data processing is completed is the tenth cycle.

From the above, when comparing the embodiment of the present invention in FIG. 12 with the conventional example in FIG. 13, the pipeline data processing method according to the embodiment of the present invention has higher performance in terms of operating speed. It can be seen that the improvement has been achieved.

FIG. 14 shows another pipeline data processing device.

In this embodiment, in addition to the configuration of FIG.
Three pipeline data processing circuits 103 to 105 having the same configuration are provided in parallel. Each of the pipeline data processing circuits 103 to 105 has three or more multi-input (three-input in the figure) type operation unit 30 ″, and corresponding to the three-input type, three data input ports 17 to 19, and three data input registers 20 to 22 for storing data to be input to these ports, respectively. The data stored in the data input registers 20 to 22 is stored in the three-input arithmetic unit 30 ''. Input and add / subtract. Other configurations are
Since the configuration is the same as that of the pipeline data processing circuit of the first embodiment shown in FIG. 4, the same portions are denoted by the same reference numerals and description thereof will be omitted. Note that in FIG.
9r indicates a register in the register file 9.

FIG. 15 shows a main configuration of a processor including the pipeline data processing device of FIG. The overall configuration of this processor is the same as the configuration of the processor of FIG. 1 shown in the first embodiment, and only different points will be described below. The processor of FIG. 15 differs only in the issue control unit 8c 'of the instruction issue control unit 8'. The issuance control unit 8c 'changes each data process so as to eliminate the data dependency between the plurality of data processes. That is, for example, in a plurality of (two) data processes having a data dependency relationship of C = A + BD = E + C shown below, After that, an instruction instructing the data processing D is issued, and this instruction is executed by the pipeline data processing circuit 103 having the three-input arithmetic unit 30 ''. Therefore, a plurality of data processes which originally have a data dependency can be simultaneously executed in parallel as a plurality of data processes having no data dependency.

Therefore, in the pipeline data processing method according to the present embodiment, when the following six data processings having data dependency are executed, C = A + BD = E + CG = F + D H = I + G J = K + HL L = M + J As shown in FIG. 16, the elimination of the data dependency by the pipeline data processing device having the three-input arithmetic unit 30 ″,
Due to the two effects of the insertion of the dummy cycle described in the first embodiment, these elements having a data dependency 6
Two data processing instructions can be issued and executed in parallel.

In this embodiment, the arithmetic unit 30 of the pipeline data processing circuit shown in FIG.
Although it is changed to 0 '', although not shown, the arithmetic unit 30 of each pipeline data processing circuit shown in FIG. 5, FIG. 6, or FIG. 7 may be changed to a three-input arithmetic unit 30 ''. Of course.

[0062]

As described in the foregoing, according to the pipeline data processing method of the invention of claim 1 to claim 7, wherein, in parallel a plurality of data processing spatially comprises a plurality of pipeline processing circuits In super scalar technology to process, whether there is data dependency between multiple data processing
Accordingly, du to be inserted into each of a plurality of instructions issued at the same time
Having calculated the number of mmy cycles, in each pipeline comprising a plurality stages, it can become able to move the execute stage of the data processing at any stage, Out
-Regardless of the Of-Order method and In-Order method, data is exchanged between data processing indicated by a plurality of instructions.
Even if there are dependencies, issue these multiple instructions at the same time.
However, the data processing indicated by these instructions
An instruction that can be executed and that instructs subsequent data processing that has no data dependency can be issued at the same time as an instruction that instructs the preceding data processing, thereby improving the data processing speed.

In particular, in the invention of claims 5 and 7, d
Each pipeline depends on whether ummy cycle is running or not
The data processing circuit determines whether the next instruction can be executed.
Therefore, the data processing specified by each instruction is
Do not introduce resource hazards in the pipeline data processing circuit
And can be executed correctly.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an overall configuration of a processor.

FIG. 2 is an explanatory diagram of a pipeline operation.

FIG. 3 is a diagram illustrating an overall configuration of a pipeline data processing device according to the pipeline data processing method according to the first embodiment of the present invention.

FIG. 4 is a diagram showing the internal configuration of one pipeline data processing circuit that constitutes the pipeline data processing device.

FIG. 5 is a diagram showing a first modification of the pipeline data processing circuit.

FIG. 6 is a diagram showing a second modification of the pipeline data processing circuit.

FIG. 7 is a diagram showing a third modification of the pipeline data processing circuit.

FIG. 8 is a timing chart showing a basic operation of the pipeline data processing circuit.

FIG. 9 is a timing chart showing another basic operation of the pipeline data processing circuit.

FIG. 10 is a timing chart showing another basic operation of the pipeline data processing circuit.

FIG. 11 is an operation timing chart when three data processes are performed by the pipeline data processing method of the present invention.

FIG. 12 is an operation timing chart when performing a large number of data processing by the pipeline data processing method of the present invention.

FIG. 13 is an operation timing diagram when performing a large number of data processing using a conventional pipeline data processing device.

FIG. 14 is a diagram illustrating an overall configuration of a pipeline data processing device according to a pipeline data processing method according to a second embodiment of the present invention.

FIG. 15 is a diagram showing a main configuration of a processor including the pipeline data processing device.

FIG. 16 is an operation timing chart when six data processes are performed by the pipeline data processing method according to the second embodiment of the present invention.

FIG. 17 is a diagram showing an overall configuration of a conventional pipeline data processing device.

FIG. 18 is an operation timing chart showing a basic operation of a conventional pipeline data processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor 8 Instruction issue control part 11 Execution control part 17-12 Data input port 20-22 Input data register 30, 30 '2-input operation unit (data operation circuit) 30' '3-input operation unit (data operation circuit) 40th 1 (intermediate) pipeline register 52 first selector (path switching circuit) 60 second (intermediate) pipeline register 70 selector (path switching circuit) 72 second selector (path switching circuit) 81 final pipeline register 91 other selector (Path switching circuit) 100-105 Pipeline data processing circuit

Claims (7)

(57) [Claims] 1. A pipeline data processing method in which a plurality of instructions each instructing a plurality of data processes are executed by a plurality of pipeline data processing circuits, wherein a plurality of instructions which are being executed and a plurality of instructions which are to be issued at the same time are provided.
In the data processing specified by each instruction.
Detecting whether there is a data dependency , and determining whether there is a data dependency between the plurality of detected data processes.
No matter what, each of the multiple instructions issued at the same time
Including information on the number of inserted dummy cycles
Then, the step of simultaneously issuing an instruction for instructing each data processing to each of the plurality of pipeline data processing circuits, and the step of receiving each of the instructions,
To the number of inserted dummy cycles included in the instruction
After an equal number of cycles , the received instruction
Pipeline data processing method but which is characterized in that a step of performing data processing to be indicated. 2. The plurality of pipeline data processing circuits each have one or a plurality of passing stages for directly shifting an execution result of data processing designated by an instruction to a next stage. in the processing circuit, after performing the data processing pipeline data processing method according to claim 1, wherein the to bypass the passage stage number equal to the number of insertions dummy cycles included in the received command . 3. A plurality of instructions to be command and simultaneously issued in already running, Engineering for detecting whether or not the data dependency exists between the data processing that each instruction instructs each
In degree, wherein when the data dependence is not among a plurality of data processing pipeline data processing method according to claim 1, wherein the setting the number of insertions dummy cycle "0". 4. A plurality of instructions to be command and simultaneously issued in already running, Engineering for detecting whether or not the data dependency exists between the data processing that each instruction instructs each
In extent, if the data dependency exists between said plurality of data processing, for each pipeline data processing circuit, du
Calculates and sets the number of insertions x of the mmy cycle based on the following equation. x = a + bc where a is the value of the pipeline data processing circuit that is responsible for data processing that depends on the preceding data processing. Number of pipeline stages to execute data processing,
b is du to be inserted into the data processing of the pipeline data processing circuit responsible for the data processing dependent on the preceding data
The number of mmy cycle, c is pipelined data processing method according to claim 1, characterized in that the cycle difference starting cycle between two data processing having the data dependence. 5. Each of the pipeline data processing circuits is dum.
By determining whether or not the my cycle is being executed,
The pipeline data processing circuit is ready to execute instructions
Judge whether or not there is, and any pipeline data processing circuit can execute the instruction
2. The pipeline data processing method according to claim 1, wherein no instruction is issued to the pipeline data processing circuit when the pipeline data processing circuit is not in a normal state . Prior to 6. Insert calculate the number of dummy cycles, the whole or a part of the plurality of data processing having the dependency claim 1, wherein the replacing the data dependence without data processing Pipeline data processing method. 7. Each of the pipeline data processing circuits is dum.
By determining whether or not the my cycle is being executed, it is determined whether or not each pipeline data processing circuit is in an instruction executable state. If it is determined that the instruction is executable, By issuing instructions individually or simultaneously to one or more pipeline data processing circuits that are not being executed, in an already executed instruction and in the one or more instructions that are to be issued individually or simultaneously at the same time, Detecting whether or not there is a data dependency between the data processing indicated by each of the instructions, and depending on the presence or absence of the detected data dependency, the one or more instructions issued individually or simultaneously at the same time, 2. The pipeline data processing method according to claim 1, further comprising information on the number of inserted dummy cycles in which nothing is performed.