JPH06324751A - Power circuit - Google Patents

Abstract

PURPOSE:To prevent circuit current from being increased when the input power supply voltage of a low saturation type stabilized power circuit is low. CONSTITUTION:This circuit is provided with a transistor Q4 which detects a voltage difference between the correcter of a transistor Q1 for a power and the output of a driving circuit, and a transistor Q5 which is driven by the driving circuit, and which by-passes one part of the output currents of a differential amplifier A with a ground terminal Gnd. Therefore, a transistor Q3 of the driving circuit is turned to a non-saturated state, and the circuit current can be prevented from being increased. Also, driving current is limited between the V1 and V2 of an input voltage Vin, and the circuit current can be prevented from being increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a stabilized power supply circuit,
Particularly, the present invention relates to reducing the circuit current when the input power supply voltage of a power supply circuit (low saturation type) in which the emitter of the power transistor is used for the input power supply terminal side and the collector is used for the output terminal side is low.

[0002]

2. Description of the Related Art A power supply circuit using the collector side of a power transistor as an output terminal is often used because it can lower the input power supply voltage as compared with a power supply circuit using an emitter as an output terminal.

An example of this type of power supply circuit will be described with reference to the circuit diagram shown in FIG.

The electric power supplied to the input power terminal Vin is
It is applied to a load (not shown) connected between the output terminal V ₀ and the ground terminal Gnd via the power transistor Q ₁ having the collector on the output terminal side. The voltage of the output terminal V ₀ is divided by the resistors R ₁ and R ₂ and monitored, input to the negative phase side of the differential amplifier A, and the output voltage of the reference voltage source Vref is input to the positive phase side. The output of the differential amplifier A is
The power transistor Q ₁ is controlled via a driver circuit composed of the transistors Q ₂ , Q ₃ , resistors R ₄ , R ₅ and the low current source 1.

In the circuit configured as described above, the negative phase input voltage of the differential amplifier A is controlled so as to be equal to the positive phase input voltage, that is, the voltage of the reference voltage source Vref.
The voltage at the output terminal V ₀ is the load (not shown) or the input terminal Vi.
Even if the voltage of n fluctuates, it is constantly stabilized.

The above description is for the normal operating state, that is, the case where the voltage of the input power supply terminal Vin is sufficiently higher than the stabilized voltage of the output terminal V _0. Next, the voltage of the input power supply terminal Vin is Regarding the operation at the time of low, FIG.
Refer also to the explanation.

[0007] In the following description, Vin input power terminals and output terminals, respectively, and be represented by Vin and V ₀ respectively their voltage with expressed by V _0.

The output voltage of the reference voltage source Vref is also V
It is represented by ref. As shown in FIG. 3a, when the input voltage Vin is small, the reference voltage source Vref does not start up and its output voltage is 0, so the output of the differential amplifier A becomes low and the transistors Q ₂ and Q ₃ turn off. Then, the power transistors Q ₁ , are turned off and the output voltage V ₀ becomes zero.

When the input voltage Vin rises to the voltage V ₁ at which the reference voltage source Vref is moved, the output of the differential amplifier A becomes high, and the output voltage V ₀ is the input voltage Vin minus the saturation voltage of the transistor Q ₁ . It becomes a value and is almost proportional to the input voltage Vin.

When the input voltage Vin further increases and becomes higher than the stabilized output voltage V ₂ which is the sum of the saturation voltage of the transistor Q ₁ , the output voltage V ₀ is controlled to be constant.

The circuit current I _{BIAS at} this time (not including the current flowing through the load) is the input voltage Vi as shown in FIG. 3b.
When n is V ₁ or less, the transistors Q ₁ , Q ₂ , and Q ₃ are all in the off state, so that the circuit current I _BIAS does not flow.

When the input voltage Vin is between V ₁ and V ₂ , all the transistors are in the ON state.
The current regulated by the resistors R _{1 to} R ₅ becomes the circuit current.

In particular, the resistance R ₃ is smaller than the other resistances, so that the current flowing through the input power supply terminal Vin → the emitter of the transistor Q ₁ → the base → the resistance R ₃ → the transistor Q ₃ → the ground terminal Grd becomes dominant. ing. When the input voltage Vin becomes V ₂ or more, the differential amplifier A balances, the transistors Q ₂ and Q ₃ are out of the saturated state, and the predetermined circuit current I _BIAS is reached.

[0014]

The conventional power supply circuit described above has the following problems because the circuit current flows when the input power supply voltage is low.

Even when the load is small, the input power supply terminal Vin
The power supply that supplies power to the device requires a power supply capacity that is larger than the maximum value of the circuit current. That is, if there is no power supply capability,
When the power supply rises, the input power supply terminal voltage Vin cannot exceed the voltage V ₂ shown in FIGS. 3a and 3b and becomes inoperable due to the large circuit current I _BIAS .

In the case where the power supply circuit is formed of an integrated circuit by PN junction separation, when the transistor Q ₁ or the like is saturated, a strange transistor occurs, and a current flows in the strange transistor in addition to the above-mentioned circuit current. Increase the circuit current of. Moreover, the characteristics of the odd transistor are very difficult to control, and vary greatly from one manufacturing lot to another.

Therefore, the present invention limits the drive current even when the transistor is saturated even when the input power supply voltage is small,
The purpose is to supply a power supply circuit with suppressed circuit current.

[0018]

SUMMARY OF THE INVENTION According to the present invention, a power transistor having an emitter as an input power supply terminal side and a collector as an output terminal side, and a monitor voltage of an output terminal voltage as one input, and a reference voltage as the other input. And a drive circuit for controlling the power transistor by its output signal to stabilize the output terminal voltage, a collector of the power transistor and an output terminal of the drive circuit. It is characterized by comprising an inrush current prevention circuit for bypassing the output current of the differential amplifier according to the voltage difference.

[0019]

According to the above configuration, when the input power supply terminal voltage is small, the output of the differential amplifier becomes high and the power transistor is saturated. When the saturated state is detected, the inrush current prevention circuit operates and the differential amplifier is activated. By partially bypassing the output current to the ground terminal, the drive current is limited and the circuit current does not increase.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. 1 is different from the conventional example in FIG. 2 only in that a rush current prevention circuit 2 is additionally provided, and therefore the same parts are designated by the same reference numerals and the description thereof is omitted.

The inrush current prevention circuit 2 will be described.

Transistor Q ₄ is a power transistor Q
By confirming the collector of ₁ and the output voltage of the drive circuit, the saturation or non-saturation of the transistor Q ₁ is detected.

That is, when the base voltage is lower than the collector voltage of the power transistor Q ₁ which is a PNP transistor, it is saturated, and when it is high, it is unsaturated, but the transistor Q ₄ is compared with the collector of the transistor Q _1. When the drive circuit output voltage is sufficiently low, it is turned on, and the energization amount changes depending on the degree.

When the transistor Q ₄ is energized, a voltage is generated in the resistor R ₆ , the transistor Q ₅ is turned on, and the differential amplifier A
A part of the output current is bypassed to the ground terminal Grd. Then, the transistor Q _{2 of the} driver circuit,
Collector voltage of the current of Q ₃ are smaller transistor Q ₃ are raised, it acts to reduce the current of the transistor Q _4, kept eventually balanced state.

Next, the operation of the power supply circuit will be described with reference to FIGS. 3a and 3c in addition to FIG. When the input voltage Vin is lower than the rising voltage V ₁ of the reference voltage source Vref, the circuit current does not flow as in the conventional circuit diagram 2. Input voltage Vi
When n is between V ₁ and V ₂ , the output of the differential amplifier A is high and the transistors Q ₂ and Q _{3 of the} driver circuit are high.
Therefore, the power transistor Q ₁ is going to be saturated.

However, in this embodiment, the transistor Q ₄ for detecting the saturation of the power transistor Q ₁ is used.
Further, the drive current is limited because the inrush current prevention diagram constituted by the transistor Q ₅ for bypassing the output current of the differential amplifier A to the ground terminal is provided.

Comparing the circuit current I _BIAS in this state with the conventional circuit, the input power supply terminal Vin → the emitter of the transistor Q ₁ → the base → the resistor R ₃ → the transistor Q ₃ which was dominant in the conventional circuit (FIG. 2). → Ground terminal Gn
The d-route current is significantly reduced due to the limited drive current.

However, the output terminal V ₀ → transistor Q ₄
→ The current flowing through (resistor R ₆ + base of transistor Q ₅ ) increases. However, this current is
Balance where the current of ₄ is very small (because the hfe of transistor Q ₅ is large). Therefore, the peak value of I _BIAS becomes smaller than that in the conventional case as shown in the subtraction chart 3c.

Next, when the input power supply voltage Vin is equal to or higher than V ₂ (during normal operation), the differential amplifier A is balanced and the transistor Q ₁ is in a non-saturated state. Therefore, the transistor Q ₄ is turned off. The bypass circuit 2 does not work and operates in the same manner as the conventional circuit diagram 2.

As described above, according to the present invention, since the inrush current prevention circuit for bypassing the output of the differential amplifier to the ground terminal is provided, the input terminal voltage is lower than the voltage to be controlled as the output voltage. Even if it is small, it will not be a large circuit current.

Furthermore, since the power transistor is not excessively saturated, it is possible to prevent the generation of an apparent circuit current flowing through the odd transistor when the integrated circuit is formed by using the PN junction.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 Conventional circuit diagram

3A is a graph showing a relationship between an input power supply terminal voltage and an output terminal voltage, b is a graph showing a relationship between an input power supply terminal voltage and a circuit current of a conventional circuit, and c is an input of an embodiment of the present invention. Graph showing the relationship between power supply terminal voltage and circuit current

[Description of symbols] 1 constant current circuit 2 inrush current prevention circuit Vin input power supply terminal, input power supply terminal voltage V ₀ output terminal, output terminal voltage Gnd ground terminal Vref reference voltage source, reference voltage A differential amplifier Q ₁ power transistor _{Q 2, Q 3, Q 4} , Q 5 transistor _{R 1, R 2, R 3} , R 4, R 5, R 6 resistance

Claims (2)

[Claims] 1. A power transistor having an emitter on the input power supply terminal side and a collector on the output terminal side, a differential amplifier having a monitor voltage at the output terminal as one input and a reference voltage at the other input, and In a power supply circuit including a drive circuit that controls the power transistor by an output signal to stabilize the output terminal voltage, the difference according to the voltage difference between the collector of the power transistor and the output terminal of the drive circuit. A power supply circuit comprising a rush current prevention circuit for bypassing an output current of a dynamic amplifier. 2. The inrush current prevention circuit includes a first transistor that generates a current according to a voltage difference between a collector of the power transistor and an output of the drive circuit, and a current of the first transistor, The power supply circuit according to claim 1, comprising a second transistor for bypassing an output current of the differential amplifier to a ground terminal.