JPH06311197A - System and equipment for series-parallel converting transmission - Google Patents

Abstract

PURPOSE:To solve the problem of stability, cost and power consumption by suppressing circuits operating at every high speed to be minimum by outputting each channel signal to a prescribed channel by letting a transmission side add a synchronization code and an ID code and letting a reception side discriminate an ID code. CONSTITUTION:In a transmission part, two channels of data D1 and D2 are inputted from input terminals 1 and 2 and synchronization code adding circuits 3 and 4 add synchronization code common to each channel. Besides, channel ID adding circuits 5 and 6 add ID codes different at every channel. A parallel- serial conversion circuit 9 converts the two pieces of added data 7 and 8 to one piece of two-channel multiplexed serial data of a high bit rate and an interface 11 output it. In a reception part, a reception interface circuit 13 receives data 12 transmitted by way of the transmission circuit to reproduce serial data corresponding to data 10. The piece of data is converted into the two channels of the signals 16 and 17 of low bit rates by a serial-parallel conversion circuit 15 and outputted by way of a switching circuit 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial / parallel conversion transmission device for transmitting multi-channel digital signals.

[0002]

2. Description of the Related Art With the practical use of optical fiber cables in recent years, multi-channel digital signal transmission has become possible. At this time, the signals that can be synchronized are increasingly converted into a single serial signal for transmission. As an example of the prior art including the one described in JP-A-4-51792, a block diagram of a transmission unit and a reception unit of an n-channel signal transmission device is shown in FIG. 3, and this operation will be briefly described below. The multi-channel signals A1, ..., An are input in parallel, and the synchronization adding circuit 24 adds a synchronization code to the beginning of the data of each signal as shown in FIG. 4 (a).
These are parallel-serial conversion circuit 25
Serial conversion is performed to form one serial signal 26 as shown in FIG. The synchronization code added to the head of the data serves as a mark for knowing the channel of the serialized signal.

A serial signal 26 output from the parallel-serial conversion circuit 25 is serial-parallel converted by a serial-parallel conversion circuit 28 via a transmission line to be converted into n.
Book parallel signals C1 to Cn are output. At this time, when the serial-parallel conversion circuit 28 sequentially distributes each word of the serial signal 26 to the number of channels simply multiplexed, how the n parallel signals C1 to Cn are combined with the signals A1 to An. It may not be determined whether or not to correspond to, due to the influence of time delay due to the transmission path.

Therefore, in the prior art, in order to determine the channel of the parallel signal distributed from the serial signal 26, a sync detecting circuit 27 for detecting a sync code in the state of the serial signal 26 is provided. A method of controlling the serial-parallel conversion circuit 28 based on the result has been adopted. However, since the serial signal is usually a signal having a very high bit rate, the circuit for detecting the synchronization code from this signal must be composed of an element operating at a very high speed. Therefore, there are problems in terms of circuit stability, cost, and power consumption.

[0005]

In the conventional serial-parallel conversion transmission device, since the serial signal transmitted from the transmission side to the reception side is a signal having a high bit rate,
A circuit for detecting a synchronization code used for channel determination after serial-parallel conversion from the serial signal needs to be configured by an element that operates at an ultrahigh speed. Therefore, there are problems in terms of circuit stability, cost, and power consumption. The object of the present invention is to minimize the circuit operating at ultra-high speed in a serial-parallel conversion transmission device, solve the problems of stability, cost, and power consumption, and transmit the signal of each channel from a predetermined output. It is to provide a serial-parallel conversion transmission device that can be reliably obtained.

[0006]

In the present invention, in order to achieve the above object, a synchronization word common to each channel and an ID code different for each channel are added to each signal of n channels on the transmission side. In addition, a means for performing parallel-serial conversion of n digital signals and transmitting the combined serial signal to the receiving side, and a serial side-parallel conversion of one serial signal at the receiving side, the original n-channel A means for restoring the signal, discriminating the ID code added to the n-channel parallel signal at this time, and switching the output so that the signal of the predetermined channel is output from the predetermined output terminal. As the ID discriminating means, a means for discriminating the ID code as valid is used only when the same ID code has come several times in succession.

[0007]

According to the present invention, the transmitting side adds the sync code and the ID code, the receiving side discriminates the ID code, and outputs each channel signal to a predetermined channel. This stabilizes the output location of the parallel signal of each channel. Furthermore, by determining that the ID code is valid when the same ID code has come several times in succession, erroneous detection of the ID code is eliminated.

[0008]

FIG. 1 shows an embodiment of the present invention, and the operation of the present invention will be described in detail below. In the following description, the case where the input signal is two channels D1 and D2 is taken as an example. Two-channel data D1 and D2 are input from the input terminals 1 and 2, the sync code adding circuits 3 and 4 add a sync code common to each channel, and the channel ID adding circuits 5 and 6 further. A different ID code is added to each channel. Two data with the sync code and the channel ID code added.
The data 7 and 8 are converted by the parallel-serial conversion circuit 9 into one serial data 10 having a high bit rate, which is multiplexed in two channels, and output from the transmission interface 11. An example of the parallel data 7 and 8 is shown in FIG.
FIG. 5 shows the serial data 10 after parallel-serial conversion.
It shows in (b).

The above is the operation of the transmitting section. Next, the operation of the receiving section will be described. The reception interface circuit 13 receives the data 12 transmitted through the transmission line, and the serial data 14 corresponding to the serial data 10 on the transmission side.
To play. This one serial data is serial
The parallel conversion circuit 15 converts the signals into two-channel signals 16 and 17 having a low bit rate. At this time, it depends on which of the transmission side signals 7 and 8 each of the signals 16 and 17 corresponds to. It has not been determined due to the effect of time delay due to 12.

However, since the synchronization code common to each channel is added in the transmitting section, there is data capable of separating the ID code from the output regardless of which channel the serial signal is input. can get. Next, the serial-to-parallel conversion circuit 15 of the parallelized output with a low bit rate is used.
The output signal 17 is sent to the channel ID judging circuit 21, the channel ID code added by the transmitting section is decoded, and it is judged what channel this signal is. Note that only the output signal 17 is the channel ID determination circuit 2
It is sent to 1 because if one of the two channels can be determined, the other will be naturally determined. This is the same even if the number of data increases, and if one channel can be determined, the order in which the signals of each channel are repeated is determined by the operation of the parallel-serial conversion circuit 9 on the input side, so it is naturally determined. To do.

The output of the serial-parallel conversion circuit 15 is a switching circuit 1 having parallel output of 2 channels.
Sent to 8. Then, based on the signal determined by the channel ID determination circuit 21, the switching control circuit 22 causes the output signal 19 of the switching circuit 18 to match the input signal D1 and the output signal 20 to match the input signal D2. Control 18 Further, as in the other embodiment shown in FIG. 2, by inserting the channel ID validity judging circuit 23 after the channel ID judging circuit 21, malfunctions in which each signal cannot be obtained from a predetermined output due to false detection of the ID code. Can be eliminated.

An example of the configuration of the ID validity judgment circuit 23 is shown in FIG.
, And the operation when the same data is input n times is validated will be described in detail as an example. ID determination circuit 21
Determines whether the output signal 17 is 1 channel or 2 channels,
For example, 2-bit data of "10" for one channel and "01" for two channels is output. The upper bit data E1 is set to 29, and the lower bit data E1 is set.
Enter 2 into 30. Each data is shifted n times by the D-F / F circuits 31-1 to 31-n and 32-1 to 32-n,
The AND gates 33 and 34 multiply the respective outputs. Then, the OR gate 37 sums the output data 35 and 36 of the two AND gates, and if the same data continues n times, the output data 39 of the OR gate is It becomes 1 and it is determined that the ID is valid.

If different data is input even once in n times, the AND product is 0 for both the upper and lower bits, and the OR gate is obtained.
Output becomes 0 and it is determined that the ID is invalid. If the ID is valid, the latch circuit 38 causes the data 35 and 36 to pass and 4
Output to 0 and 41. If the ID is invalid, the latch circuit 38 stops the data, outputs the data before invalidation to 40 and 41, and sends the data to the switch control circuit 22. As a result, even if the output is confirmed by the ID code, the ID code is output.
It is possible to prevent the signal from not being obtained from the predetermined output immediately when the error is detected.

[0014]

As described above, when the present invention is used, the circuit that must operate at the highest speed is only the parallel-serial conversion circuit on the transmission side and the serial-parallel conversion circuit on the reception side, and synchronization detection and channel determination are possible. The switching circuits and the like may all operate at a rate of 1/2 or less. Therefore, the problems of stability, cost, and electric power, which have been problems in the conventional method, are significantly improved. Further, in the present invention, even if the channel ID code is erroneously received due to the occurrence of transmission error, the channel signal is not replaced by the wrong channel determination, and the output data is not greatly disturbed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a transmission / reception unit in a conventional technique.

FIG. 4 is a diagram illustrating a data format according to the conventional technique of FIG.

FIG. 5 is a diagram illustrating a data format in the first embodiment of FIG.

FIG. 6 is a diagram illustrating a configuration of a channel ID validity determination circuit in FIG.

[Explanation of symbols]

 1, 2, 29, 30 Input terminals 3, 4, 24-1 to 24-n Synchronous code addition circuit 5, 6 Channel ID code addition circuit 7, 8, 16, 17 Parallel data output 9, 25 Parallel-serial conversion circuit 10, 14, 26 Serial data output 11 Transmission interface circuit 12 Transmission line 13 Reception interface circuit 15, 28 Serial-parallel conversion circuit 18 Switching circuit 19, 20 Output data 21 channel ID determination circuit 22 switching control circuit 23 channel ID validity determination circuit 27 synchronization detection circuit 31-1 to 31-n, 32-1 to 32-n DF / F circuit 33, 34 AND gate 35, 36 ID validity judgment output data 37 OR gate 38 Latch circuit 39 Latch circuit switching data 40, 41 Output terminal

Claims (4)

[Claims] 1. An n (n) in which an ID code is added to a digital signal of n (n is a plurality) channels and the ID code is added
The channel digital signal is parallel-serial converted into one serial signal, and the receiving unit serial-parallel converts the one serial signal to restore n digital signals. ID of
A serial-to-parallel conversion transmission method characterized in that each code is discriminated and the output channels are exchanged. 2. The serial-parallel conversion transmission system according to claim 1, wherein the determination of the ID code includes an operation of confirming that the determined ID code is valid. 3. An ID adding means for adding an ID code to a digital signal of n (n is a plural number) channels, and the digital signal of the n channel added with the ID code is converted into one serial signal. A transmission section having parallel-serial conversion means, serial-parallel conversion means for converting the one serial signal into n digital signals,
ID for discriminating the ID code of the n digital signals
A serial-parallel conversion transmission device comprising a code discriminating means and a receiving section provided with a switching means for switching output channels. 4. The ID code validity determining means for verifying whether the determined ID code is valid or not is included in the ID code determining means. Parallel conversion transmission equipment.