JPH06310662A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent high-frequency signal power emitted from one circuit from propagating to the other adjacent circuit even if the device is very highly integrated. CONSTITUTION:MIM capacitors C1, C3, C6, C4, C10 are located at the place to separate circuits integrated on a semiconductor substrate 10. One conductor B of each of the MIM capacitors C1, C3, C6, C4, C10 is grounded through a bonding wire WE.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention forms a circuit in which an active element such as a microwave transistor and a passive circuit such as a matching circuit and an MIM capacitor are integrated on a semiconductor substrate through a microstrip line. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a down converter IC (integrated circuit) used in, for example, a mobile phone. The high frequency signal input terminal 1 to which the high frequency signal RF is input is grounded via the capacitor C ₁ and is connected to the gate of the FET 2 via the series circuit of the capacitor C ₂ and the inductance L ₁ . The gate of the FET 2 is grounded via the resistor R ₁ .
The power supply terminal 3 is grounded via a series circuit of a resistor R ₂ , a FET 2 and a resistor R _3, and a capacitor C ₃ is connected in parallel to the resistor R ₃ . The power supply terminal 3 is grounded through a series circuit of a resistor R ₄ , a dual gate FET 4 and a resistor R ₅ ,
A capacitor C ₄ is connected in parallel with the resistor R ₅ .

The drain of the FET 2 is connected to the first gate of the dual gate FET 4 via the capacitor C ₅ and is grounded via the capacitor C ₆ . Dual gate FET
The first gate of No. 4 is grounded via an inductance L ₂ . The local oscillation frequency signal input terminal 5 to which the local oscillation frequency signal LO is input is connected to the second gate of the dual gate FET 4 via the capacitor C ₇ and is grounded via the capacitor C ₈ . The second gate of the dual gate FET 4 is grounded via the inductance L ₃ .

The drain of the dual gate FET 4 is connected via a capacitor C ₉ to an intermediate frequency signal output terminal 6 which outputs an intermediate frequency signal IF, and is further grounded via a capacitor C ₁₀ . In this down converter IC, when the high frequency signal RF is input to the high frequency signal input terminal 1 and the local oscillation frequency signal LO is input to the local oscillation frequency signal input terminal 5,
The intermediate frequency signal IF is output from the intermediate frequency signal output terminal 6.

FIG. 3 is a schematic top view showing the structure of a chip in which the high frequency mixer circuit shown in FIG. 2 is integrated on a semiconductor substrate. The semiconductor substrate 10 has a square shape, and the high frequency signal input terminal 1 is provided at the intersection of the edges K ₁ and K _3.
However, the intermediate frequency signal output terminal 6 is arranged at the intersection of the edge K ₃ and the edge K _2, and the local oscillation frequency signal input terminal 5 is arranged at the intersection of the edge K ₁ and the edge K _4. Has been done.
On the edge K ₃ side, the power supply terminal 3 is arranged in the middle between the high frequency signal input terminal 1 and the intermediate frequency signal output terminal 6 facing each other.

On the edge K ₁ side of the semiconductor substrate 10, an elongated one-side conductor B ₁ having an appropriate width and forming capacitors C ₁ and C ₃ C ₆ is arranged along the edge K ₁ . . One side conductor B
The other side conductors A ₁ , A of the rectangle forming capacitors C ₁ , C ₃ , C ₆ on the upper surface of ₁ through an insulator (not shown)
₃ , A ₆ are arranged in that order at appropriate intervals.

Further, it is formed in an L shape with the same width dimension as the one-side conductor B _{1 so as} to extend over the edge K ₄ side and the edge K ₂ side to form capacitors C ₈ , C ₄ , C _10. The side conductor B ₂ has an edge K ₄
And are arranged along the edge K ₂ . Capacitors C ₈ and C ₄ are provided on one side conductor B ₂ via an insulator (not shown).
The rectangular other-side conductors A ₈ and A ₄ forming the capacitor C ₁₀ are arranged along the edge K ₄ , and the rectangular other-side conductor A ₁₀ forming the capacitor C ₁₀ is arranged along the edge K _2. There is. As a result, the capacitors C ₁ , C ₃ , C ₆ , C ₈ , C ₄ ,
At C ₁₀ , a MIM (Metal Insulated Metal) capacitor having a conductor laminated structure in which conductors are opposed to each other with an insulator interposed therebetween is formed.

The high frequency signal input terminal 1 has a capacitor C ₂
And it is connected to the gate of the FET 2 through a series circuit of an inductance L _1, directly to the other side conductor A ₁ of the capacitor C ₁
Connected with. The gate of the FET 2 is connected to the one-side conductor B ₁ via the resistor R ₁ . The power supply terminal 3 has a resistor R ₂ and a FET
2 and a resistor R ₃ connected in series to the one-side conductor B _1, and the source of the FET 2 is directly connected to the other-side conductor A ₃ . The drain of the FET 2 is directly connected to the other-side conductor A ₆ and is connected to the one-side conductor B ₁ via a series circuit of a capacitor C ₅ and an inductance L ₂ .

The connection between the capacitor C ₅ and the inductance L ₂ is connected to the first gate of the dual gate FET 4. The second gate of the dual gate FET 4 is connected to the other conductor B ₁ via the inductance L ₃ and is connected to the local oscillation frequency signal input terminal 5 and the other conductor A ₈ via the capacitor C ₇ . The power supply terminal 3 is connected to the other conductor B ₂ via a series circuit of a resistor R ₄ , a dual gate FET 4 and a resistor R ₅ . The drain of the dual gate FET 4 is connected to the intermediate frequency signal output terminal 6 via the capacitor C ₉ and also to the other side conductor A ₁₀ . The source of the dual gate FET 4 is connected to the other conductor A ₄ .

The semiconductor substrate 10 thus constructed is housed in a package (not shown), and the high frequency signal input terminal 1, the power supply terminal 3, the intermediate frequency signal output terminal 6 and the local oscillation frequency signal input terminal 5 are connected by the bonding wire W. ,
The one-side conductors B ₁ and B ₂ connected to the inner leads (not shown) corresponding to the respective terminals are connected to the ground portion of the package connecting the lower surface ground electrode formed on the lower surface side of the semiconductor substrate 10 and the bonding wire W _E , A semiconductor device is constructed by connecting with W _E.

[0011]

As described above, a circuit in which a passive circuit including an active element such as FET, MIM capacitor, and inductance is integrated on a semiconductor substrate at high density through a microstrip line is formed. Then, the intervals between the adjacent passive circuits and between the microstrip lines are narrowed to increase the coupling degree. Therefore, there is a problem in that the high-frequency signal power radiated from a part of the integrated circuits propagates to the other integrated circuits.

In view of the above problems, the present invention is to form a circuit in which an active element and a passive circuit are integrated on a semiconductor substrate,
It is an object of the present invention to provide a semiconductor device capable of suppressing the propagation of high-frequency signal power radiated from an integrated circuit to other integrated circuits.

[0013]

In a semiconductor device according to the present invention, an active element such as a microwave transistor and a passive circuit including a matching circuit and an MIM capacitor are integrated on a semiconductor substrate via a microstrip line. In a semiconductor device forming an integrated circuit, the MIM is provided at a position where a circuit in which the active element and the passive circuit are integrated is divided.
A capacitor is arranged, and one of the conductors of the MIM capacitor is configured to be grounded.

[0014]

[Function] At a position where an integrated circuit forming an integrated circuit of an active element and a passive circuit is formed on a semiconductor substrate,
When the MIM capacitor is placed and one conductor of the MIM capacitor is grounded, the integrated circuit is separated by the ground conductor. The high-frequency signal power radiated from one of the separated circuits is absorbed by the ground conductor and hardly propagates to the other circuit. Therefore, it is possible to suppress the high-frequency signal power from propagating from one circuit to the other circuit.

[0015]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 1 is a schematic top view showing a configuration of a chip of a semiconductor device according to the present invention. A circuit in which the down converter circuit shown in FIG. 2 is integrated is formed in this semiconductor device. The semiconductor substrate 10 has a square shape and has an edge K ₁
Intermediate frequency signal and the high frequency signal input terminal 1, a high frequency signal RF is input to the intersection between the edge K ₃ is, to output an intermediate frequency signal IF to the intersection between the edge K ₂ and edge K ₃ The local oscillation frequency signal input terminal 5 to which the local oscillation frequency signal LO is input is arranged at the intersection of the output terminal 6 and the edge K ₁ and the edge K ₄ .

On the edge K ₃ side, a power supply terminal 3 is arranged in the middle between the high frequency signal input terminal 1 and the intermediate frequency signal output terminal 6 facing each other. At the center position between the edge K ₃ and the edge K ₄ , L-shape is formed with an appropriate width dimension to form capacitors C ₁ , C ₃ , C ₆ , C ₄ , C ₈ , C ₁₀ . The one side conductor B common to them is arranged with its long side on the edges K ₃ , K.
It is arranged in parallel with ₄ and straddles the edges K ₁ and K ₂ .

The short side of the one side conductor B are arranged in a length reaching the edge K ₄ along the edge K _2. On the one side conductor B, capacitors C ₁ , C ₃ ,
Rectangular other conductors A ₁ , A forming C ₆ , C ₄ , C _10
3 , A ₆ , A ₄ are separated in this order by an appropriate distance and the edge K
_The L-shaped other-side conductor A that is arranged from the _first side and that forms the capacitor C ₁₀ is provided between the other-side conductor A ₄ and the edge K _2.
A part of ₁₀ is arranged at an appropriate interval. The other side conductors A ₁ , A ₃ , A ₆ , A ₄ , and A ₁₀ are all formed with the same width dimension, and are slightly smaller than the width dimension of the one side conductor B.

On one side conductor B along the edge K ₂ ,
A part of the other-side conductor A ₁₀ and a rectangular other-side conductor A ₈ are arranged at appropriate intervals with an insulator (not shown) interposed therebetween. That is, one side conductor B and the other side conductors A ₁ , A ₃ , A ₆ ,
A ₄ , A ₁₀ , and A ₈ are MIM capacitors C ₁ , C ₃ ,
It is a counter electrode for C ₆ , C ₄ , C ₁₀ , and C ₈ .

High frequency signal arranged on the semiconductor substrate 10.
The input terminal is directly connected to the capacitor C₁Other conductor A₁Contact with
And capacitor C₂And the inductance L₁Direct with
It is connected to the gate of FET 2 via a column circuit. Of FET 2
The gate has a resistance R₁One side common to MIM capacitors via
It is connected to the conductor B. Power supply terminal 3 has resistance R₂And FET 2
Through the series circuit of the other side conductor A₃Connected to FET 2
One side conductor A₃The connection with and the resistance R₃Through one side conductor B
Connected with. The drain of FET 2 is the other conductor A ₆Connect with
To be done. The power supply terminal 3 has a resistor R_FourThrough the other side
Body A_TenThe drain of FET 4 is connected to capacitor C₉
Is connected to the intermediate frequency signal output terminal 6 via.

These capacitors C ₂ , C ₉ , resistors R ₁ , R ₂ , R ₃ , R ₄ , inductance L ₁ and FET
2 is integrated on one surface side of the semiconductor substrate 10 divided by the MIM capacitors C ₁ , C ₃ , C ₆ , C ₄ , and C ₁₀ .

The local oscillation frequency signal input terminal 5 is directly connected to the other side conductor A ₈ and is also connected to one side gate of the dual gate FET 4 via the capacitor C ₇ . The second gate of the dual gate FET 4 is connected to the one side conductor B via the inductance L ₃ . The first gate of the dual gate FET 4 is connected to the one side conductor B via the inductance L ₂ and is connected to the other side conductor A ₆ via the capacitor C ₅ . The other side conductor A ₁₀ is a dual gate FET 4 and a resistor R ₅
Is connected to the one-side conductor B via a series circuit. FET 4
Is connected to the other conductor A ₄ .

These inductances L ₂ , L ₃ , capacitors C ₅ , C ₇ , resistor R ₅ and dual gate FET 4
Are integrated on the other surface side of the semiconductor substrate 10 divided by the MIM capacitors C ₁ , C ₃ , C ₆ , C ₄ and C ₁₀ . As a result, the integrated circuit on the high frequency signal input terminal 1 side and the integrated circuit on the local oscillation frequency signal input terminal 5 side are separated.

The semiconductor substrate 10 on which the integrated circuit is formed as described above is housed in a package (not shown), and the high frequency signal input terminal 1, the power supply terminal 3, the intermediate frequency signal output terminal 6 and the local oscillation frequency signal input are input. The terminals 5 are connected by bonding wires W to inner leads (not shown) in the package corresponding to those terminals. Also
The one-side conductor B of the MIM capacitor is connected by a bonding wire W _E to a ground portion in the package that connects a lower surface ground electrode (not shown) formed on the lower surface side of the semiconductor substrate 10. As a result, the one-side conductor B is also used as a ground conductor to form a semiconductor device. As a result, the circuit on the high frequency signal input terminal 1 side and the local oscillation frequency signal input terminal 5
The circuit on the side will be separated by the ground conductor.

Therefore, the local oscillation frequency signal input terminal 5
When the signal power is radiated from the integrated circuit on the side, the radiated high frequency signal power is absorbed by the ground conductor that is one side conductor of the MIM capacitor while propagating to the integrated circuit on the side of high frequency signal input terminal 1, It becomes difficult to propagate to the integrated circuit on the signal input terminal 1 side, and propagation of high-frequency signal power can be significantly suppressed. Further, since the ground conductor also serves as one side conductor of the MIM capacitor, the pattern area of the integrated circuit does not increase.

Further, since the ground conductor which also serves as the other conductor of the MIM capacitor is arranged so as to divide the semiconductor substrate in two, the portion to be grounded located on the center side of the semiconductor substrate can be short distanced. Can be grounded. In addition, the number of bonding wires can be minimized because the MIM capacitors are not distributed. Furthermore, it is possible to reduce the number of grounding probing points during DC measurement.

In this embodiment, the one conductor on the lower layer side of the MIM capacitor is the ground conductor, but the other conductor on the upper layer side may be the ground conductor. Further, although the circuit in which the down converter circuit is integrated is shown on the semiconductor substrate, it is merely an example, and the invention is not limited to the down converter circuit.

[0027]

As described above in detail, in the semiconductor device of the present invention, the MIM capacitor is arranged on the semiconductor substrate at the position where the integrated circuit is divided, and one conductor forming the MIM capacitor is formed. Since the circuit is grounded, the integrated circuit can be separated by the ground conductor. Therefore, the signal power emitted from one of the separated circuits is absorbed by the ground conductor and becomes difficult to propagate to the other circuit, and the amount of propagation can be significantly suppressed. Also, since one conductor of the MIM capacitor is also used as the ground conductor, the area occupied by the integrated circuit does not increase. Further, since the ground conductors are not arranged in a distributed manner, it is possible to reduce the number of bonding wires that ground the ground conductors.

[Brief description of drawings]

FIG. 1 is a schematic top view of a chip in a semiconductor device according to the present invention.

FIG. 2 is a circuit diagram of a down converter IC.

FIG. 3 is a schematic top view of a chip in a conventional semiconductor device.

[Explanation of symbols]

1 high frequency signal input terminal 2 single gate FET 3 power supply terminal 4 dual gate FET 5 local oscillation frequency signal input terminal 6 intermediate frequency signal output terminal C ₁ , C ₃ , C ₄ , C ₆ , C ₈ , C ₁₀ MIM capacitor A ₁ , A ₃ , A ₄ , A ₆ , A ₈ , A ₁₀ Other conductor B One conductor W, W _E Bonding wire

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI technical display location // H03D 7/00 F 7350-5J (72) Inventor Nasunori Uda 2 Keihanhondori, Moriguchi-shi, Osaka 18-chome Sanyo Electric Co., Ltd. (72) Inventor Yatsuo Harada 2--18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (1)

[Claims] 1. A semiconductor device in which an active element such as a microwave transistor and a passive circuit including a matching circuit and an MIM capacitor are integrated on a semiconductor substrate through a microstrip line. A semiconductor device, wherein the MIM capacitor is arranged at a position where a circuit in which the active element and the passive circuit are integrated is divided, and one conductor of the MIM capacitor is configured to be grounded.