JP2001085570A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2001085570A
JP2001085570A JP26191799A JP26191799A JP2001085570A JP 2001085570 A JP2001085570 A JP 2001085570A JP 26191799 A JP26191799 A JP 26191799A JP 26191799 A JP26191799 A JP 26191799A JP 2001085570 A JP2001085570 A JP 2001085570A
Authority
JP
Japan
Prior art keywords
conductor
ground
resistor
metals
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26191799A
Other languages
Japanese (ja)
Other versions
JP3913937B2 (en
Inventor
Yasushi Shizuki
康 志津木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP26191799A priority Critical patent/JP3913937B2/en
Publication of JP2001085570A publication Critical patent/JP2001085570A/en
Application granted granted Critical
Publication of JP3913937B2 publication Critical patent/JP3913937B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Landscapes

  • Waveguide Connection Structure (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device whose operation becomes stably by suppressing unwanted resonance. SOLUTION: This semiconductor device has a MMIC(monolithic microwave IC) chip 11, where at least one part of a transmission path is made of a coplanar line composed of a signal conductor 1a and grounding metals 2a1-2a3 and 2b1-2b3 positioned on both its sides. In this case, the grounding metal is divided into plural grounding metals 2a1-2a3 and 2b1-2b3, and moreover the divided ground metals 2a1-2a3, and 2b1-2b3 are connected with the others by conductors 5 and resistors 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ミリ波やマイクロ
波などの高周波信号を扱う半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device that handles high-frequency signals such as millimeter waves and microwaves.

【0002】[0002]

【従来の技術】通信分野の広がりから利用する周波数範
囲が拡大し、通信分野においてミリ波(30GHz)以
上の超高周波帯を利用する動きが出ている。
2. Description of the Related Art With the spread of the communication field, the frequency range to be used has been expanded, and in the communication field, there has been a movement to use an ultra-high frequency band of millimeter waves (30 GHz) or more.

【0003】ここで、高周波信号を利用する従来の半導
体装置について図5を参照して説明する。図5の半導体
装置は、MMIC(Monolithic Microwave Integrated
Circuit )チップ210およびMMICチップ210を
実装する実装基板220などから構成されている。MM
ICチップ210の主表面上には、HEMTなどの能動
素子、および、キャパシタや抵抗を含む集中定数回路や
分布定数回路などで構成された電気回路(図示省略)が
形成されている。これら電気回路の周囲には、複数のボ
ンディングパッド230が設けられている。
Here, a conventional semiconductor device using a high-frequency signal will be described with reference to FIG. The semiconductor device of FIG. 5 is an MMIC (Monolithic Microwave Integrated
Circuit) and a mounting substrate 220 on which the MMIC chip 210 is mounted. MM
On the main surface of the IC chip 210, an active element such as a HEMT and an electric circuit (not shown) including a lumped constant circuit and a distributed constant circuit including a capacitor and a resistor are formed. A plurality of bonding pads 230 are provided around these electric circuits.

【0004】MMICチップ210が実装される実装基
板220上には、線路導体250やボンディングパッド
260が設けられ、MMICチップ210上のボンディ
ングパッド230と実装基板220上のボンディングパ
ッド260間は、ボンディングワイヤ240で電気的に
接続されている。実装基板220上のボンディングパッ
ド260の一部は、実装基板220に形成されたスルー
ホール270を介して、実装基板220裏面のほぼ全面
に形成された接地電極280と電気的に接続されてい
る。
A line conductor 250 and a bonding pad 260 are provided on a mounting substrate 220 on which the MMIC chip 210 is mounted. A bonding wire is provided between the bonding pad 230 on the MMIC chip 210 and the bonding pad 260 on the mounting substrate 220. At 240, they are electrically connected. A part of the bonding pad 260 on the mounting substrate 220 is electrically connected to a ground electrode 280 formed on almost the entire back surface of the mounting substrate 220 via a through hole 270 formed in the mounting substrate 220.

【0005】上記した構成の半導体装置は、たとえば、
実装基板220の一部にMMICチップ210の大きさ
に見合った窪みを設け、その窪みの部分にMMICチッ
プ210を実装する方法がとられ、MMICチップ21
0の底面は接地電極280に接続されている。
[0005] The semiconductor device having the above-described structure is, for example,
A method of providing a depression corresponding to the size of the MMIC chip 210 in a part of the mounting substrate 220 and mounting the MMIC chip 210 in the depression is adopted.
0 is connected to the ground electrode 280.

【0006】次に、MMICチップ210の主表面に形
成される電気回路の一例を図6を参照して説明する。I
Nは入力端子、OUTは出力端子で、入力端子INと出
力端子OUT間に、HEMT201などの能動デバイス
やキャパシタC1、C2、整合回路を構成する分布定数
線路202a、202bが接続されている。HEMT2
01と分布定数線路202a間には、分布定数線路20
2cとキャパシタC3からなるバイアス回路が接続さ
れ、HEMT201と分布定数線路202a間には分布
定数線路202dやキャパシタC4からなるバイアス回
路が接続されている。
Next, an example of an electric circuit formed on the main surface of the MMIC chip 210 will be described with reference to FIG. I
N is an input terminal and OUT is an output terminal. Active devices such as the HEMT 201, capacitors C1 and C2, and distributed constant lines 202a and 202b forming a matching circuit are connected between the input terminal IN and the output terminal OUT. HEMT2
01 and the distributed constant line 202a.
A bias circuit composed of a capacitor 2c and a capacitor C3 is connected, and a bias circuit composed of a distributed constant line 202d and a capacitor C4 is connected between the HEMT 201 and the distributed constant line 202a.

【0007】上記した構成のMMICの場合、電気素子
間を接続する伝送線路には、図8に示すようなコプレー
ナ線路が多く使用される。図の(a)はコプレーナ線路
の上面図、図の(b)(c)は、図(a)のA−A、B
−Bにおける断面図で電界分布を矢印で示している。
In the case of the MMIC having the above configuration, a coplanar line as shown in FIG. 8 is often used as a transmission line for connecting electric elements. (A) of the figure is a top view of the coplanar waveguide, and (b) and (c) of the figures are AA and B in the figure (a).
The electric field distribution is indicated by an arrow in the cross-sectional view at -B.

【0008】図中301はコプレーナ線路を構成する信
号導体、302a、302bはコプレーナ線路を構成す
る接地メタルで、接地メタル302a、302b間は、
電位を等しくするために、信号導体301を跨いでブリ
ッジ303で接続されている。ブリッジ303は信号導
体301と接触しないように形成される。
In FIG. 1, reference numeral 301 denotes a signal conductor forming a coplanar line, and 302a and 302b denote ground metals forming a coplanar line.
In order to make the potentials equal, they are connected by a bridge 303 across the signal conductor 301. The bridge 303 is formed so as not to contact the signal conductor 301.

【0009】上記したコプレーナ線路は、信号導体30
1の両脇に等間隔に接地メタル302a、302bが配
置されている。このため、図(b)に示すように配線構
造は左右対称となり、電界分布も左右対称となる。ブリ
ッジ303の部分でも、図(c)に示すように配線構造
は左右対称となり、電界分布も左右対称になっている。
The above-described coplanar line includes a signal conductor 30.
Ground metals 302a and 302b are arranged at equal intervals on both sides of 1. For this reason, the wiring structure is bilaterally symmetric and the electric field distribution is bilaterally symmetric as shown in FIG. At the bridge 303 as well, the wiring structure is symmetrical and the electric field distribution is symmetrical as shown in FIG.

【0010】MMICにおいてコプレーナ線路を伝送線
路として用いる場合、コプレーナ線路の接地メタルを利
用して接地できる。このため、MMICチップの接地部
分を接地する場合、実装基板に接地用の貫通孔を設けな
いですむという利点がある。
When a coplanar line is used as a transmission line in an MMIC, grounding can be performed using a ground metal of the coplanar line. For this reason, when the grounding portion of the MMIC chip is grounded, there is an advantage that it is not necessary to provide a through hole for grounding on the mounting board.

【0011】[0011]

【発明が解決しようとする課題】MMICチップを実装
基板に実装する従来の半導体装置は、MMICの接地部
分と実装基板の接地導体とを電気的に同一電位にするた
めに、両者の間がボンディングワイヤなどを用いて接続
される。この状態を図7の断面図を参照して説明する。
図7では、図8に対応する部分には同一の符号を付し、
重複する説明を一部省略する。
In a conventional semiconductor device in which an MMIC chip is mounted on a mounting substrate, bonding is performed between the grounding portion of the MMIC and the grounding conductor of the mounting substrate so as to make them electrically the same potential. It is connected using a wire or the like. This state will be described with reference to the sectional view of FIG.
In FIG. 7, parts corresponding to those in FIG.
A duplicate description is partially omitted.

【0012】符号311がMMICチップを構成するM
MIC基板で、MMIC基板311は、たとえば実装基
板312に設けられた窪みに配置され、MMIC基板3
11の底面は実装基板312の裏面に設けられた接地導
体316と接触している。
Reference numeral 311 denotes M constituting the MMIC chip.
In the MIC substrate, the MMIC substrate 311 is arranged in a recess provided in the mounting substrate 312, for example.
The bottom surface of 11 is in contact with the ground conductor 316 provided on the back surface of the mounting board 312.

【0013】MMIC311基板上には信号導体301
や接地メタル302a、302bが設けられ、接地メタ
ル302a、302bは、ボンディングワイヤ315お
よび実装基板312上のパッド313、実装基板312
に形成されたスルーホール313aなどを介して、実装
基板312裏面の接地導体316と電気的に接続されて
いる。
The signal conductor 301 is provided on the MMIC 311 substrate.
And the grounding metals 302a and 302b are provided. The grounding metals 302a and 302b are connected to the bonding wires 315, the pads 313 on the mounting substrate 312, and the mounting substrate 312.
Is electrically connected to a ground conductor 316 on the back surface of the mounting board 312 through a through hole 313a formed in the substrate.

【0014】上記した構成の場合、MMIC基板311
が、接地メタル302a、302bや接地導体316な
どの導体で囲まれた形になり、擬似的な空間が形成され
る。そのため、擬似的な空間の共振周波数においてMM
IC内の伝送線路と結合し、特性を劣化させる。
In the case of the above configuration, the MMIC board 311
Are surrounded by conductors such as the ground metals 302a and 302b and the ground conductor 316, and a pseudo space is formed. Therefore, MM at the resonance frequency of the pseudo space
It couples with the transmission line in the IC and degrades the characteristics.

【0015】図7(b)は、図7(a)の上面図で、コ
プレーナ配線を用いたMMICチップを実装基板312
に実装して共振が発生した場合に、コプレーナ線路の接
地メタル302a、302b部分に流れる電流分布を矢
印Yで示している。この電流分布は、上記した擬似的空
間を、導体に囲まれた空胴共振器とみなした場合のTE
101モードの電流分布と同じである。
FIG. 7B is a top view of FIG. 7A, in which an MMIC chip using coplanar wiring is mounted on a mounting substrate 312.
The arrow Y indicates the distribution of the current flowing through the grounded metal 302a, 302b of the coplanar line when resonance occurs when mounted on the coplanar line. This current distribution is obtained when the above pseudo space is regarded as a cavity resonator surrounded by a conductor.
This is the same as the current distribution in the 101 mode.

【0016】ミリ波帯の場合は、MMICチップの大き
さが動作周波数の波長に対して無視できなくなる。MM
IC基板にGaAsを用いた場合は、比誘電率が13程
度と高く共振周波数が低下する。そのため、擬似的空間
の共振周波数でMMIC上の伝送線路と結合が起り、M
MIC内の電気回路の動作に障害となる。
In the case of the millimeter wave band, the size of the MMIC chip cannot be ignored with respect to the wavelength of the operating frequency. MM
When GaAs is used for the IC substrate, the relative dielectric constant is as high as about 13 and the resonance frequency decreases. Therefore, coupling occurs with the transmission line on the MMIC at the resonance frequency of the pseudo space, and M
It interferes with the operation of the electric circuit in the MIC.

【0017】図7(b)は、コプレーナ線路の信号導体
301をMMIC311の中心線上に配置した場合を示
している。しかし、擬似的空間の共振周波数における伝
送線路との結合は、信号導体の位置に関係なく発生す
る。
FIG. 7B shows a case where the signal conductor 301 of the coplanar line is arranged on the center line of the MMIC 311. However, the coupling with the transmission line at the resonance frequency in the pseudo space occurs regardless of the position of the signal conductor.

【0018】本発明は、上記した欠点を解決し、不要な
共振を抑え動作が安定な半導体装置を提供することを目
的としている。
An object of the present invention is to solve the above-mentioned drawbacks and to provide a semiconductor device in which unnecessary resonance is suppressed and operation is stable.

【0019】[0019]

【課題を解決するための手段】本発明は、信号導体およ
びこの両側に位置する接地メタルで構成されるコプレー
ナ線路によって、伝送線路の少なくとも一部が形成され
ているMMICチップを有する半導体装置において、前
記接地メタルが複数に分割され、かつ、分割された前記
接地メタル間が導体および抵抗体で接続されていること
を特徴としている。
According to the present invention, there is provided a semiconductor device having an MMIC chip in which at least a part of a transmission line is formed by a coplanar line composed of a signal conductor and ground metal located on both sides of the signal conductor. The ground metal is divided into a plurality of parts, and the divided ground metals are connected by a conductor and a resistor.

【0020】[0020]

【発明の実施の形態】本発明の実施形態について図1を
参照して説明する。図の(a)は、MMICチップを実
装基板上にワイヤボンディング実装した場合の上面図、
図の(b)は、図(a)の点線で囲んだ円Rの部分を拡
大した拡大図、図(c)は、図(a)のA−Aにおける
断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. (A) of the figure is a top view when the MMIC chip is mounted by wire bonding on a mounting board,
(B) of the figure is an enlarged view enlarging a portion of a circle R surrounded by a dotted line of the (a), and (c) is a cross-sectional view along AA of the (a).

【0021】符号12は実装基板で、たとえば、実装基
板12の中央に窪み12aが設けられ、その窪み12a
の部分にMMICチップ11が配置されている。実装基
板12上には、MMICチップ11を囲んで複数のパッ
ド13が配置され、左右の両端部分に伝送線路14が設
けられている。
Reference numeral 12 denotes a mounting board, for example, a recess 12a is provided in the center of the mounting board 12, and the recess 12a
The MMIC chip 11 is arranged in the portion. A plurality of pads 13 are arranged on the mounting substrate 12 so as to surround the MMIC chip 11, and transmission lines 14 are provided at both left and right end portions.

【0022】MMICチップ11中央部分の横方向にコ
プレーナ線路を構成する信号線1aが設けられ、信号線
1aが延長するその一方の側に、信号線1aの延長方向
に分割された接地メタル2a1〜2a3が設けられ、信
号線1aの他方の側にも、信号線1aの延長方向に分割
された接地メタル2b1〜2b3が設けられている。分
割された接地メタル2a1〜2a3、2b1〜2b3の
うち、信号線1aの延長方向に隣接するどうしは、それ
ぞれ導体のブリッジ5および複数の抵抗体3で接続され
ている。なお、信号線1aを挟んで隣接する接地メタル
どうし、たとえば2a1と2b1、2a2と2b2、2
a3と2b3は、信号線1aを跨ぐブリッジ5によって
接続されている。
A signal line 1a forming a coplanar line is provided in the lateral direction of the central part of the MMIC chip 11, and one side of the extension of the signal line 1a is provided with a ground metal 2a1 divided in the extension direction of the signal line 1a. 2a3 is provided, and the other side of the signal line 1a is also provided with ground metals 2b1 to 2b3 divided in the extension direction of the signal line 1a. Among the divided ground metals 2a1-2a3, 2b1-2b3, adjacent ones in the extension direction of the signal line 1a are connected by a bridge 5 of a conductor and a plurality of resistors 3, respectively. It should be noted that ground metals adjacent to each other across the signal line 1a, for example, 2a1 and 2b1, 2a2 and 2b2, 2
a3 and 2b3 are connected by a bridge 5 that straddles the signal line 1a.

【0023】上記した構成において、それぞれの接地メ
タル2a1〜2a3、2b1〜2b3と実装基板12上
のパッド13がボンディングワイヤ15で接続される。
パッド13は、図1(c)に示すように、実装基板12
を貫通するスルーホール13aを通して実装基板12裏
面の接地導体16と電気的に接続されている。このと
き、MMICチップ11部分には、MMICチップ11
上の接地メタル2a1〜2a3、2b1〜2b3および
実装基板16裏面の接地導体16などの導体で囲まれた
擬似的空間が形成される。
In the above configuration, the grounding metals 2a1-2a3, 2b1-2b3 and the pads 13 on the mounting board 12 are connected by bonding wires 15.
The pad 13 is, as shown in FIG.
Is electrically connected to the ground conductor 16 on the back surface of the mounting board 12 through a through hole 13a penetrating through the through hole 13a. At this time, the MMIC chip 11
A pseudo space is formed surrounded by conductors such as the upper ground metals 2a1-2a3, 2b1-2b3 and the ground conductor 16 on the back surface of the mounting board 16.

【0024】なお、図(b)に示すように、信号導体1
aの同じ側で隣接する接地メタルどうし、たとえば2a
1と2a2間は、ブリッジ5の方が抵抗体3よりも信号
導体1aに近い位置で電気的に接続されている。この場
合、信号導体1aの同じ側で隣接する接地メタルどうし
が信号導体1aに近い位置で電気的に接続されるため、
コプレーナ線路自体に伝送特性の劣化が生じない。
Note that, as shown in FIG.
a between adjacent ground metals on the same side of
The bridge 5 is electrically connected between 1 and 2a2 at a position closer to the signal conductor 1a than the resistor 3 is. In this case, adjacent ground metals on the same side of the signal conductor 1a are electrically connected at a position close to the signal conductor 1a.
The transmission characteristics do not deteriorate in the coplanar line itself.

【0025】ここで、MMICチップを実装基板にワイ
ヤボンディング実装した場合の共振について、分割した
接地メタルどおしを抵抗体で接続した場合と、抵抗体な
しに直接接続した場合とで、三次元電磁界解析のシミュ
レーションを行った結果について図2を参照して説明す
る。
The resonance when the MMIC chip is mounted on the mounting substrate by wire bonding is three-dimensional when the divided ground metal is connected by a resistor and when the MMIC chip is directly connected without a resistor. The result of the simulation of the electromagnetic field analysis will be described with reference to FIG.

【0026】シミュレーションは、 MMICチップの大きさ:1.2mm×1.5mm×
0.2mm、 MMICチップの基板の誘電率:12.9 MMICチップの伝送線路を中央付近で開放という条件
で行った。
In the simulation, the size of the MMIC chip: 1.2 mm × 1.5 mm ×
0.2 mm, dielectric constant of the substrate of the MMIC chip: 12.9 This was performed under the condition that the transmission line of the MMIC chip was opened near the center.

【0027】抵抗体ありの場合は、隣接する接地メタル
間どうしを抵抗体によって3個所で接続し、抵抗体なし
の場合は、抵抗体の抵抗値を0として比較した。
When there is a resistor, adjacent ground metals are connected to each other at three locations by a resistor, and when there is no resistor, the resistance value of the resistor is set to 0 for comparison.

【0028】図2は、縦軸が挿入損失(S21)(d
B)、横軸が周波数(GHz)で、特性Pが抵抗なしの
場合で、特性Qが抵抗(抵抗値20Ω)ありの場合であ
る。図から分かるように、抵抗なしの場合(P)は、共
振周波数(36.2GHz)でアイソレーションが劣化
している。抵抗ありの場合(Q)は、共振周波数におけ
るアイソレーションの極大値が減少している。
In FIG. 2, the vertical axis indicates the insertion loss (S21) (d
B), the horizontal axis represents frequency (GHz), the characteristic P has no resistance, and the characteristic Q has resistance (resistance of 20Ω). As can be seen from the figure, in the case without the resistor (P), the isolation is deteriorated at the resonance frequency (36.2 GHz). In the case with the resistance (Q), the maximum value of the isolation at the resonance frequency is reduced.

【0029】したがって、分割した接地メタル間を抵抗
体で接続すれば、共振時に接地メタルに流れる電流を抵
抗体で減衰できる。そのため、MMICにコプレーナ線
路を用いても、不要な共振による特性の劣化が防止され
る。また、分割した接地メタルどうしをつなぐブリッジ
を信号導体に近接させているため、接地メタル間が抵抗
体で接続されても伝送特性の劣化は防止される。
Therefore, if the divided ground metals are connected by a resistor, the current flowing through the ground metal during resonance can be attenuated by the resistor. Therefore, even if a coplanar line is used for the MMIC, deterioration of characteristics due to unnecessary resonance is prevented. Further, since the bridge connecting the divided ground metals is close to the signal conductor, even if the ground metals are connected by a resistor, deterioration of transmission characteristics is prevented.

【0030】本発明の他の実施形態について図3を参照
して説明する。図3では、図1に対応する部分には同一
の符号を付し、重複する説明は一部省略する。
Another embodiment of the present invention will be described with reference to FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be partially omitted.

【0031】この実施形態は、コプレーナ線路の信号導
体を一部で分岐し、分岐信号導体を設けた場合で、図3
(a)は、その分岐部分を拡大して示した上面図、図3
(b)は、図(a)のB−Bにおける断面図である。
In this embodiment, the signal conductor of the coplanar line is partially branched to provide a branched signal conductor.
FIG. 3A is an enlarged top view of the branch portion, and FIG.
FIG. 2B is a cross-sectional view taken along line BB in FIG.

【0032】コプレーナ線路を構成する信号線路1aの
一部に、信号線路1aから分岐する分岐信号線1bが設
けられている。信号線路1aの一方の側に接地メタル2
aが設けられ、分岐信号線1bは、たとえば信号線路1
aの他方の側に位置し分割された接地メタル2b1と2
b2間に伸びている。分割された接地メタル2b1と2
b2間は信号線路1aに近い位置がブリッジ5で接続さ
れ、ブリッジ5よりも離れた位置に抵抗体3が接続され
ている。この場合、図(b)に示すように、分岐信号線
1bと抵抗体3が交差する部分は、分岐信号線1bの一
部が抵抗体3の上方を跨ぐブリッジ状線路4に形成され
ている。
A part of the signal line 1a constituting the coplanar line is provided with a branch signal line 1b branched from the signal line 1a. Grounding metal 2 on one side of signal line 1a
a, and the branch signal line 1 b
a and divided ground metals 2b1 and 2b located on the other side of
It extends between b2. Divided ground metal 2b1 and 2
Between b2, a position near the signal line 1a is connected by a bridge 5, and a resistor 3 is connected to a position farther from the bridge 5. In this case, as shown in FIG. 2B, a portion where the branch signal line 1b intersects with the resistor 3 is formed in a bridge-like line 4 in which a part of the branch signal line 1b crosses over the resistor 3. .

【0033】なお、コプレーナ線路を構成する接地メタ
ル間を抵抗体で接続する場合、隣接する接地メタル間の
中央と抵抗体の中心とが一致するすれば、左右対称の構
造となる。このとき、抵抗体に電流が流れないため、抵
抗体を接続したことによる伝送損失は生じない。
When connecting the ground metals forming the coplanar line with a resistor, if the center between the adjacent ground metals coincides with the center of the resistor, a symmetrical structure is obtained. At this time, since no current flows through the resistor, no transmission loss occurs due to the connection of the resistor.

【0034】上記した構成によれば、不要な共振を防止
するための抵抗体を含むT分岐部を設けても、T分岐自
体に伝送損失を生じないように構成できる。
According to the above configuration, even if a T-branch including a resistor for preventing unnecessary resonance is provided, a transmission loss can be prevented from occurring in the T-branch itself.

【0035】本発明の他の実施形態について図4を参照
して説明する。図の(a)はMMICチップ上に形成さ
れる回路構成、図(b)は図(a)の回路構成をMMI
Cにレイアウトした際の信号導体や接地メタル、抵抗体
などの配置図、図(c)は、図(b)の一部を拡大した
拡大図である。
Another embodiment of the present invention will be described with reference to FIG. FIG. 3A shows a circuit configuration formed on an MMIC chip, and FIG. 3B shows a circuit configuration of FIG.
The layout of the signal conductors, the ground metal, the resistors, and the like when laid out on C is shown. FIG. 3C is an enlarged view of a part of FIG.

【0036】図(a)において、INが入力端子、OU
Tが出力端子で、入力端子INと出力端子OUT間に、
入力端子INの側から順に、整合回路41、FET4
2、整合回路43、整合回路44、FET45、整合回
路46が接続されている。
In FIG. 3A, IN is an input terminal, OU
T is an output terminal, between the input terminal IN and the output terminal OUT,
In order from the input terminal IN side, the matching circuit 41 and the FET 4
2. The matching circuit 43, the matching circuit 44, the FET 45, and the matching circuit 46 are connected.

【0037】2つのFET42、45にはそれぞれ、ス
タブLやキャパシタCなどで構成されたバイアス回路が
2個づつ設けられている。
Each of the two FETs 42 and 45 is provided with two bias circuits each including a stub L and a capacitor C.

【0038】図(b)は、図(a)の回路構成の一部、
たとえば、コプレーナ線路を構成する信号導体101、
および、信号導体101の一方の側に分割して配置され
た接地メタル104a1、104a2、104a3、信
号導体101の他方の側に分割して配置された接地メタ
ル104b1、104b2、104b3、隣接する接地
メタル間を接続する抵抗体105、隣接する接地メタル
間を接続する抵抗を装荷しないブリッジ106、信号導
体101から分岐し、抵抗105と交差する部分がブリ
ッジ状に形成されたスタブLなどの配置を示している。
FIG. 4B shows a part of the circuit configuration of FIG.
For example, the signal conductor 101 constituting a coplanar line,
In addition, the ground metals 104a1, 104a2, and 104a3 that are separately arranged on one side of the signal conductor 101, the ground metals 104b1, 104b2, and 104b3 that are separately arranged on the other side of the signal conductor 101, and the adjacent ground metal FIG. 2 shows an arrangement of a resistor 105 connecting between the two, a bridge 106 not loaded with a resistor connecting between adjacent ground metals, and a stub L branched from the signal conductor 101 and crossing the resistor 105 in a bridge shape. ing.

【0039】上記したMMICチップは全体が矩形状に
形成され、一方、たとえば図の左右方向の長さlが、図
の上下方向の長さsよりも長くなっている。なお、矩形
状の点線Sで囲った部分はスタブL部分のレイアウトを
示している。
The MMIC chip described above is formed in a rectangular shape as a whole, while, for example, the length 1 in the left-right direction in the figure is longer than the length s in the vertical direction in the figure. The portion surrounded by the rectangular dotted line S indicates the layout of the stub L portion.

【0040】図4(c)は、図4(b)における円Rで
囲まれた信号導体の分岐部分を拡大した図で、バイアス
回路を構成するスタブLの少なくとも一部がMMICチ
ップの短辺sに平行にレイアウトされている。
FIG. 4 (c) is an enlarged view of a branch portion of the signal conductor surrounded by a circle R in FIG. 4 (b), and at least a part of a stub L constituting a bias circuit has a short side of an MMIC chip. It is laid out in parallel with s.

【0041】上記のスタブLをコプレーナ線路で構成す
る場合、接地メタル間を接続するブリッジの一部、たと
えばその中央に抵抗体を装荷すれば、不要な共振を減衰
させる抵抗体をコプレーナ線路内に設けることができ
る。
When the stub L is formed of a coplanar line, a resistor for attenuating unnecessary resonance can be provided in the coplanar line by mounting a resistor at a part of a bridge connecting ground metals, for example, at the center thereof. Can be provided.

【0042】上記の実施形態では、接地メタル間を抵抗
体で接続しているが、この場合、接地メタル間を、一部
が抵抗体で一部が導体で形成された抵抗片を用いて接続
することもできる。
In the above embodiment, the ground metal is connected by a resistor. In this case, the ground metal is connected by using a resistor piece partially formed of a resistor and partially formed of a conductor. You can also.

【0043】また、上記の実施形態では、接地メタルを
分割する場合、接地メタルを信号導体の延長方向で分割
している。しかし、接地メタルを分割する場所や方向は
任意に設定することができる。また、上記の実施形態で
は、MMICチップをワイヤボンディング実装した場合
で説明しているが、この発明は、MMICチップをバン
プ実装した場合にも適用できる。
In the above embodiment, when the ground metal is divided, the ground metal is divided in the extending direction of the signal conductor. However, the location and direction of dividing the ground metal can be set arbitrarily. In the above embodiment, the case where the MMIC chip is mounted by wire bonding is described. However, the present invention can be applied to the case where the MMIC chip is mounted by bump.

【0044】[0044]

【発明の効果】本発明によれば、不要な共振を抑え、動
作が安定な半導体装置を実現できる。
According to the present invention, a semiconductor device which suppresses unnecessary resonance and operates stably can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態を説明するための概略の構造
図である。
FIG. 1 is a schematic structural diagram for explaining an embodiment of the present invention.

【図2】本発明の特性を説明するための特性図である。FIG. 2 is a characteristic diagram for explaining characteristics of the present invention.

【図3】本発明の他の実施形態を説明するための概略の
構造図である。
FIG. 3 is a schematic structural diagram for explaining another embodiment of the present invention.

【図4】本発明の他の実施形態を説明するための概略の
構造図である。
FIG. 4 is a schematic structural diagram for explaining another embodiment of the present invention.

【図5】従来例を説明するための概略の斜視図である。FIG. 5 is a schematic perspective view for explaining a conventional example.

【図6】従来例を説明するための回路構成図である。FIG. 6 is a circuit configuration diagram for explaining a conventional example.

【図7】従来例を説明するための概略の構造図である。FIG. 7 is a schematic structural diagram for explaining a conventional example.

【図8】従来例を説明するための概略の構造図である。FIG. 8 is a schematic structural diagram for explaining a conventional example.

【符号の説明】[Explanation of symbols]

3…抵抗体 5…ブリッジ 11…MMICチップ 12…実装基板 13…パッド 13a…スルーホール 14…伝送線路 15…ボンディングワイヤ 16…実装基板裏面の接地導体 1a…コプレーナ線路の信号導体 2a1〜2a3、2b1〜2b3…コプレーナ線路の接
地メタル
DESCRIPTION OF SYMBOLS 3 ... Resistor 5 ... Bridge 11 ... MMIC chip 12 ... Mounting board 13 ... Pad 13a ... Through hole 14 ... Transmission line 15 ... Bonding wire 16 ... Ground conductor on the back surface of mounting board 1a ... Signal conductor of coplanar line 2a1-2a3, 2b1 ~ 2b3 ... Coplanar line ground metal

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 信号導体およびこの両側に位置する接地
メタルで構成されるコプレーナ線路によって、伝送線路
の少なくとも一部が形成されているMMICチップを有
する半導体装置において、前記接地メタルが複数に分割
され、かつ、分割された前記接地メタル間が導体および
抵抗体で接続されていることを特徴とする半導体装置。
In a semiconductor device having an MMIC chip having at least a part of a transmission line formed by a coplanar line formed of a signal conductor and ground metal located on both sides of the signal conductor, the ground metal is divided into a plurality of parts. And the divided ground metal is connected by a conductor and a resistor.
【請求項2】 信号導体およびこの両側に位置する接地
メタルで構成されるコプレーナ線路によって、伝送線路
の少なくとも一部が形成されているMMICチップと、
一方の側に接地メタルが形成され他方の側に前記MMI
Cチップが実装される実装基板とを具備した半導体装置
において、前記接地メタルが複数に分割され、かつ、分
割された前記接地メタル間が導体および抵抗体で接続さ
れていることを特徴とする半導体装置。
2. An MMIC chip in which at least a part of a transmission line is formed by a coplanar line composed of a signal conductor and ground metal located on both sides of the signal conductor,
A ground metal is formed on one side, and the MMI is formed on the other side.
A semiconductor device comprising: a mounting substrate on which a C chip is mounted; wherein the ground metal is divided into a plurality of parts, and the divided ground metals are connected by a conductor and a resistor. apparatus.
【請求項3】 信号導体から分岐して分割された接地メ
タル間を通る分岐導体が設けられ、その分割された接地
メタル間で、導体の方が抵抗体よりも信号導体に近い位
置で接続されている請求項1または請求項2記載の半導
体装置。
3. A branch conductor which branches from a signal conductor and passes between divided ground metals is provided, and between the divided ground metals, the conductor is connected at a position closer to the signal conductor than the resistor. 3. The semiconductor device according to claim 1, wherein
【請求項4】 信号導体から分岐して分割された接地メ
タル間を通る分岐導体が設けられ、かつ、分割された前
記接地メタル間を接続する抵抗体と前記分岐導体とが交
差する部分では、前記分岐導体が前記抵抗体の上方を跨
いでいる請求項1または請求項2記載の半導体装置。
4. A portion provided with a branch conductor that branches from a signal conductor and passes between divided ground metals, and at a portion where the resistor that connects the divided ground metals intersects the branch conductor, 3. The semiconductor device according to claim 1, wherein the branch conductor straddles over the resistor.
【請求項5】 実装基板に貫通孔が設けられ、コプレー
ナ線路の接地メタルと実装基板の接地導体とが、前記貫
通孔部分に形成された導電層を介して電気的に接続され
ている請求項2記載の半導体装置。
5. A through hole is provided in the mounting board, and a ground metal of the coplanar line and a ground conductor of the mounting board are electrically connected to each other via a conductive layer formed in the through hole portion. 3. The semiconductor device according to 2.
【請求項6】 コプレーナ線路の接地メタルと実装基板
の接地導体とがバンプによって電気的に接続されている
請求項2記載の半導体装置。
6. The semiconductor device according to claim 2, wherein the ground metal of the coplanar line and the ground conductor of the mounting board are electrically connected by bumps.
JP26191799A 1999-09-16 1999-09-16 Semiconductor device Expired - Fee Related JP3913937B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26191799A JP3913937B2 (en) 1999-09-16 1999-09-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26191799A JP3913937B2 (en) 1999-09-16 1999-09-16 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2001085570A true JP2001085570A (en) 2001-03-30
JP3913937B2 JP3913937B2 (en) 2007-05-09

Family

ID=17368539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26191799A Expired - Fee Related JP3913937B2 (en) 1999-09-16 1999-09-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3913937B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003257988A (en) * 2002-03-05 2003-09-12 Sharp Corp Transistor circuit and communication equipment
JP2010003859A (en) * 2008-06-20 2010-01-07 New Japan Radio Co Ltd Integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003257988A (en) * 2002-03-05 2003-09-12 Sharp Corp Transistor circuit and communication equipment
JP2010003859A (en) * 2008-06-20 2010-01-07 New Japan Radio Co Ltd Integrated circuit

Also Published As

Publication number Publication date
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