JPH06302619A - Fabrication of field-effect transistor - Google Patents

Abstract

PURPOSE:To stabilize a device by more shortening a gate length and sharply improving drain breakdown strength. CONSTITUTION:An active layer 2 is formed on a semi-insulating GaAs substrate 1 and thereafter an SiO2 pattern 8 is formed in a gate formation region in the direction of gate width. A Schottky gate metal 4' is deposited on the entire surface and a metal sidewall 4'' is left behind on opposite sides of the pattern 8 in the direction of gate width using anisotropic dry etching. A high concentration layer 6 is formed in a source-drain region with high dose ion implantation taking the pattern 8 and a metal sidewall 4'' as a mask. Unnecessary portions; the metal sidewall 4'' and the pattern 8 are removed and a remaining sidewall is taken as a gate electrode 4. Light dose ions are implanted in the gate-drain region with the gate electrode 4 used as a mask to form an n' GaAs active layer 7 for LDD in a drain region adjoining the gate. There are further formed a source electrode 3, a drain electrode 5, and a gate extraction electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor, and more particularly to a Schottky junction field effect transistor (hereinafter referred to as ME) which is a main device of a compound semiconductor.
The present invention relates to a manufacturing method suitable for SFET).

[0002]

2. Description of the Related Art In general, in order to improve the performance of MESFETs, it is necessary to shorten the gate length, make the active layer shallow, reduce the gate and source resistances, and improve the threshold voltage fluctuations due to the two-dimensional effect. . Also, various manufacturing methods for realizing the structure have been proposed. A typical example thereof is a structure as shown in FIG.

The structure shown in FIG. 3 (a) is a basic form of MESFET, though there is a modified example of a recess structure for reducing the source resistance and improving the drain breakdown voltage. As shown in the figure, the source electrode 3, the gate electrode 4, and the drain 5 electrode are arranged side by side. In this manufacturing method, after the source electrode 3 and the drain electrode 5 are formed, alignment is performed by photolithography to form the gate electrode 4. Note that there is also the reverse method. In any case, the distance between the source electrode 3 and the drain electrode 5, that is, the gate length is determined by the alignment accuracy and processing accuracy of the photolithography, and considering the device yield and the like,
That distance needs to be increased. Along with this, element performances such as mutual conductance gm and noise characteristics deteriorate. Moreover, since the self-alignment method is not introduced in the process steps, the process procedure becomes complicated.

On the other hand, the one shown in FIG. 3 (b) introduces the self-alignment method in which the gate electrode is preceded, and is used for digital applications. In this manufacturing method, after forming an active layer to be a channel, WSi is deposited as a gate metal, and after the deposition, a photolithography process is used to form a gate electrode 4
Is formed, a high-concentration ion implantation layer 6 for source / drain is formed using the gate electrode 4 as a mask, and annealing is performed. After that, source and drain ohmic electrodes 3, 5
Is formed. The manufacturing method adopts the self-alignment method to simplify the process procedure. However, the processing of the gate electrode 4 is determined by the resolution of the photolithography, and there is a limit to the shortening of the gate length and variations in processing level. At present, it is about 0.5 μm ± 0.1 μm. With this value, the threshold voltage Vth greatly fluctuates, making it difficult to achieve large scale integration. Further, characteristically, since the distance between the gate electrode 4 and the drain electrode 5 is short, the drain breakdown voltage becomes small and it is difficult to apply to an analog element. In particular, the dependence of the threshold voltage Vth on the gate length becomes large,
There is a drawback in that the capacitance between the drains is large.

An LDD (lightly Doped Drain) shown in FIG. 3 (c) is provided as a structure for eliminating the drawbacks of these characteristics.
) There is a structure. In this manufacturing method, the LDD n'active layer 7 is formed between the gate electrode 4 and the drain electrode 5 by ion implantation under the condition that the concentration is higher than that of the high concentration layer 6 for the ohmic electrode and higher than the concentration of the active layer. Is. This structure is ideal because it has a large drain breakdown voltage and a small gate-drain capacitance. However, in order to form the LDD n ′ active layer 7, it becomes difficult to apply the self-alignment method, and as a result, it is necessary to complicate the manufacturing process and to enhance the alignment accuracy of photolithography.

[0006]

As described above, each of the conventional manufacturing methods has advantages and disadvantages. The summary is as follows.

(1) Although it is common to FIGS. 3A to 3C, the size of the gate length is determined by photolithography, and the shortening limit of the gate length depends on photolithography. Therefore, the element becomes unstable in consideration of variations in gate processing.

(2) FIG. 3B shows deterioration of drain breakdown voltage.
The structure is easily affected by the two-dimensional effect, and deterioration of the device characteristics is likely to occur.

(3) FIG. 3 (c) shows an ideal structure, but it is legally required to enhance the alignment accuracy in photolithography. If the alignment accuracy is loosened, the chip area increases and the device performance deteriorates.

(4) Since FIGS. 3A and 3C are not manufactured by the self-alignment method, the manufacturing process becomes complicated.

The object of the present invention is to improve the process procedure, thereby eliminating the drawbacks of the prior art described above, further shortening the gate length, and greatly improving the drain breakdown voltage to stabilize the device. It is an object of the present invention to provide a method of manufacturing a field effect transistor that can be manufactured.

[0012]

A method of manufacturing a field effect transistor according to the present invention includes a step of forming a Schottky gate on an active layer formed on a substrate, and at the time of forming the Schottky gate, forming the gate on the active layer. In the region, an insulating film pattern that has a side surface in the gate width direction and forms a step with the active layer is formed, a metal that will be a Schottky gate is deposited on the entire surface including the insulating film pattern, and this metal is dry-etched. By doing so, a side wall of metal is formed on the side surface in the gate width direction of the insulating film pattern, and then the unnecessary metal side wall is removed and the remaining metal side wall is used as the gate electrode. .

The method of manufacturing a field effect transistor of the present invention is the method of manufacturing a Schottky junction type field effect transistor using a compound semiconductor, wherein an active layer is formed on a compound semiconductor substrate by ion implantation and then the active layer is formed. A step of forming an insulating film pattern having a side surface in the gate width direction and forming a step with the active layer in the gate forming region on the layer, and using this insulating film pattern as a mask, a high-level electrode for forming an ohmic electrode is formed in the drain region. A step of forming a high-concentration layer by dose ion implantation, a step of depositing a metal to be a Schottky gate on the entire surface, and a metal side wall on the side surface of the insulating film pattern in the gate width direction by etching the metal. The formation process and high dose ion implantation for ohmic electrode formation are performed on the source region using the insulating film pattern and the metal sidewall as a mask. A step of forming a high-concentration layer, a step of removing an unnecessary portion of the metal side wall and the side wall portion left by removing the insulating film pattern as a gate electrode, and using the gate electrode as a mask, the metal side wall and the insulation A step of forming a lightly-doped layer for draining with a light dose amount of ions in the drain region adjacent to the gate from which the film pattern has been removed, and a source / drain electrode / gate extraction by depositing a metal for source / drain electrodes And a step of forming an electrode.

The method of manufacturing a field effect transistor of the present invention is the method of manufacturing a field effect transistor of LDD structure described above, in which a lightly doped layer is formed in order to apply this to a field effect transistor of a general structure. By omitting the step, a high-concentration layer for high-dose ion implantation for forming an ohmic electrode is simultaneously formed in the source region and the drain region.

The compound semiconductor in the present invention is GaA.
Other than s series, InP series or AlGaAs series, InG
It can also be applied to aAs system.

[0016]

The gate electrode is formed as a thick metal side wall on the side surface in the gate width direction of the insulating film pattern that forms a step with the active layer. The thickness of the side wall of the gate metal becomes the gate length. Therefore, the insulating film pattern merely provides a reference for determining the starting end of the gate length, and the accuracy of the insulating film pattern does not affect the gate length dimension. The gate length is determined by the thickness of the gate metal deposited on the entire surface of the wafer and the variation of the dry etching performed to form the metal sidewall, and the accuracy is greatly improved because it does not depend on photolithography. Moreover, since the variation factor of dry etching is smaller than the metal deposition thickness,
Depending on the metal deposition thickness, the gate length can be 0.1 μm or less.

On the other hand, the region other than the portion to be the gate electrode is removed by etching using a photoresist by photolithography as a mask which does not require alignment accuracy. Further, the ion implantation of the source / drain ohmic high concentration layer and the ion implantation of the light concentration layer for the LDD structure are performed by a self-alignment method using the gate electrode as a mask.

As described above, the present invention provides a self-alignment method capable of forming a gate electrode and a source / drain electrode without using a highly accurate photolithography technique, and an LDD structure ME.
Since the SFET self-alignment method is used, the gate length is shortened, the drain breakdown voltage is improved, and it is possible to greatly improve the device characteristics and stably manufacture the device.

[0019]

The first and second embodiments in which the method for manufacturing a field effect transistor of the present invention is applied to a GaAs MESFET will be described below.

[Embodiment 1] FIG. 1 shows a manufacturing process of a first embodiment. First, as shown in FIG. 1A, semi-insulating Ga
NGa that becomes a channel layer on the As substrate 1 by the ion implantation method
The As active layer 2 was formed. Ion implantation condition is 50 ke
V, 2 × 10 ¹² cm ⁻² Si ions, annealing as
This is a method using H ₃ . Then, a SiO ₂ film 8 ′ is deposited by a thermal decomposition method using SiH ₄ gas at a thickness of 4000 Å, and a photolithography process is used to form a gate formation region at a width (length in the left-right direction on the paper surface) of 2.5.
μm, length (length in the direction perpendicular to the paper) 20 μm Si
The O ₂ pattern 8 was formed in the gate width direction (direction perpendicular to the paper surface). The left step of the SiO ₂ pattern 8 defines one end of the gate length.

After forming the SiO ₂ pattern 8, FIG.
As shown in (b), the photoresist film 9 is left on the source side with the SiO ₂ pattern 8 as a boundary, and the n ⁺ GaAs source.
Ion implantation of the high concentration layer 6 for drain was performed on the drain side. n ⁺ ion implantation is Si ion 75 keV, 1 × 1
The dose was 0 ¹³ cm ^-2 .

Next, as shown in FIG. 1 (c), WSi4 'to be a gate metal is deposited by sputtering to a thickness of 4000 angstroms, and then dry etching is performed using NF ₃ gas on both sides of the SiO ₂ pattern 8. The side wall 4 ″ of the thin gate metal was left. Dry etching at this time was performed in an anisotropic etching state by a plasma method. The anisotropic etching can be adjusted by the gas pressure and the strength of the vertical electric field.

After forming the side wall, as shown in FIG. 1D, a photoresist film 9'is applied to the drain side and the source film is applied to the source side.
Ions are implanted into the high-concentration n ⁺ GaAs layer 6 for drain. The ion implantation conditions are the same as the ion implantation conditions performed in FIG.

After the high-concentration layer is formed, a portion used as the gate electrode 4 from the gate metal sidewalls 4 "formed on both sides of the SiO ₂ pattern 8 and a gate extraction electrode subsequent thereto (not shown because it is in the direction perpendicular to the paper surface). 1E, a photoresist film 9 ″ is formed on the contour thereof by a photolithography process to leave a portion used as a mask) and dry etching is performed using this as a mask to remove the gate metal sidewall 4 ″ of an unnecessary portion. Removed.

After removal, as shown in FIG.
₂ pattern 8 is removed, n'ion implantation for LDD structure is performed on the entire surface using the gate electrode 4 as a mask, and n'Ga is applied to the drain adjacent to the gate where the SiO ₂ pattern 8 is removed.
The active layer 7 for AsLDD was formed. n'ion condition is S
The acceleration voltage is 50 keV for i ions, and the dose amount is 5 × 10 ¹² cm ⁻² . Then, the ion implantation layer was annealed at 800 ° C. using AsH ₃ gas.

Thereafter, as shown in FIG. 1 (g), n
⁺ Source electrode 3 and drain electrode 4 on the source region and drain region of the GaAs high concentration layer 6 for source / drain
Was formed. The formation method is as follows. A SiO ₂ film 8 ″ is deposited by a thermal decomposition method using SiH ₄ gas to a thickness of 3200 Å, and the source electrode 3 is formed by a photolithography process.
A pattern of a gate extraction electrode (not shown) connected to the drain electrode 5 and the gate electrode 4 is formed. And A
It was performed by depositing a uGeNi-based ohmic metal and forming a source / drain metal pattern by a lift-off method. After that, an alloying step was performed in order to completely obtain the ohmic property.

Since the gate extraction electrode is formed at the same time as the gate electrode 4, AuG is further formed thereon.
It has a structure in which eNi-based source / drain electrode metals are stacked. When the source / drain electrode metal is overlaid on the gate extraction electrode in this way, the same conditions as the source electrode and the drain electrode are obtained. Therefore, the wiring between the electrodes performed in the next wiring step can be performed easily and surely. You can

According to the above embodiment, the gate length of the WSi gate electrode 4 obtained in FIG. 1 (c) or (e) is 0.
It was 3 μm. It can be seen that the size is greatly reduced as compared with the conventional 0.5 μm. A gate length of 0.1 μm could also be realized by setting the metal thickness to 2600 angstroms. Moreover, even if the metal thickness of 5000 angstrom is left, it is 0.1 μm by etching over.
We were able to achieve the gate length.

[0029] In the above embodiment the ion implantation process of the drain-side n ⁺ layer 6, is to perform prior to the ion implantation process of the source-side n ⁺ layer 6. This is the gate
This is to improve the breakdown voltage between the drains and reduce the capacitance and the like. It should be noted that the drain side may be injected at the same time as the source side injection unless significant improvements in characteristics such as breakdown voltage and capacitance are taken into consideration. Note that the drain side injection may be performed simultaneously with the source side injection. That is, the ion implantation step of the source side n ⁺ layer 6 (FIG. 1D)
1), the step of removing an unnecessary portion of WSi ′ in FIG.
Ion implantation of the ⁺ layer 6 is performed simultaneously.

[Embodiment 2] Although the LDD structure has been described in Embodiment 1, the method of the present invention can be applied to an MESFET having a general structure. FIG. 2 shows the manufacturing process of the second embodiment.

As shown in FIG. 2A, semi-insulating Ga
After forming the active layer 2 on the As substrate 1, a SiO ₂ film is formed on the
After depositing SiO ₂ pattern 8 to 0 Å, gate metal WSi was deposited to 5000 Å, and sidewalls 4 ″ of WSi gate metal were formed on both sides of SiO ₂ pattern 8 by dry etching.

Next, as shown in FIG. 2B, the WSi gate metal 4 ″ other than the gate electrode 4 and the gate extraction electrode is removed by the same method as in Example 1, and the gate electrode 4 is used as a mask.
N ⁺ GaAs ions were implanted to form high-concentration n ⁺ GaAs layers 6 for source and drain in the source region and the drain region. Of course, the source of this n ⁺ GaAs layer 6
A photolithography process was used to form the drain region. After n ⁺ ion implantation, annealing for activation of the n ⁺ ion implanted layer was performed.

Then, as shown in FIG. 2C, the source electrode 3 and the drain 5 electrode were formed. Like this MESFE
When T is a general structure, the process procedure can be greatly simplified, and the number of steps is about half that of the LDD structure.

In the above embodiment, GaAs MESF is used.
Since electrons have higher mobility than holes in ET, the n-channel MESFET has been described in the embodiment, but the method of the present invention can be applied to the p-channel MESFET. Further, it goes without saying that the invention can be applied to both the enhancement type (E type) and the depletion type (D type) which are essential in a digital integrated circuit. Then, by introducing a wiring process into the above process, an integrated circuit having a higher degree of integration can be manufactured.

[0035]

As described above, the present embodiment has the following effects.

(1) In the method of manufacturing a field effect transistor according to the first aspect, the deposited gate metal is dry-etched to form a metal side wall on the side surface of the insulating film pattern, and the metal side wall is formed. Therefore, the gate length can be shortened by ordinary photolithography without using special fine processing. Moreover, the accuracy is determined by the deposited metal film thickness that is easy to control and the dry etching that removes the film thickness, so that the accuracy can be improved.

(2) According to the method of manufacturing a field effect transistor according to the second aspect, in addition to the above effects, a self-alignment method is used for forming the source / drain regions and forming the LDD active layer, which are the main steps. Since it is used, the high alignment accuracy of photolithography is not required, and the process procedure is simplified. In addition, the performance of the MESFET is significantly improved by greatly reducing the gate length, and the gate / collector breakdown voltage can be increased by adopting the LDD structure, and the element can be stabilized. Considering the manufacturing of integrated circuits, high-frequency circuits, and single elements, this leads to an improvement in manufacturing yield and can greatly contribute to productivity improvement.

(3) According to the method of manufacturing a field effect transistor of claim 3, MESFE having a general structure.
Since it is applied to T, the process procedure can be significantly shortened as compared with the MESFET having the LDD structure.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a GaAs MESFET having an LDD structure according to a first embodiment of a field effect transistor of the present invention.

FIG. 2 is a manufacturing process diagram of a GaAs MESFET having a general structure according to a second embodiment of the field effect transistor of the present invention.

FIG. 3 is a cross-sectional structure diagram of various conventional GaAs MESFETs.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 nGaAs active layer 3 source electrode 4 gate electrode 4 ′ WSi 4 ″ gate metal sidewall 5 drain electrode 6 high concentration n ⁺ GaAs layer for source / drain 7 nGaAs active layer for LDD 8 SiO ₂ pattern 8 ′ SiO ₂ film 8 ″ SiO ₂ film 9 photoresist film 9 ′ photoresist film 9 ″ photoresist film

Claims (3)

[Claims] 1. A step of forming a Schottky gate on an active layer formed on a substrate, wherein a gate forming region on the active layer has a side surface in a gate width direction when forming the Schottky gate. An insulating film pattern that forms a step between the insulating film pattern is formed, a metal that will be a Schottky gate is deposited on the entire surface including the insulating film pattern, and the metal is dry-etched in the gate width direction of the insulating film pattern. A method for manufacturing a field effect transistor, comprising forming a metal side wall on a side surface, and then removing an unnecessary metal side wall to use the remaining metal side wall as a gate electrode. 2. A method of manufacturing a Schottky junction field effect transistor using a compound semiconductor, wherein an active layer is formed on a compound semiconductor substrate by ion implantation, and then a gate forming region on the active layer is formed in a gate width direction. A step of forming an insulating film pattern having a side surface and forming a step between the active layer and the active layer, and using the insulating film pattern as a mask, forming a high-concentration layer for high-dose ion implantation for ohmic electrode formation in the drain region A step of depositing a metal to be a Schottky gate on the entire surface, a step of etching the metal to form a side wall of metal on the side surface in the gate width direction of the insulating film pattern, the insulating film pattern and the metal A step of forming a high-concentration layer by high-dose ion implantation for forming an ohmic electrode in the source region using the sidewall as a mask, and then forming an unnecessary portion A step of removing the metal side wall and the side wall portion remaining after removing the insulating film pattern as a gate electrode; and using the gate electrode as a mask, draining a drain region adjacent to the metal side wall and the gate from which the insulating film pattern is removed. And a step of forming a lightly concentrated layer by light dose ion implantation for forming a source electrode, a drain electrode and a gate extraction electrode by depositing a metal for a source / drain electrode. Method for manufacturing field effect transistor. 3. A method of manufacturing a Schottky junction field effect transistor using a compound semiconductor, wherein an active layer is formed on a compound semiconductor substrate by ion implantation, and then a gate width direction is formed in a gate formation region on the active layer. Forming an insulating film pattern having a side surface and forming a step with the active layer, depositing a metal serving as a Schottky gate on the entire surface including the insulating film pattern, and etching the metal A step of forming a metal side wall on the side surface of the insulating film pattern in the gate width direction, and a high-concentration layer for source / drain ion implantation into the source / drain region using the insulating film pattern and the metal side wall as a mask. And a step of removing the side wall of the metal, which is an unnecessary portion, and the side wall remaining after removing the insulating film pattern as a gate electrode. The source electrode and depositing a metal for the source and drain electrodes, a method of manufacturing a field effect transistor, characterized in that a step of forming a drain electrode and a gate lead-out electrode.