JPH0629279A - Electronic circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To stabilize the manufacture of an anode aluminum oxide transistor by grading hierarchically wirings led to a gate electrode wiring according to their width and optimizing the wirings when manufacturing the anode aluminum oxide transistor. CONSTITUTION:When manufacturing an anode aluminum oxide gate transistor, there are installed a trunk wiring 13, which is the widest in size, and a branch wiring 5, which is narrower than the trunk wiring 13 and a gate electrode wiring 6, which is laid out at the end, thereby forming a circuit layout as described above. This wiring layout dramatically inhibits the difference in the development of anode oxidation produced between the gate electrode wirings 6 at the end. The adhesive properties of an anode oxide film of each of the gate electrode wirings 6 show a virtually constant value. This construction makes it possible to use a dry etching process and process the film to a fine degree and enhance yield as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix such as a semiconductor integrated circuit or a liquid crystal display device, or other electronic circuit, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Mainly since 1980's, a material mainly for silicon has been used as a material for a gate of a MOS type semiconductor integrated circuit. This is in addition to the physical characteristic that the energy difference between the gate electrode and the semiconductor channel is small,
This is because the source / drain can be formed in a self-aligned manner due to the heat resistance. On the contrary, the aluminum gate, which has been the mainstream until then, is not suitable for the self-alignment process due to its lack of heat resistance, and is gradually not used despite its low wiring resistance.

Recently, however, it has been clarified that a self-alignment process can be adopted even for an aluminum gate by using a laser annealing technique or the like, and the gate electrode or a wiring connected thereto (these are mutually connected). Since it cannot be clearly distinguished, an aluminum oxide film having excellent corrosion resistance and pressure resistance is formed on the surface of the gate electrode wiring (hereinafter collectively referred to as "gate electrode wiring") by an anodic oxidation method. It was shown that the separation can be reliably performed and that the offset region can be formed in the gate and the source / drain by using aluminum oxide (Japanese Patent Application No. 3-34033).
6, ibid. 4-30220, ibid. 4-34194).

[0004]

[Problems to be Solved by the Invention] However, there are some problems. For example, even if anodization is performed, the adhesion of the oxide film varies depending on the location.
Part of it may peel off. Further, since aluminum oxide has extremely strong corrosion resistance, it cannot be easily removed by ordinary wet etching or dry etching. Further, aluminum oxide has a remarkably large etching selection ratio with respect to silicon oxide, and during etching of aluminum oxide, even peripheral materials such as silicon oxide may be remarkably etched. In particular, in the case of forming a complicated circuit, the gate electrode wirings of a number of transistors are connected to one wiring to perform anodic oxidation, and the wiring for that is to be removed later. It was difficult to remove the wiring covered with aluminum oxide. Further, when trying to form a contact in a limited portion of these gate electrode wirings, the surrounding material is also eroded, which is a great limitation in the fabrication of the circuit.

On the other hand, for example, Japanese Patent Application No. 3-3481.
As described in 30, a high-energy electromagnetic wave such as a laser beam is intensively applied to the etching area,
We proposed a method to remove the aluminum oxide and the underlying gate electrode wiring in that portion. However, with such a method, even the underlying gate electrode wiring is removed or considerably damaged, and it is almost impossible to form a contact.

The present invention has been made to solve such a problem, and proposes a manufacturing method for stably manufacturing an anodized aluminum gate transistor and a circuit arrangement suitable for the manufacturing method.

[0007]

[Means for Solving the Problem] As pointed out above, in manufacturing an anodized aluminum gate transistor,
There were two problems, that is, peeling of the anodic oxide film resulted in uneven adhesion, removal of unnecessary wiring after anodization, and formation of contact holes. As for the above, as a result of research by the present inventors, it has been clarified that the wiring including the gate electrode wiring should be optimized. That is, conventionally, since the width of the wiring is not particularly considered, the potential is different between the gate electrode wirings. This is because the current path leading to the gate electrode wiring was not taken into consideration. In such a situation, even if the anodic oxidation progresses in the same way, the thickness of the anodic oxide film occupying the wiring width becomes larger in the part where the line width is narrower than in the part where the line width is thick, resulting in The difference caused unevenness in adhesion, resulting in peeling. Therefore, the present invention is shown in FIG.
As shown in (A), the wirings up to the gate electrode wirings are hierarchized according to their width.

That is, the wiring extending from the current source is the widest main wiring 13, the branch wiring 5 narrower than the main wiring is provided from there, and further the gate electrode wiring 6 is provided at the end. With such a circuit arrangement,
The difference in the progress of anodic oxidation between the terminal gate electrode wirings was significantly suppressed, and the adhesion of the anodic oxide film on each gate electrode wiring could be made almost constant.

In order to solve the above-mentioned problem, in the present invention, a portion which is subsequently etched or a contact is formed is covered with an organic coating material so as not to be anodized. The organic coating material may be, for example, photo nice. Such organic coating materials are easily removed by a suitable solvent. In particular, it is desirable to have oxidation resistance enough to withstand anodic oxidation.

After removing the organic coating material, the metal wiring is exposed, so that the etching is easy, and there is no problem in forming the contact.
In particular, when forming a contact, after forming an interlayer insulator, a contact hole may be formed as usual to provide a contact. Examples are shown below,
The present invention will be further described.

[0011]

EXAMPLE 1 Example 1 is shown in FIGS. 1 and 2. FIG. 1 is a top view, and FIG. 2 is a conceptual cross section for each step in order to make the steps of the present invention easier to understand. Therefore, FIG. 2 is not a cross-section of the particular portion of FIG.

First, Corning 7059 glass was used as the substrate 1. Then, the underlying silicon oxide film 2 is formed to a thickness of 1
Only the thickness of 00 nm was formed by the sputtering method. further,
An amorphous silicon film was formed by plasma CVD to a thickness of 150 nm. This at 600 ℃ for 60 hours,
It was annealed in a nitrogen atmosphere and recrystallized. further,
This was patterned to form a plurality of island-shaped semiconductor regions 3.

Further, a gate oxide film 4 having a thickness of 115 nm is deposited by a sputtering method in an oxygen atmosphere targeting silicon oxide, and then an aluminum film (thickness 500 nm) is formed by electron beam evaporation. Then, this was patterned to form the first wiring 5, the second wiring 13, and the gate electrode wiring 6. Here, the first wiring is the branch wiring referred to in the present invention, and the second wiring is the trunk wiring. The width of these wirings was 4 μm for the first wiring and 10 μm for the second wiring. In this way, the outer shape of the thin film transistor (TFT) was adjusted. TFT at this time
The channel has a length of 2 μm and a width of 12 μm.

Further, 5 wt% is used for patterning this wiring.
% A mixture of nitric acid and phosphoric acid was used. For example, when the etching temperature is 40 ° C, wiring (aluminum)
The etching rate was 225 nm / min. The state so far is shown in FIG. 1 (A) and FIG. 2 (A).

Furthermore, Photo Nice (Toray UR380
0) was applied by a spin coater. Rotation speed is 25
It was 00 rpm. Then, this photo nice was patterned. In this case, the first wiring 5 and the second wiring 13 are left on the entire surface. Then, the wiring 13,
An aluminum oxide film 8 was formed on the periphery (top surface and side surface) of the gate electrode wiring not coated with photonice by applying an anodic oxidation method with electricity supplied to 5 and 6. Anodic oxidation is performed by adding 3% tartaric acid in ethylene glycol to 5%.
It was carried out using a solution neutralized with ammonia to a pH of 7.0 ± 0.2. First, platinum was immersed in a solution as a cathode, and further the TFT was immersed together with the substrate to connect the second wiring 13 to the anode of the power supply. The temperature was kept at 25 ± 2 ° C.

In this state, first, 0.1 to 0.5 mA /
When a voltage of 250 V is applied with a current of ² cm ² , the current is 0.005 mA / c while keeping the voltage constant.
When the current reached m ² , the current was stopped and the anodic oxidation was completed. The thickness of the anodized film thus obtained is 320
was nm. Figure 1 shows the state of the circuit obtained up to this point.
It shows in (B) and FIG. 2 (B).

Next, an N type impurity region (source / drain) 9a or a P type impurity region 9b was formed in the semiconductor region 3 by ion implantation. Phosphorus ions are used as the N-type dopant, and the ion energy is 70.
˜100 keV, and the phosphorus concentration was 1˜5 × 10 ¹³ cm ⁻² . BF ₃ ⁺ was used as the P-type dopant. The dose amount and the acceleration energy were the same as those for phosphorus doping. With this ion implantation, the source,
The drain region 9 has a portion (offset region) not overlapping the gate electrode with a thickness of aluminum oxide (about 300 n).
It is estimated that only m) are formed.

Next, the photonice was removed and laser annealing was performed. The laser used was a KrF excimer laser, and a laser pulse with a power density of 350 mJ / cm ² was irradiated for 50 shots. By this laser annealing, the portion which was made amorphous by ion implantation was recrystallized. The state of the circuit thus obtained is shown in FIGS. 1C and 2C.

Next, as shown in FIG. 1D, part of the first wiring and all of the second wiring are selectively removed, and C
A large number of MOS gate arrays were formed. Part of the first wiring was left as shown by 5a. After that, FIG. 2 (D)
As shown in FIG. 3, the interlayer insulator 10 is formed by sputter deposition of silicon oxide, and the contact holes 11a, 1 are formed on the semiconductor region 3 by a known photolithography technique.
1b was formed, and at the same time, the contact hole 12 was formed on the first wiring 5a. Of course, the contact holes do not necessarily have to be formed at the same time, and these contact holes may be formed independently as required. Then, a metal film is selectively formed to complete the semiconductor circuit.

[Second Embodiment] FIG. 3 shows the present embodiment. The wiring pattern seen from the upper surface is substantially the same as that of FIG.

First, Corning 7059 is used as the substrate 21.
Glass was used. Then, the underlying silicon oxide film 22 was formed to a thickness of 100 nm by the sputtering method. Further, an amorphous silicon film was formed by LPCVD to a thickness of 50 nm. This was irradiated with a pulsed laser to crystallize. As the laser, for example, KrF
An excimer laser was used. Energy density is 150
~ 350 mJ / cm ² , preferably 250-300 mJ
/ Cm ² was suitable. Further, this was patterned to form a plurality of island-shaped semiconductor regions 23.

Further, a gate oxide film 24 having a thickness of 115 nm is deposited by a sputtering method in an oxygen atmosphere targeting silicon oxide, and then an aluminum film (thickness 500 nm) is formed by electron beam evaporation. ,
This was patterned to form a first wiring 25 and a gate electrode wiring 26. In this way, the outer shape of the thin film transistor (TFT) was adjusted. At this time, the channel size of the TFT was 2 μm in length and 12 μm in width.

Also, 5 wt% is used for patterning this wiring.
% A mixture of nitric acid and phosphoric acid was used. For example, when the etching temperature is 40 ° C, wiring (aluminum)
The etching rate was 225 nm / min. The state up to this point is shown in FIG.

Furthermore, Photo Nice (Toray UR380
0) was applied by a spin coater. Rotation speed is 25
It was 00 rpm. Then, this photo nice was patterned and left only on the wiring 25, as shown in FIG. Then, electricity is applied to the wirings 25 and 26, and an aluminum oxide coating film 28 is formed around the gate electrode wiring not coated with photonice (upper surface and side surface) by anodic oxidation. The anodization was performed using a solution in which a 3% ethylene glycol solution of tartaric acid was neutralized with 5% ammonia to a pH of 7.0 ± 0.2. First, platinum was immersed in the solution as a cathode, and further the TFT was immersed together with the substrate, and the wiring was connected to the anode of the power supply. The temperature was kept at 25 ± 2 ° C.

In this state, first, 0.1 to 0.5 mA /
When a voltage of 250 V is applied with a current of ² cm ² , the current is 0.005 mA / c while keeping the voltage constant.
When the current reached m ² , the current was stopped and the anodic oxidation was completed. The thickness of the anodized film thus obtained is 320
was nm. Figure 3 shows the state of the circuit obtained up to this point.
It shows in (B).

Next, an N type impurity region (source / drain) 29a or a P type impurity region 29b is formed in the semiconductor region 23 by ion implantation. Phosphorus ions are used as the N-type dopant, the ion energy is 70 to 100 keV, and the phosphorus concentration is 1 to 5 × 10 ¹³ c.
m ^-2 . Further, as a P-type dopant, BF ₃
I used ⁺ . The dose amount and the acceleration energy were the same as those for phosphorus doping. By this ion implantation, in the source / drain region 29, a portion (offset region) that does not cover the gate electrode has a thickness of aluminum oxide (about 3 mm).
It is presumed that only (00 nm) was formed. This step may be performed by plasma doping (also referred to as ion doping) that does not allow mass separation of ions, or may be performed by another appropriate doping method.

Next, the photonice was removed and laser annealing was performed. At this time, unlike Example 1, laser irradiation was performed from the back surface of the substrate (see FIG. 3C). The laser is a XeCl excimer laser (wavelength 3
08nm) or XeF excimer laser (wavelength 3
50 nm) was used. Here, in selecting the laser, the light transmittance of the substrate (here, Corning 7059) must be taken into consideration. If it is quartz, a KrF laser (wavelength 248 nm) may be used. In this example, laser irradiation was performed from the back surface as shown in FIG. 3C, for example, 10 shots of laser pulse having a power density of 350 mJ / cm ² . By this laser annealing, the portion which was made amorphous by ion implantation was recrystallized.

This method is the same as the first embodiment in that the impurity region is activated by laser annealing, but the second laser annealing is performed from the back surface of the substrate, so that the impurity region and the channel forming region are formed. The purpose is to form a continuous connection. Defects due to discontinuous boundaries will be described later. However, when the laser irradiation is performed from only the back surface, only the substrate side of the silicon layer is often crystallized and may not reach the entire impurity region. For more reliable crystallization, laser irradiation may be performed from both sides.

Further, when the laser is irradiated from the upper surface as in Example 1, a phenomenon in which the wiring is separated due to the difference in the coefficient of thermal expansion is observed at the interface between the non-anodized region and the anodized region. However, since there is no such difference on the back surface, peeling of the wiring was suppressed by irradiation from the back surface.

After that, a part of the wiring 25 is removed, and
As shown in FIG. 3D, an inter-layer insulator 30 is formed by sputter deposition of silicon oxide, contact holes 31a and 31b are formed on the semiconductor region 23 by a known photolithography technique, and wiring is simultaneously formed. A contact hole 32 was also formed on 25a. Of course, the contact holes do not necessarily have to be formed at the same time, and these contact holes may be formed independently as required. Then, a metal film is selectively formed to complete the semiconductor circuit.

An example of the characteristics of the obtained element (NMOS) is shown in FIG. FIG. 4A shows the element characteristics when the laser irradiation for activating the impurity regions is performed from the upper surface. The initial characteristics (shown by a in the figure) are good, but the gate characteristics are When a 30V pulse is continuously applied, b
It has deteriorated as shown in. It is considered that this is because the interface between the impurity region and the channel formation region is discontinuous and the junction is weak, and hydrogen or the like terminating the dangling bond is released by long-term voltage application.

On the other hand, when the laser irradiation was performed from the back surface, there was no change in the initial characteristics (indicated by c in the figure) and after 100 hours (indicated by d in the figure). Thus, the effect of laser irradiation from the back surface was confirmed.

[0033]

As described above, according to the present invention, the wiring patterning of the anodized aluminum gate transistor can be easily performed to the same extent as in the case of the conventional transistor. In particular, the present invention is considered to be advantageous for microfabrication. Because aluminum oxide could not be removed by a normal dry etching process other than a special method such as laser etching, it was mainly performed by wet etching. However,
Since fine processing was difficult with wet etching,
The produced device also had a low degree of integration. According to the present invention, a dry etching process can be used, fine processing is possible, and the yield can be improved.

In the embodiments of the present invention, the transistor on the insulating substrate is described. This is used, for example, in an active matrix of a liquid crystal display device, which claims that the present invention cannot be used for manufacturing a transistor on a semiconductor substrate, that is, a normal semiconductor integrated circuit. Not something to do. Rather, if a semiconductor integrated circuit is manufactured at a low temperature on a semiconductor substrate by using a laser annealing process according to the present invention, the characteristics of the device will be superior to those of a conventional silicon gate. The present invention is also effective when forming a TFT on an insulating layer on a semiconductor substrate. As described above, the present invention is a basic technology widely required for manufacturing semiconductor circuits, and its industrial value is great.

[Brief description of drawings]

FIG. 1 shows a manufacturing process of a semiconductor circuit of the present invention. (Top view)

2A to 2D show steps of manufacturing a semiconductor circuit of the present invention. (Cross section)

FIG. 3 shows a manufacturing process of a semiconductor circuit of the present invention. (Cross section)

FIG. 4 shows an example of characteristics of the device obtained in the example.

[Explanation of symbols]

 1 Substrate 2 Base Oxide Film 3 Semiconductor Region 4 Gate Insulating Film 5 First Wiring 6 Gate Electrode Wiring 7 Organic Coating Material 8 Anodized Film 9 Impurity Region (Source / Drain) 10 Interlayer Insulator 11 Contact Hole (for Impurity Region) 12 contact hole (for first wiring) 13 second wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication H01L 29/784 // H01L 21/316 T 7352-4M (72) Inventor Shunpei Yamazaki Atsugi Kanagawa 398 Hase, Ichi, Ltd. Inside the Semiconductor Energy Laboratory Co., Ltd.

Claims (3)

[Claims] 1. A gate electrode wiring formed on a substrate,
The gate electrode wiring is connected to a first wiring having a width larger than that of the gate electrode wiring, and the first wiring is connected to a second wiring having a width larger than that of the first wiring. An electronic circuit characterized in that the wiring and the second wiring are formed in the same step by using a metal material containing aluminum as a main component. 2. An organic coating material is selectively formed on a gate electrode wiring formed on a substrate or a wiring connected to the gate electrode wiring, and an electric current is applied to the gate electrode wiring or the wiring connected to the gate electrode wiring in an electrolytic solution to carry out anodization. And a step of etching a part of a portion of the wiring for connecting to the gate electrode or a wiring connected to the gate electrode wiring covered with an organic coating material. 3. The method for manufacturing an electronic circuit according to claim 2, further comprising a step of implanting impurities and a step of irradiating a laser from the back surface of the substrate.