CN1033769C - Electric circuit and method for forming the same - Google Patents
Electric circuit and method for forming the same Download PDFInfo
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- CN1033769C CN1033769C CN 93106335 CN93106335A CN1033769C CN 1033769 C CN1033769 C CN 1033769C CN 93106335 CN93106335 CN 93106335 CN 93106335 A CN93106335 A CN 93106335A CN 1033769 C CN1033769 C CN 1033769C
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Abstract
An improved method of forming insulated gate field effect transistors is described. In accordance with the method, gate electrodes are formed from metal such as aluminum together with wirings electrically connecting the gate electrodes. The gate electrodes are anodic oxidized by dipping them as an anode in an electrolyte to form an oxide of the metal covering them. Since the connecting wirings are covered with a suitable organic film before the anodizing, no aluminum oxide is formed thereon so that it is easy to remove the connecting wiring by usual etching.
Description
The present invention generally relates to a kind of circuit.
Since the eighties, the grid of MOS (metal-oxide semiconductor (MOS)) N-type semiconductor N integrated circuit is mainly prepared by silicon.Because silicon gate and below semiconductor channel area between to have a little electronic energy poor, and silicon has big thermal resistance, this makes might adopt autoregistration (selfaligning) manufacturing technology for preparation source/drain region.In contrast, under the situation that adopts aluminium gate, this autoregistration manufacturing technology is inapplicable, and described aluminium gate once was extensive use of before adopting.This is because aluminium does not possess sufficient thermal endurance.Owing to this reason, it is out-of-date that aluminium gate is considered to, although it possesses low resistance.
Yet existing recently such report by adopting the laser annealing technology, under the situation of aluminium gate, also can adopt the autoregistration manufacturing technology to form source/drain region.Also propose such suggestion, can realize that by on grid, forming anode oxide film this film forms simultaneously with the wiring that is formed by same material fully with the layer insulation of grid.Below with grid and the wiring totally abbreviate grid wiring as because be difficult to always distinguish exactly them.Aluminum oxide film has sufficient corrosion resistance and sufficient resistance to pressure, and be used to form so-called biasing (offset) structure between grid and source region and the drain region, as described in flat (Hei) 3-340336, flat 4-30220 of the Japanese patent application of same Applicant or the flat 4-34194.
But, in the technology that adopts the anodization grid wiring, several problems have been pointed out.For example, even the outer surface of grid wiring is covered by aluminum oxide film, the adhesiveness between them also can change with the position on surface, so that aluminum oxide film comes off from following ground, grid wiring top sometimes.In addition, anodic aluminum oxide film is to adopt different thickness to form according to the position on grid.Further, because aluminum oxide film has extremely strong corrosion resistance, it is difficult that wet etching by routine or dry etching are removed, so that in removing the process of aluminum oxide film, near the material such as silica that is in the aluminum oxide film has etched trend.In addition, in the anodizing process that anode is handled as grid, because grid wiring integral body is interconnecting, the inessential part that is connected to each grid must be removed after anodization, so that these grids are separated.But aluminium oxide also applies unnecessary portions, and is difficult to they are removed.Also have, it is difficult offering and passing the connecting hole that corrosion resistant aluminum oxide film passes to necessity of following grid wiring, to such an extent as to adjacent circuit element also can be corroded.
On the other hand, also propose such suggestion, partly remove the grid wiring that is coated with aluminium oxide, and offer connecting hole, as described in the flat 3-348130 of Japanese patent application by necessity partly being given superlaser irradiation.Following grid wiring can be damaged by superlaser, so that seem and can not form connecting hole by this method.
As noted above, be coated with in the technology of grid of anode oxide film in employing, there is following shortcoming.
1) the adhering inconsistent film that causes between the anode oxide film of grid and covering comes off.
2) pass in the inessential part of removing the grid wiring that is coated with anode oxide film and formation and have difficulties aspect the anode oxide film connecting hole.
3) anode film is in uneven thickness.
Have been found that above-mentioned shortcoming 1 by the research that the inventor did) and 3) mainly be by the variation of the level of grid outer surface and thereby cause by the variation of the electric current by described surface.The oxidation rate on aluminium surface is by the level decision of said each position in anodization process.That is the difference of anodization speed, has been considered to reflect the difference of level.As a result, anodic oxide is being grown soon on than wide figure on the narrow figure, and owing to adhering difference the trend that comes off is arranged.
Therefore, an object of the present invention is to provide a kind of improved electronic device of aluminium gate that has.
A further object of the present invention is that a kind of improved electronic device will be provided, and wherein, the figure of anodized aluminium wiring can easily be realized.
Another purpose of the present invention is that a kind of improved electronic device that very fine structure is arranged will be provided.
Further purpose of the present invention is that a kind of improved electronic device with anodised aluminium gate will be provided.
Other purpose of the present invention, advantage and new feature will be described in the following description, and for the ordinary skill in the art, wherein part can be understood according to following analysis, perhaps can realize from enforcement of the present invention.Objects and advantages of the present invention can realize with combination by the means that particularly point out in the appended claims and obtain.
For realizing above-mentioned and other purpose, according to the present invention, as summarizing at this and broadly described, a kind of method of making semiconductor device may further comprise the steps: form the not aluminium figure of electrical separation on a substrate; With resist film aluminium coating figure partly; Outer surface to the aluminium pattern that do not cover resist film carries out anodization; Remove resist film.Particularly, by anodization aluminium visuals ground is covered by aluminium oxide, and after removing the resist film step, forms an exposed surface, can remove following aluminium figure or with this aluminium figure electrical connection by this exposed surface.
Under the situation of preparation insulated-gate type field effect transistor, on substrate, form a skim, this film comprises a kind of material of selecting from following material group: aluminium; Tantalum; Be mixed with the aluminium of silicon, copper, tantalum, scandium and palladium; Their alloy and their multilayer material, described film is made into figure, so that form grid, the public line of public line and high level.By in electrolyte them as anode pickling, grid is carried out anodic oxidation, to form the aluminium oxide of cover gate.Because before anodization, line covers the suitable organic membrane of last layer, alumina-free forms on it, thereby can easily remove line by conventional etching.
According to an aspect of the present invention, many grids is divided into many groups.Belong to every group grid and be connected in the many public lines corresponding one, public line has the width greater than grid.For reducing the resistance of first wiring, the width of public line is increased to the width greater than grid.Public line is connected to a public line of high level in proper order.That is to say that overall aluminium figure is designed to hierarchy (hierarchy fashion).A circuit according to the present invention comprises: at the such grid that forms on the substrate, at so public line of high level of so public line of the conduct that forms on the substrate first wiring and conduct second wiring that forms on substrate.Second wiring has the width greater than first wiring.For reducing the resistance of second wiring, the width of second wiring increases to the width greater than first wiring.Grid, first wiring and second wiring comprise that identical materials, this material are selected from following material group; Aluminium; Tantalum; Be mixed with the aluminium of silicon, copper, tantalum, scandium and palladium; Their alloy and their multilayer material.One channel shape is formed on the substrate and is adjacent with grid, and a gate insulating film is arranged therebetween.Can see a typical example from Fig. 1 (A), among this figure, a plurality of grids 6 are connected to a branch line 5 with big width, and a plurality of branch line 5 is connected to a main line with bigger width.According to this shape, the thickness and the degree of adhesion that cover the anode oxide film on the grid at the end of hierarchical system are mutually the same.
The aluminium figure that comprises grid can pass through dry etch technique, and for example laser-induced thermal etching comes etching, so that improve productivity ratio, because etched aluminum portions is not covered by corrosion resistant pellumina.Owing to this reason, can prepare very fine geometry.Before the present invention, aluminium oxide must be removed by wet etching, and this type of etching can be removed aluminium oxide but is unsuitable for preparing very fine structure, and integration density just can not improve so many like this.
Ratio (first wiring width)/(width of grid) preferably 2 to 10.And ratio (width of second wiring)/(width of first wiring) is 2 to 10.
Accompanying drawing comprises in the present invention and constitutes first of the present invention, and it and specification one are used from explains principle of the present invention.
Fig. 1 (A) is the plane graph that shows according to the method for the manufacturing complementary thin-film insulated gate polar form field-effect transistor of the first embodiment of the present invention to 1 (D).
Fig. 2 (A) to 2 (D) be with Fig. 1 (A) to the corresponding sectional drawing of 1 (D), it demonstrates the method according to the manufacturing complementary thin-film insulated gate polar form field-effect transistor of the first embodiment of the present invention.
Fig. 3 (A) to 3 (D) be the sectional drawing that shows the method for making the complementary thin-film insulated-gate type field effect transistor according to a second embodiment of the present invention.
Fig. 4 (A) is the V that shows the film-insulated grid type field-effect transistor of making according to the first embodiment of the present invention
G-I
DThe curve chart of characteristic.
Fig. 4 (B) is the V that shows the film-insulated grid type field-effect transistor of making according to a second embodiment of the present invention
G-I
DThe curve chart of characteristic.
Fig. 5 is the curve chart that shows as the relation between the etch-rate of the pressure of the oxygen plasma atmosphere of etching gas and organic coating, and described coating is made by Photoneece in oxygen plasma, and thickness is 2.3 microns.
Make the method for complementary thin-film insulated-gate type field effect transistor according to the first embodiment of the present invention to 2 (D) explanation to 1 (D) and Fig. 2 (A) referring now to Fig. 1 (A).For describe and explain convenient for the purpose of, Fig. 1 (A) is just conceptually corresponding and be not that geometry is corresponding exactly to 1 (D) and Fig. 2 (A) to 2 (D).
One glass plate is used as substrate 1.For example this glass plate is the Corning7059 glass plate that healthy and free from worry (Corning) company makes.On substrate, forming thickness by sputter is the silicon oxide film 2 of 100nm.On silicon oxide film 2, be the amorphous semiconductor films of 150nm by plasma CVD (chemical vapor deposition) deposit thickness.Constitute figure then by making the crystallization again of this semiconductive thin film in 60 hours, and by photolithography and active-ion-etch with a plurality of semiconductor island 3 at 600 ℃ of thermal annealings.In oxygen be that target is the silicon oxide film 4 of 115nm by sputter precipitation thickness, to form gate insulating film with the silica.By forming thickness on the electron beam evaporation silicon oxide film 4 is the aluminium film of 500nm, and constitute figure so that form grid 6 branch lines 5 and main line 13 by etching, here said etching for example, is the wet etching that adopts the mixed acid etchant that adds 5% nitric acid preparation in phosphoric acid.Grid 6, branch line 5 and main line 13 are electrically connected to each other and form, shown in Fig. 1 (A).Etch-rate is (for example) about 225nm/ minute.The width of branch line 5 is 4 microns.The width of main line 13 is 10 microns.The length of the raceway groove that forms under grid 6 is that 2 microns face width degree are 12 microns.By above process, on substrate, just formed transistorized necessary profile, shown in Fig. 1 (A) and 2 (A).One deck organic coating optionally is formed at grid or in the wiring that (branch line and main line) links to each other therewith that forms on the substrate.
Then in electrolyte by applying electric current, the wiring anodic oxidation that makes grid 6 or link to each other therewith, and branch line 5 and main line 13 are partly covered by organic coating is so that be removed or provide the aluminium film of connection not covered by corrosion resistant oxide-film.A part or at least a portion of organic coating are etched away, so that expose grid or continuous therewith wiring in said part.Organic coating preferably forms by having 270 ℃ or higher stable on heating organic material.For this reason, be suitable based on organic polyimides to material.An exemplary of this polyimides based on material is Photoneece (UR3800), and it is a kind of photosensitive organic resin of being made by Tore industrial group.This resin is composition easily.This class organic coating can by suitable solvent for example hydrazine remove at an easy rate, perhaps remove at an easy rate by the plasma that for example produces in nitrogen dioxide or the ozone in oxygen or other oxidizing gas atmosphere.On the other hand, this type of organic layer can stop the anodic oxidation environment.
Fig. 5 depicts the relation between the etch-rate of the pressure of oxygen plasma atmosphere and organic coating, and described organic coating is made by Photoneece, and thickness is 2.3 microns.The local pressure of oxygen is 100%.Produce plasma by at room temperature between two blocks of parallel-plates, applying radio frequency (RF) electric energy, thereby realize etching (polishing) during this time.Oxygen is that the speed with 2.3SCCM adds to etching space continuously.As road as we know from the figure, etch-rate is directly proportional with the pressure of oxygen plasma.Though not shown, can find that according to experiment etch-rate raises with temperature and increases during polishing, and in room temperature to 300 ℃ scope, is linear proportional relation between them.Therefore, confirm, can improve etch process performance by the local pressure that improves oxidizing gas.
That is to say that the Photoneece (UR3800) by Tore industrial group makes by spin coating on substrate 1, is covered on grid 6, branch line 5 and the main line 13.The speed of rotation is 2500rpm.Organic membrane was able to drying in 1 hour by the temperature baking with 80 ℃ in nitrogen.After the oven dry, coating is partly removed by composition, so that only stay the rete 7 that covers branch line 5 and main line 13, shown in Fig. 1 (B).Coating 7 is once more 300 ℃ of bakings 0.5 to 2 hour, to make it to become polyimide film.Then, the outer surface of grid 6 is promptly formed the pellumina that covers them with side surface on it by anodic oxidation.Anodization is performed such, and the substrate that will have grid is dipped in the solution as anode, also will be dipped in as the platinum of negative electrode in the solution simultaneously, flows through an electric current by grid 6, branch line 5 and main line 13.Described solution is by the ammoniacal liquor that adopt to add 5%, in and 3% 2,1 of 3-dyhydrobutanedioic acid (tartaric acid), inferior ethylene glycol (ethylene glycol) formulations prepared from solutions of 2-so that its pH value reduces to 7.0 ± 0.2.Solution temperature remains on 25 ± 2 ℃ during anode treatment.
During anodization, electric current is in the following manner by grid 6, branch line 5 and main line 13.At first, regulating the voltage between anode and the negative electrode, is 0.1 to 0.5mA/cm so that make the electric current that flows through
2, 0.5mA/cm for example
2For holding current density fixed voltage will progressively improve.When voltage reached 250V, anodization was proceeded, and voltage keeps 250V, yet current density progressively reduces.When current density reduces 0.005mA/cm
2The time, substrate is shifted out from solution, and place the plasma chamber that makes the substrate polishing, to remove Photoneece coating 7.The pressure of plasma chamber is 0.2 to 2.0 torr.Radio-frequency power is 0.1 to 0.3w/cm
3The plasma that forms in the chamber during the polishing is an oxygen plasma.The etch-rate that polishing causes can improve in 90 to 300 ℃ by heated substrate.As a result, shown in Fig. 1 (B) and 2 (B), having formed thickness is the aluminum oxide film 8 of 320nm.
Next step forms source region and drain region in semiconductor island 3, so that according to known CMOS manufacturing technology, be infused in by ion and form n channel region and p channel region around here.Digital 9a among Fig. 1 (C) and 9b represent p raceway groove and n channel transistor respectively.That is to say that phosphonium ion is injected into the semiconductor island that is used for p channel transistor 9a with 70 to 110Kev accelerating voltage, and grid 6 and aluminum oxide film 8 cover the middle part of semiconductor island, to become channel region.Final phosphorus is from being 1 to 5 * 10 in concentration
13Cm
-2Boron fluoride ion (BF
3 +) be injected into the semiconductor island that is used for n channel transistor 9b with same program.By aluminum oxide film 8, grid is left in source region and drain region 9 in the so-called bias structure as shown in Fig. 2 (c) edge one segment distance forms.Offset or dish is considered about 300nm, and this thickness with aluminum oxide film 8 is corresponding.
Because the crystallinity in source region and drain region 9 is substantially ion and injects institute and destroy and become the amorphism structure basically, thus for make source region and drain region again crystallization to carry out laser annealing.Laser annealing is by using 50 laser pulses irradiate semiconductors by the emission of KrF excimer laser to carry out.The energy density of laser pulse is (for example) 350mj/cm
2In the case for obtaining identical operating state, available halogen lamp instead of lasers.After the annealing, branch line 5 and main line 13 are optionally removed, so that only stay the part 5a of the branch line 5 shown in Fig. 1 (D).Just a plurality of CMOS grid arrays have been formed subsequently.Can easily connect grid by part 5a.
On this structure, cover one deck silica barrier film 10 by sputtering sedimentation then.Adopt known photoetching technique, pass silicon oxide film 4 and 10 and offer connecting hole 11a and 11b, so that expose source region and drain region 9.Pass silicon oxide film 4 and 10, also can offer suitable connecting hole 12, so that expose wiring 5a.These connecting holes can form at the same time or separately according to the required suitable procedures of this method.At last, by deposition of aluminum or chromium thin film and make it composition, form required wiring by metal film.
Explain the method for manufacturing complementary thin-film insulated-gate type field effect transistor according to a second embodiment of the present invention to 3 (D) referring now to Fig. 3 (A).The plane graph of Fig. 3 (A) to 3 (D), with Fig. 2 (A) to the identical mode of 2 (D), and conceptually corresponding to 1 (D) with Fig. 1 (A).
One glass plate is as substrate 21.This glass mean pole is the Corning7059 glass plate that (for example) made by Corning company.Formation thickness is the silicon oxide film 22 of 100nm on the substrate by sputtering at.By low pressure chemical vapor deposition, on silicon oxide film, forming thickness is the amorphous semiconductor films of 50nm.This semiconductive thin film is by laser annealing crystallization again.Laser annealing is to realize by adopting by the pulsed light irradiation semiconductor of KrF excimer laser emission.The energy density of laser pulse is that (for example) 150 is to 350mj/cm
2, preferably 250 to 300mj/cm
2Make the semiconductive thin film composition by photolithography and active-ion-etch then, so that on substrate, constitute a plurality of semiconductive thin film islands 23.By in oxygen, with the silica be target to sputter at the thickness that deposition on the substrate 21 covers semiconductive thin film island 23 be the silicon oxide film 24 of 115nm so that form gate insulating film.Pass through electron beam evaporation, forming thickness on silicon oxide film 24 is the aluminium film of 500nm, and passes through the mixed acid corrosion of the nitric acid preparation of interpolation 5% in phosphoric acid, makes aluminium film composition, to form grid 26, branch line and main line, promptly identical grid wiring with first embodiment.Corrosion rate is (for example) about 225nm/ minute.The raceway groove that under grid 26, forms, long 2 microns wide 12 microns.By above-mentioned operation, on substrate, just formed transistorized necessary profile as shown in the figure.
On substrate 21,, form the photosensitive organic resin of cover gate wiring by spin coating.This photosensitive organic resin is the Photoneece (UR3800) that (for example) made by Tore industrial group.The speed of rotation is 2500rpm.By composition with this (organic) coating layer portion remove so that only stay the film 27 that covers wiring 25, shown in Fig. 3 (B).The exposed surface of grid 26, i.e. its upper surface and side surface are thereafter by anodic oxidation, so that form the aluminum oxide film that covers them.Anodization is performed such, and will have the grid substrate as anode, connects same platinum plate as negative electrode, impregnated in the solution, and allows electric current flow through grid 26.Described solution is by the ammoniacal liquor that adds 5%, in and 3% 2,1 of 3-dyhydrobutanedioic acid, the inferior ethanolic solution preparation of 2-so that its PH reduces to 7.0 ± 0.2.The temperature of solution remains on 25 ± 2 ℃ during anodization.
Electric current is as follows by grid 26 during anodization.At first, regulate the voltage between anode and the negative electrode, making the electric current that flows through is 0.1 to 0.5mA/cm
2, for example, 0.5mA/cm
2For keeping this current density, voltage will progressively improve.When voltage reached 250 volts, anodization was proceeded, and voltage keeps 250V, yet current density progressively reduces.When current density is reduced to 0.005mA/cm
2The time, anodization just is through with.As a result, shown in Fig. 1 (B) and 2 (B), having formed thickness is the aluminum oxide film 28 of 320nm.
Next step forms source region and drain region in semiconductive thin film island 23 on substrate, form n raceway groove and p raceway groove around here so that be infused in by ion according to known CMOS manufacturing technology.With the mode identical, form p raceway groove and n channel transistor with first embodiment.That is to say that as the phosphonium ion of impurity, the accelerating voltage with 70 to 110KeV is introduced into the semiconductive thin film island that is used for the p channel transistor, and grid 26 and aluminum oxide film 28 cover the middle part of semiconductive thin film island so that become channel region.The ultimate density of phosphonium ion is 1 to 5 * 10
13Cm
2Boron fluoride (BF
3 +) be introduced into the semiconductive thin film island that is used for the n channel transistor with same operation.By aluminum oxide film 28, the source region and the drain region 29 of a folder raceway groove, the edge certain distance apart from grid in the so-called bias structure shown in Fig. 3 (C) forms.Bias area is formed between each of raceway groove and source region and drain region.Offset or dish is considered about 300nm, and the thickness of this and aluminum oxide film 28 is corresponding.The formation in source region and drain region can be passed through plasma doping technology (that is, ion doping technique) or other suitable doping techniques and realize that described plasma doping technology can not be according to the differential separation different ions of quality.
After removing Photoneece film 27, carry out laser annealing, so that make the crystallization again of source region and drain region by the mode identical with first embodiment.Yet in the case, laser annealing is adopted 10 laser pulses to pass substrate 21 irradiation semiconductors and is realized.That is to say the rear side surface of the laser alignment substrate 21 of pulse.Laser is XeCl excimer laser (308nm wavelength) or KrF excimer laser (350nm wavelength).The selection of laser will be considered the light transmittance of substrate (being Corning7050 in the case).If substrate is made by quartz, can use KrF laser (248nm wavelength), the energy density of laser pulse is (for example) 350mj/cm
2For obtaining identical operating state, laser can be substituted by halogen lamp.After the annealing, the wiring 25 of capping oxidation aluminium is not optionally removed, so that only stay the part 25a shown in Fig. 3 (C).As a result, a plurality of CMOS grid arrays have been formed.
Thereafter, cover this structure for 30 meters by sputtering sedimentation silica barrier film.Use known photoetching technique, pass silicon oxide film 24 and 30, offer connecting hole 31a and 31b, to expose source region and drain region 29.Pass silicon oxide film 24 and 30 and also can offer suitable connecting hole 32, to expose wiring 25a.The suitable operation required according to the method, these connecting holes can form at the same time or separately.At last, by deposition of aluminum or chromium film and make it composition, form required wiring by metallic film.
Under the situation of second embodiment, use the mode identical to make the crystallization again of semiconductive thin film island by laser annealing with first embodiment.But, second laser annealing is performed such, and after introducing impurity, with the light that laser or halogen lamp send, substrate and semiconductive thin film island are shone in (from substrate behind) from behind.This makes and might form source region and drain region simultaneously and to be connected to therebetween raceway groove smoothly.If save first laser annealing, the crystallization fully again of the top of semiconductive thin film island.For this reason, preferably carry out laser annealing (or lamp annealing) from the both sides of substrate.In addition, because being the rear side surface from substrate, second laser annealing carries out, this can prevent peeling off of grid wiring effectively, and this reason of peeling off is, by having different thermal coefficient of expansions between aluminum oxide film part that covers and the part that does not have aluminum oxide film to cover.
From the real advantage of the rear side surface of substrate irradiation, will from Fig. 4 (A) and 4 (B), recognize.Under the situation of upper surface irradiation, I
D-V
GIt is good that characteristic begins, represented as curve (a) among Fig. 4 (A), but when 25 to 30 volts pulse repeatedly as to grid the time, I
D-V
GCharacteristic degenerates significantly, shown in curve (b).This is considered to owing to following reason: because the interface is discontinuous and forms bad connection that hydrogen atom termination dangling bonds disconnect from the interface in channel region and source region and drain region.On the other hand, when with laser during from the rear side surface of substrate irradiation semiconductive thin film island, the original properties shown in curve (C) among Fig. 4 (B) is kept, even does not also have after 100 hours in work and significantly to become bad, shown in the middle curve (D) of Fig. 4 (B).
The above-mentioned explanation of preferred embodiment is for the usefulness of describing and explain the present invention.It does not also mean that to be exactly of the present invention whole, and perhaps the present invention is limited to described concrete form, and, obviously can carry out multiple changes and improvements according to above-mentioned instruction.The selection of embodiment is in order more clearly to explain principle of the present invention and practical application thereof, thereby makes others skilled in the art in various execution modes and adopt various changes to be suitable for specific desired application and use the present invention most effectively.
Claims (8)
1. a circuit comprises:
Be located at the grid on the substrate, it comprises a kind of material in the group that is selected from following material composition: aluminium, and tantalum is added with silicon, copper, tantalum, the aluminium of scandium and palladium, their alloy, and their multilayer material;
Be located at the wiring of first on the described substrate, it links to each other with described grid and comprises described material, and described first wiring has the width greater than described grid; With
Be located at the wiring of second on the described substrate, it links to each other with described first wiring and comprises described material, and described second wiring has the width greater than described first wiring.
2. according to the circuit of claim 1, it further comprises and is located on the described substrate and the raceway groove adjacent with described grid, is provided with gate insulating film between this raceway groove and described grid.
3. according to the circuit of claim 2, it further comprise be located on the described substrate and between the source region and the drain region of the described raceway groove of folder.
4. according to the circuit of claim 3, wherein, be provided with bias area between each in described raceway groove and described source region and drain region.
5. a circuit comprises:
Be located at the grid on the substrate, it comprises a kind of material in the group that is selected from following material composition: aluminium, and tantalum is added with silicon, copper, tantalum, the aluminium of scandium and palladium, their alloy, and their multilayer material;
Be located at the wiring of first on the described substrate, it links to each other with described grid and comprises described material, and described first wiring has the width greater than described grid;
Be located at the wiring of second on the described substrate, it links to each other with described first wiring and comprises described material, and described second wiring has the width greater than described first wiring; With
Cover the anodic oxide on the described grid.
6. a circuit comprises:
Be located at the grid on the substrate, it comprises a kind of material in the group that is selected from following material composition: aluminium, and tantalum is added with silicon, copper, tantalum, the aluminium of scandium and palladium, their alloy, and their multilayer material:
Be located at the wiring of first on the described substrate, it links to each other with described grid and comprises described material, and the width of described first wiring increases to the width greater than described grid, so that reduce the resistance of described first wiring; With
Be located at the wiring of second on the described substrate, it links to each other with described first wiring and comprises described material, and the width of described second wiring increases to the width greater than described first wiring, to reduce the resistance of described second wiring.
7. according to the circuit of claim 6, wherein, ratio (width of described first wiring)/(width of described grid wiring) is 2 to 10.
8. according to the circuit of claim 6, wherein, ratio (width of described second wiring)/(width of described first wiring) is 2 to 10.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP143319/92 | 1992-05-09 | ||
| JP14331992 | 1992-05-09 | ||
| JP28235292A JP3150792B2 (en) | 1992-05-09 | 1992-09-28 | Electronic circuit fabrication method |
| JP282352/92 | 1992-09-28 | ||
| JP360192/92 | 1992-12-28 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96103218A Division CN1115722C (en) | 1992-05-09 | 1996-01-29 | Method for forming electric circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1081282A CN1081282A (en) | 1994-01-26 |
| CN1033769C true CN1033769C (en) | 1997-01-08 |
Family
ID=26475084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 93106335 Expired - Lifetime CN1033769C (en) | 1992-05-09 | 1993-05-08 | Electric circuit and method for forming the same |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3150792B2 (en) |
| CN (1) | CN1033769C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1984944B (en) * | 2004-06-09 | 2011-03-09 | 荷兰应用科学研究会(Tno) | Fibre-reinforced polymer composites and processes for preparing the same |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3469337B2 (en) * | 1994-12-16 | 2003-11-25 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP3176253B2 (en) * | 1995-05-25 | 2001-06-11 | シャープ株式会社 | Circuit board |
| JP5044427B2 (en) * | 2008-01-29 | 2012-10-10 | 日本放送協会 | Electronic device manufacturing method and circuit board |
-
1992
- 1992-09-28 JP JP28235292A patent/JP3150792B2/en not_active Expired - Fee Related
-
1993
- 1993-05-08 CN CN 93106335 patent/CN1033769C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1984944B (en) * | 2004-06-09 | 2011-03-09 | 荷兰应用科学研究会(Tno) | Fibre-reinforced polymer composites and processes for preparing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1081282A (en) | 1994-01-26 |
| JP3150792B2 (en) | 2001-03-26 |
| JPH0629279A (en) | 1994-02-04 |
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