JP2009182015A - Manufacturing method of circuit board and electronic element, and circuit board - Google Patents

Manufacturing method of circuit board and electronic element, and circuit board Download PDF

Info

Publication number
JP2009182015A
JP2009182015A JP2008017565A JP2008017565A JP2009182015A JP 2009182015 A JP2009182015 A JP 2009182015A JP 2008017565 A JP2008017565 A JP 2008017565A JP 2008017565 A JP2008017565 A JP 2008017565A JP 2009182015 A JP2009182015 A JP 2009182015A
Authority
JP
Japan
Prior art keywords
wiring
circuit board
manufacturing
thin film
compensation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008017565A
Other languages
Japanese (ja)
Other versions
JP5044427B2 (en
Inventor
Yoshiki Nakajima
宜樹 中嶋
Tatsuya Takei
達哉 武井
Yoshihide Fujisaki
好英 藤崎
Toshihiro Yamamoto
敏裕 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Broadcasting Corp
Original Assignee
Nippon Hoso Kyokai NHK
Japan Broadcasting Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Hoso Kyokai NHK, Japan Broadcasting Corp filed Critical Nippon Hoso Kyokai NHK
Priority to JP2008017565A priority Critical patent/JP5044427B2/en
Publication of JP2009182015A publication Critical patent/JP2009182015A/en
Application granted granted Critical
Publication of JP5044427B2 publication Critical patent/JP5044427B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board whereby an insulating film can be surely formed, even if there are disconnected spots in wiring, and to provide a manufacturing method of an electronic element whereby the electronic element is formed on the circuit board, and the circuit board. <P>SOLUTION: This circuit board 10 is equipped with a board 11, a plurality of wiring 12, a plurality of compensation wiring s13 to connect between a plurality of the wiring 12, and a power supply connecting part 14, to which a dc power supply is connected, when anodizing is carried out. A plurality of the wiring 12 are equipped with wiring conductor parts 12a formed by a valve metal, wiring insulating films 12b formed by anodizing the surface of the valve metal, respectively. A plurality of the compensation wiring 13 are equipped with compensation wiring conductor parts 13a, formed in regions between pixel regions 15 adjacent to each other and forme by the valve metal, and compensation wiring insulating films 13b formed by anodizing the surface of the valve metal, respectively. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、複数の配線に絶縁膜が形成された回路基板、この回路基板の製造方法及びそれに電子素子を形成する電子素子の製造方法に関する。   The present invention relates to a circuit board in which an insulating film is formed on a plurality of wirings, a method for manufacturing the circuit board, and a method for manufacturing an electronic element for forming an electronic element thereon.

近年、ディスプレイの大型化、高精細化及び薄型化が急速に進んでおり、種々の薄型ディスプレイが開発されている。これらの薄型ディスプレイには、薄膜トランジスタ(TFT)や薄膜コンデンサといった薄膜デバイスを集積化した背面板が用いられている。今後はディスプレイの更なる薄型化、軽量化が図られ、背面板として例えばプラスチックフィルムのような柔軟性を有する基板が用いられると考えられる。   In recent years, the enlargement, high definition, and thinning of displays have rapidly progressed, and various thin displays have been developed. In these thin displays, a back plate in which thin film devices such as thin film transistors (TFTs) and thin film capacitors are integrated is used. In the future, the display will be made thinner and lighter, and a flexible substrate such as a plastic film will be used as the back plate.

しかしながら、プラスチックフィルムは、従来一般に用いられる基板(例えばガラス基板)と比べ耐熱性が低いので、従来の薄膜デバイスの製造方法がプラスチックフィルムにはそのまま適用できないという課題があった。例えば、薄膜デバイスの製造に必要とされる絶縁膜の形成工程は、従来のスパッタリング法や蒸着法では一般に300℃以上で行われるので、プラスチックフィルムには適用できない。   However, since the plastic film has low heat resistance as compared with a conventionally used substrate (for example, a glass substrate), there has been a problem that the conventional method for manufacturing a thin film device cannot be applied to a plastic film as it is. For example, an insulating film forming process required for manufacturing a thin film device is generally performed at 300 ° C. or higher by a conventional sputtering method or vapor deposition method, and thus cannot be applied to a plastic film.

この課題の解決を図ることを目的として、陽極酸化法という手法を用いて絶縁膜を形成する製造方法が知られている(例えば、特許文献1参照)。特許文献1に示された製造方法は、ゲート電極が形成された基板を電解液に浸漬し、ゲート電極を陽極、電解液中の対向電極を陰極として直流電源を接続し、電気分解を行うことによってゲート電極上に絶縁膜を形成するものである。
特開2003−258260号公報
In order to solve this problem, a manufacturing method is known in which an insulating film is formed using a technique called anodizing (see, for example, Patent Document 1). In the manufacturing method disclosed in Patent Document 1, a substrate on which a gate electrode is formed is immersed in an electrolytic solution, and a direct current power source is connected using the gate electrode as an anode and the counter electrode in the electrolytic solution as a cathode to perform electrolysis. Thus, an insulating film is formed on the gate electrode.
JP 2003-258260 A

しかしながら、特許文献1に示された従来の製造方法では、直流電源が接続される位置からゲート電極が形成される位置までの基板上の配線に断線箇所があると、その断線箇所より先の領域に直流電源からの電荷が供給されないので、その領域にあるゲート電極には絶縁膜が形成されないこととなる。   However, in the conventional manufacturing method shown in Patent Document 1, if there is a disconnection point in the wiring on the substrate from the position where the DC power supply is connected to the position where the gate electrode is formed, the region ahead of the disconnection point Since no electric charge is supplied from the DC power source, an insulating film is not formed on the gate electrode in that region.

その結果、絶縁膜形成後の工程において基板上に作製される薄膜デバイスのうち、該当する領域内のものには絶縁膜がないため電極間がショートした不良が発生し、この不良は修繕できないので基板全体が不良になるという課題があった。特に、従来の製造方法では、画面が大型化するに従って配線が長くなり複雑化するため断線の確率が大きくなり、基板の不良が発生しやすくなるので、その改善が望まれていた。   As a result, among the thin-film devices fabricated on the substrate in the process after the formation of the insulating film, there is no insulating film in the device in the corresponding area, so a defect occurs in which the electrodes are short-circuited, and this defect cannot be repaired. There was a problem that the entire substrate became defective. In particular, in the conventional manufacturing method, since the wiring becomes longer and more complicated as the screen becomes larger, the probability of disconnection increases and the substrate is likely to be defective.

本発明は、前述した事情に鑑みてなされたものであり、配線に断線箇所がある場合でも絶縁膜を確実に形成することができる回路基板の製造方法、及び回路基板に電子素子を形成する電子素子の製造方法、並びに回路基板を提供することを目的とする。   The present invention has been made in view of the above-described circumstances, and a method of manufacturing a circuit board capable of reliably forming an insulating film even when the wiring has a disconnection portion, and an electron forming an electronic element on the circuit board An object of the present invention is to provide an element manufacturing method and a circuit board.

本発明の回路基板の製造方法は、基板上に複数の配線を形成する工程と、前記複数の配線の予め定められた箇所同士を電気的に接続する電気的接続手段を形成する工程と、前記複数の配線のそれぞれに絶縁膜を電気的に形成する工程と、前記電気的接続手段を除去する工程とを含む構成を有している。   The method for manufacturing a circuit board according to the present invention includes a step of forming a plurality of wirings on a substrate, a step of forming an electrical connection means for electrically connecting predetermined locations of the plurality of wirings, It has a configuration including a step of electrically forming an insulating film on each of the plurality of wirings and a step of removing the electrical connection means.

この構成により、本発明の回路基板の製造方法は、絶縁膜を形成する工程において電気的接続手段が複数の配線間を電気的に接続するので、配線に断線箇所があっても電気的接続手段を介して断線箇所より先に電荷を供給することができ、絶縁膜を確実に形成することができる。   With this configuration, in the method of manufacturing a circuit board according to the present invention, the electrical connection means electrically connects the plurality of wirings in the step of forming the insulating film. Thus, the electric charge can be supplied prior to the disconnection portion, and the insulating film can be reliably formed.

本発明の電子素子の製造方法は、前記基板上に電子素子を形成する電子素子の製造方法であって、前記絶縁膜上に電極を形成する工程を含む構成を有している。   The method for manufacturing an electronic device of the present invention is a method for manufacturing an electronic device on the substrate, and includes a step of forming an electrode on the insulating film.

この構成により、本発明の電子素子の製造方法は、確実に形成される絶縁膜上に電極を形成できるので、この絶縁膜を用いた電子素子を製造する際の製造歩留の向上を図ることができる。   With this configuration, the method for manufacturing an electronic device according to the present invention can form an electrode on an insulating film that is reliably formed. Therefore, the manufacturing yield when manufacturing an electronic device using this insulating film is improved. Can do.

本発明の回路基板は、回路基板の製造方法で製造される回路基板であって、前記電気的接続手段が除去された痕跡を有するものである。   The circuit board of the present invention is a circuit board manufactured by a method for manufacturing a circuit board, and has a trace from which the electrical connection means has been removed.

この構成により、本発明の回路基板は、配線に断線箇所があっても電気的接続手段が断線箇所より先に電荷を供給することによって形成した絶縁膜を備えることとなる。
したがって、本発明の回路基板は、確実に形成される絶縁膜上に電子素子を形成することができるので、電子素子を形成する際の製造歩留の向上を図ることができる。
With this configuration, the circuit board of the present invention includes an insulating film formed by supplying electric charges before the disconnection site even if the wiring has a disconnection site.
Therefore, the circuit board of the present invention can form an electronic element on an insulating film that is reliably formed, so that it is possible to improve the manufacturing yield when the electronic element is formed.

本発明は、配線に断線箇所がある場合でも絶縁膜を確実に形成することができる回路基板の製造方法、及び回路基板に電子素子を形成する電子素子の製造方法、並びに回路基板を提供することができるものである。   The present invention provides a method for manufacturing a circuit board capable of reliably forming an insulating film even when the wiring has a broken portion, a method for manufacturing an electronic element for forming an electronic element on the circuit board, and a circuit board. It is something that can be done.

以下、本発明の実施の形態について図面を用いて説明する。なお、本発明の回路基板をディスプレイの背面板に適用した例を挙げて説明する。また、このディスプレイの画素は4個×5個のマトリクス状に配置されるものとする。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. An example in which the circuit board of the present invention is applied to a back plate of a display will be described. The pixels of this display are arranged in a matrix of 4 × 5.

まず、本発明に係る回路基板の一実施の形態における構成について説明する。図1は、本実施の形態における回路基板の概念図であって陽極酸化処理後の構成を示しており、図1(a)は概念平面図、図1(b)及び(c)は、それぞれ、図1(a)における断面AA及びBBを部分拡大して示した概念断面図である。   First, the configuration of an embodiment of a circuit board according to the present invention will be described. FIG. 1 is a conceptual diagram of a circuit board in the present embodiment and shows a configuration after anodizing treatment. FIG. 1 (a) is a conceptual plan view, and FIGS. 1 (b) and (c) are respectively diagrams. FIG. 2 is a conceptual cross-sectional view showing a cross-section AA and BB in FIG.

図1に示すように、本実施の形態における回路基板10は、基板11と、複数の配線12と、複数の配線12の間を接続する複数の補償配線13と、陽極酸化処理を行う際に直流電源が接続される電源接続部14とを備えている。   As shown in FIG. 1, the circuit board 10 according to the present embodiment includes a substrate 11, a plurality of wirings 12, a plurality of compensation wirings 13 connecting the plurality of wirings 12, and an anodizing process. And a power supply connection portion 14 to which a DC power supply is connected.

基板11は、例えば、厚さが100μm〜200μm程度のプラスチックフィルムで構成され、画素が形成される画素形成領域15を有している。この画素形成領域15は、例えば、100μm〜1000μm程度の大きさであり、この領域には発光ダイオードが形成されるようになっている。なお、プラスチックフィルムに代えてガラス基板やシリコン基板等を用いて基板11を構成してもよい。   The substrate 11 is made of, for example, a plastic film having a thickness of about 100 μm to 200 μm, and has a pixel formation region 15 in which pixels are formed. The pixel formation region 15 has a size of about 100 μm to 1000 μm, for example, and a light emitting diode is formed in this region. The substrate 11 may be configured using a glass substrate, a silicon substrate, or the like instead of the plastic film.

複数の配線12は、それぞれ、例えば、バルブ金属を材料として形成されたものであって、バルブ金属で構成された配線導体部12aと、バルブ金属の表面を陽極酸化して形成された配線絶縁膜12bとを備えている。ここで、配線導体部12aは、例えば、100nm〜200nm程度の厚さで形成される。また、配線絶縁膜12bは、例えば、100nm〜200nm程度の厚さで形成され、配線絶縁膜12b上には薄膜コンデンサや薄膜トランジスタ等の電極が形成されるようになっている。   Each of the plurality of wirings 12 is formed by using, for example, a valve metal as a material, and a wiring conductor portion 12a made of the valve metal and a wiring insulating film formed by anodizing the surface of the valve metal 12b. Here, the wiring conductor portion 12a is formed with a thickness of about 100 nm to 200 nm, for example. Further, the wiring insulating film 12b is formed with a thickness of, for example, about 100 nm to 200 nm, and electrodes such as a thin film capacitor and a thin film transistor are formed on the wiring insulating film 12b.

複数の補償配線13は、それぞれ、複数の配線12の予め定められた位置の間を接続するよう設けられている。本実施の形態においては、複数の補償配線13は、それぞれ、互いに隣接する画素形成領域15の間の領域に形成されている。なお、複数の補償配線13は、それぞれ、本発明に係る電気的接続手段を構成する。   The plurality of compensation lines 13 are provided so as to connect between predetermined positions of the plurality of lines 12. In the present embodiment, the plurality of compensation wirings 13 are each formed in a region between adjacent pixel formation regions 15. Each of the plurality of compensation wires 13 constitutes an electrical connection unit according to the present invention.

また、複数の補償配線13の材料は、例えば、複数の配線12と同様にバルブ金属を材料として構成されるものであって、バルブ金属で構成された補償配線導体部13aと、バルブ金属の表面を陽極酸化して形成された補償配線絶縁膜13bとを備えている。また、補償配線導体部13aは、配線導体部12aと一体化して形成されており、互いに電気的に接続されている。この補償配線導体部13aは、絶縁膜形成後の工程で除去されるものである。   Further, the material of the plurality of compensation wires 13 is, for example, made of a valve metal as a material similarly to the plurality of wires 12, and the compensation wire conductor portion 13a made of the valve metal and the surface of the valve metal. And a compensation wiring insulating film 13b formed by anodizing the substrate. The compensation wiring conductor portion 13a is formed integrally with the wiring conductor portion 12a and is electrically connected to each other. The compensation wiring conductor portion 13a is removed in a step after the formation of the insulating film.

電源接続部14は、図示しない直流電源の陽極が接続され、直流電源からの電荷を複数の配線12にそれぞれ供給するようになっている。   The power supply connection unit 14 is connected to an anode of a DC power supply (not shown), and supplies charges from the DC power supply to the plurality of wirings 12.

以上の構成により、本実施の形態における回路基板10では、複数の配線12のいずれかの特定箇所に断線が生じている場合でも、電源接続部14から供給される電荷が補償配線13を含む経路を介して断線箇所より先に供給されるので、複数の配線12のいずれにおいても陽極酸化が適切に進行し、配線絶縁膜12bを確実に形成することができる。したがって、本実施の形態における回路基板10を用いることにより、配線絶縁膜12bを含む薄膜デバイスを複数の配線12上に形成することができ、ディスプレイの背面基板としての製造歩留を向上させることができる。   With the above configuration, in the circuit board 10 according to the present exemplary embodiment, even when a disconnection occurs in any specific part of the plurality of wirings 12, a path in which the charge supplied from the power supply connection unit 14 includes the compensation wiring 13. Thus, the anodic oxidation proceeds appropriately in any of the plurality of wirings 12, and the wiring insulating film 12b can be reliably formed. Therefore, by using the circuit board 10 in this embodiment, a thin film device including the wiring insulating film 12b can be formed on the plurality of wirings 12, and the manufacturing yield as a back substrate of the display can be improved. it can.

具体的には、図1に示すC部に断線が生じている場合、従来のものでは、電源接続部14から供給される電荷がD部まで届かず、C部からD部までの間の配線12に絶縁膜が形成されないので、C部より先の画素形成領域15a及び15bに係る薄膜デバイスの形成ができなかった。例えば、配線導体部12aを一方の電極として薄膜コンデンサを形成する場合、絶縁膜が形成されていない状態で他方の電極を形成すると、2つの電極が短絡してしまい、修繕ができない不良となってしまう。   Specifically, when the disconnection occurs in the C portion shown in FIG. 1, in the conventional device, the charge supplied from the power supply connection portion 14 does not reach the D portion, and the wiring between the C portion and the D portion Since no insulating film was formed on the thin film device 12, the thin film device related to the pixel formation regions 15 a and 15 b ahead of the C portion could not be formed. For example, when a thin film capacitor is formed using the wiring conductor portion 12a as one electrode, if the other electrode is formed without an insulating film, the two electrodes are short-circuited, resulting in a defect that cannot be repaired. End up.

これに対し、本実施の形態における回路基板10では、複数の補償配線13を設ける構成としたので、C部に断線が生じている場合でも補償配線13を含む経路を介して電源接続部14からの電荷をD部まで供給することができ、画素形成領域15a及び15bに係る薄膜デバイスを形成することができる。   On the other hand, since the circuit board 10 according to the present embodiment has a configuration in which a plurality of compensation wirings 13 are provided, even when a disconnection occurs in the C part, the power supply connection part 14 is connected via a path including the compensation wiring 13. Can be supplied to the D portion, and the thin film device according to the pixel formation regions 15a and 15b can be formed.

なお、配線12に断線箇所がある場合は、配線絶縁膜12b形成した後の工程で断線箇所を修繕することにより、電源接続部14から見て断線箇所より先にある領域に形成された薄膜デバイスを正常に機能させることができる。   In addition, when there exists a disconnection location in the wiring 12, the thin film device formed in the area | region ahead of the disconnection location seeing from the power supply connection part 14 by repairing a disconnection location in the process after forming the wiring insulating film 12b. Can function normally.

次に、本実施の形態における回路基板10の製造方法について図2を用いて説明する。なお、図2に示した各断面図において配線12の本数を3つとしている。また、以下に示す製造方法における材質、寸法、手法等は一例であり、本発明はこれらに限定されるものではない。   Next, the manufacturing method of the circuit board 10 in this Embodiment is demonstrated using FIG. In each cross-sectional view shown in FIG. 2, the number of wirings 12 is three. In addition, materials, dimensions, methods, and the like in the manufacturing method described below are examples, and the present invention is not limited to these.

まず、厚さが100μm〜200μm程度のプラスチックフィルムの基板11上に、室温でスパッタリング法を用いて、金属薄膜21を200nm〜400nm程度の厚さで形成する(図2(a))。金属薄膜21の材料としては、バルブ金属と呼ばれるものを用いるのが好ましく、アルミニウム、タンタル、ニオブ、チタン、ハフニウム、ジルコニウム、亜鉛、タングステン、ビスマス、アンチモン等が好ましい。なお、金属薄膜21を成膜する前に、基板11との密着性を向上させるため、例えばシリコン系の酸化膜又は窒化膜等を基板11上に堆積させておく工程を設けてもよい。   First, the metal thin film 21 is formed with a thickness of about 200 nm to 400 nm on a plastic film substrate 11 having a thickness of about 100 μm to 200 μm by sputtering at room temperature (FIG. 2A). As the material of the metal thin film 21, what is called a valve metal is preferably used, and aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, antimony, and the like are preferable. Before the metal thin film 21 is formed, a step of depositing, for example, a silicon-based oxide film or nitride film on the substrate 11 may be provided in order to improve adhesion with the substrate 11.

次に、フォトリソグラフィ法と、ドライエッチング法又はウエットエッチング法とを用いて、所定の配線パターンを形成する(図2(b1)、(b2))。例えば、ドライエッチング法を用いる場合は、六フッ化硫黄のガスによる反応性エッチング法を利用して配線パターンを形成することができる。この工程により、配線12及び補償配線13のそれぞれの導体部に相当する配線導体部12a及び補償配線導体部13aが基板11上に形成される。なお、この工程において、電源接続部14(図1(a)参照)も基板11上に形成する。   Next, a predetermined wiring pattern is formed by using a photolithography method and a dry etching method or a wet etching method (FIGS. 2B1 and 2B2). For example, when the dry etching method is used, the wiring pattern can be formed by using a reactive etching method using sulfur hexafluoride gas. Through this step, the wiring conductor portion 12 a and the compensation wiring conductor portion 13 a corresponding to the respective conductor portions of the wiring 12 and the compensation wiring 13 are formed on the substrate 11. In this step, the power supply connection portion 14 (see FIG. 1A) is also formed on the substrate 11.

続いて、室温で陽極酸化処理を行う(図2(c))。具体的には、電源接続部14を電源22の陽極に、陰極板23を電源22の陰極にそれぞれ接続し、電解液24中に浸して室温で通電処理を行う。陰極板23としては例えば白金、電解液24としては、金属薄膜21にタンタルを用いた場合には例えばホウ酸アンモニウムを用いるのが好ましい。通電処理における電流密度は、1mA/cm程度が好ましい。絶縁層を所定の厚さ、例えば100nm〜200nm程度で形成した後、通電処理を終了する。陽極酸化後は基板11を純水で充分洗浄して乾燥させる。 Subsequently, anodization is performed at room temperature (FIG. 2C). Specifically, the power supply connection unit 14 is connected to the anode of the power supply 22, and the cathode plate 23 is connected to the cathode of the power supply 22. For example, platinum is preferably used as the cathode plate 23, and ammonium borate is preferably used as the electrolyte solution 24, for example, when tantalum is used for the metal thin film 21. The current density in the energization process is preferably about 1 mA / cm 2 . After the insulating layer is formed with a predetermined thickness, for example, about 100 nm to 200 nm, the energization process is terminated. After the anodic oxidation, the substrate 11 is sufficiently washed with pure water and dried.

この陽極酸化処理により、配線導体部12a及び補償配線導体部13aをそれぞれ被覆する配線絶縁膜12b及び補償配線絶縁膜13bが形成される。陽極酸化処理では、反応過程における絶縁膜の薄い部分に電界が集中する自己整合作用によって、より均一な膜厚の絶縁膜を形成することができるので、スパッタ法や蒸着法、CVD法等よりもピンホールの少ない緻密で耐圧の優れた薄膜が得られる。   By this anodizing treatment, a wiring insulating film 12b and a compensation wiring insulating film 13b are formed to cover the wiring conductor portion 12a and the compensation wiring conductor portion 13a, respectively. In the anodizing process, an insulating film with a more uniform film thickness can be formed by the self-aligning action in which the electric field concentrates on the thin part of the insulating film in the reaction process. A dense thin film with few pinholes and excellent pressure resistance can be obtained.

次に、フォトリソグラフィ法と、ドライエッチング法又はウエットエッチング法とを用いて電気配線を加工し(図2(d1)、(d2))、補償配線13を除去する(図2(e1)、(e2))。例えば、ドライエッチング法を用いる場合は、例えば、四フッ化炭素による反応性エッチング法を利用して補償配線13を除去することができる。補償配線13を除去する工程の後、配線導体部12a及び配線絶縁膜12bは、補償配線13が除去された痕跡を有することとなる。なお、図2(e2)は、補償配線13の全体を除去して隣接する配線導体部12a同士の接続を断つ例を示しているが、1つの補償配線13の一部を除去して隣接する配線導体部12a同士の接続を断つ工程としてもよい。   Next, the electrical wiring is processed using a photolithography method and a dry etching method or a wet etching method (FIG. 2 (d1), (d2)), and the compensation wiring 13 is removed (FIG. 2 (e1), ( e2)). For example, when the dry etching method is used, the compensation wiring 13 can be removed using a reactive etching method using carbon tetrafluoride, for example. After the step of removing the compensation wiring 13, the wiring conductor portion 12 a and the wiring insulating film 12 b have traces from which the compensation wiring 13 has been removed. FIG. 2 (e2) shows an example in which the entire compensation wiring 13 is removed and the connection between the adjacent wiring conductor portions 12a is disconnected, but a part of one compensation wiring 13 is removed and adjacent. It is good also as a process of cutting off connection between wiring conductor parts 12a.

次に、本実施の形態における具体的な実施例について説明する。なお、以下に記載した材料や製造方法等は一例であり、本発明は、これらに限定されるものではない。   Next, specific examples in the present embodiment will be described. In addition, the material, the manufacturing method, etc. which were described below are examples, and this invention is not limited to these.

(第1の実施例)
まず、回路基板10上に薄膜デバイスとして薄膜コンデンサ及び薄膜トランジスタを回路基板10上に形成する場合の実施例について図3を用いて説明する。
(First embodiment)
First, an embodiment in which a thin film capacitor and a thin film transistor are formed on a circuit board 10 as a thin film device on the circuit board 10 will be described with reference to FIG.

図3(a)に示すように、薄膜コンデンサ30は、配線導体部12aを1つの電極とし、誘電体である配線絶縁膜12bを挟んで配線導体部12aに対向する対向電極31を備えている。対向電極31の対向面の大きさは、5μm〜100μm角程度とするのが好ましい。また、対向電極31は、クロムやチタン等の超薄膜(1nm〜5nm程度の膜厚)と金(50nm〜100nm程度の膜厚)との積層構造とするのが好ましい。   As shown in FIG. 3A, the thin film capacitor 30 includes a wiring conductor portion 12a as one electrode and a counter electrode 31 facing the wiring conductor portion 12a with a wiring insulating film 12b as a dielectric interposed therebetween. . The size of the facing surface of the counter electrode 31 is preferably about 5 μm to 100 μm square. The counter electrode 31 preferably has a laminated structure of an ultrathin film (thickness of about 1 nm to 5 nm) such as chromium or titanium and gold (thickness of about 50 nm to 100 nm).

この構成において、陽極酸化後に補償配線13を除去した後、対向電極31を新たな配線で所望に接続することにより、回路基板10には平行平板型の薄膜コンデンサ30をマトリクス状に容易に形成することができる。この薄膜コンデンサ30は、例えば、プラスチックフィルム上に形成された集積回路用のコンデンサとして利用できる。   In this configuration, after the compensation wiring 13 is removed after the anodic oxidation, the counter electrode 31 is connected as desired with a new wiring, whereby the parallel plate type thin film capacitors 30 are easily formed in a matrix on the circuit board 10. be able to. The thin film capacitor 30 can be used as, for example, a capacitor for an integrated circuit formed on a plastic film.

また、図3(b)に示すように、薄膜トランジスタ40は、配線導体部12aをゲート電極とし、配線絶縁膜12b上に形成されたソース電極41及びドレイン電極42と、有機半導体43とを備えている。ソース電極41とドレイン電極42との間隔は、1μm〜10μm程度とするのが好ましい。また、ソース電極41及びドレイン電極42の大きさは、それぞれ、幅を5μm〜10μm程度、長さを10μm〜500μm程度とするのが好ましい。また、ソース電極41及びドレイン電極42は、それぞれ、クロムやチタン等の超薄膜(1nm〜5nm程度の膜厚)と金(50nm〜100nm程度の膜厚)との積層構造とするのが好ましい。また、有機半導体43としては、例えばペンタセンを成膜して形成することができ、その膜厚は50nm〜100nm程度とするのが好ましい。   As shown in FIG. 3B, the thin film transistor 40 includes a source electrode 41 and a drain electrode 42 formed on the wiring insulating film 12b, and an organic semiconductor 43, with the wiring conductor portion 12a as a gate electrode. Yes. The distance between the source electrode 41 and the drain electrode 42 is preferably about 1 μm to 10 μm. The source electrode 41 and the drain electrode 42 preferably have a width of about 5 μm to 10 μm and a length of about 10 μm to 500 μm, respectively. Each of the source electrode 41 and the drain electrode 42 preferably has a laminated structure of an ultrathin film (film thickness of about 1 nm to 5 nm) and gold (film thickness of about 50 nm to 100 nm) such as chromium and titanium. The organic semiconductor 43 can be formed, for example, by forming a film of pentacene, and the film thickness is preferably about 50 nm to 100 nm.

この構成において、陽極酸化後に補償配線13を除去した後、回路基板10には電界効果型の薄膜トランジスタ40を容易に形成することができる。また、ソース電極41及びドレイン電極42をそれぞれ新たな配線で所望に接続することにより、マトリクス状に有機薄膜トランジスタアレイを形成することができる。この有機薄膜トランジスタアレイは、例えば、プラスチックフィルム上に形成される薄型ディスプレイ等の駆動素子として利用できる。   In this configuration, the field effect thin film transistor 40 can be easily formed on the circuit board 10 after the compensation wiring 13 is removed after the anodic oxidation. Further, the organic thin film transistor array can be formed in a matrix by connecting the source electrode 41 and the drain electrode 42 as desired with new wirings. This organic thin film transistor array can be used as a driving element for a thin display formed on a plastic film, for example.

(第2の実施例)
次に、前述の薄膜コンデンサ30及び薄膜トランジスタ40を基板11上に形成し、有機EL(エレクトロルミネッセンス)ディスプレイとして構成した実施例を図4に基づいて説明する。図4(a)は、本実施例における回路基板20の概念平面図であって陽極酸化処理後の構成を示しており、図4(b)は、図4(a)に示したE部の拡大概念図である。なお、図4において、図1及び図3における構成要素と同様なものには同一の符号を付している。
(Second embodiment)
Next, an embodiment in which the thin film capacitor 30 and the thin film transistor 40 described above are formed on the substrate 11 and configured as an organic EL (electroluminescence) display will be described with reference to FIG. FIG. 4A is a conceptual plan view of the circuit board 20 in the present embodiment and shows a configuration after anodizing treatment, and FIG. 4B is a diagram of the E portion shown in FIG. It is an expansion conceptual diagram. In FIG. 4, the same components as those in FIGS. 1 and 3 are denoted by the same reference numerals.

本実施例における回路基板20は、画素形成領域15毎に、1つの薄膜コンデンサ30と、2つの薄膜トランジスタ40a及び40bとを備えたものである。以下、製造方法の概要を説明する。   The circuit board 20 in the present embodiment includes one thin film capacitor 30 and two thin film transistors 40a and 40b for each pixel formation region 15. Hereinafter, an outline of the manufacturing method will be described.

まず、図4(a)に示すように、薄膜コンデンサ信号線(以下「TFC信号線」という。)16と、薄膜トランジスタ信号線(以下「TFT信号線」という。)17とを基板11上に設ける。また、陽極酸化処理を行う際に直流電源が接続される電源接続部14も基板11上に形成する。   First, as shown in FIG. 4A, a thin film capacitor signal line (hereinafter referred to as “TFC signal line”) 16 and a thin film transistor signal line (hereinafter referred to as “TFT signal line”) 17 are provided on the substrate 11. . In addition, a power connection portion 14 to which a direct current power source is connected when anodizing is performed is also formed on the substrate 11.

ここで、TFC信号線16は、薄膜コンデンサ30の一方の電極(図3(a)の符号12a相当)が形成されるパターン16aを含む。また、TFT信号線17は、薄膜トランジスタ40a及び40bの各ゲート電極(図3(b)の符号12a相当)がそれぞれ形成されるパターン17a及び17bを含む。また、TFC信号線16とTFT信号線17との間は、補償配線13によって接続されている。なお、TFC信号線16及びTFT信号線17は、図1における配線12に相当するものである。   Here, the TFC signal line 16 includes a pattern 16a in which one electrode of the thin film capacitor 30 (corresponding to reference numeral 12a in FIG. 3A) is formed. The TFT signal line 17 includes patterns 17a and 17b in which the gate electrodes (corresponding to reference numeral 12a in FIG. 3B) of the thin film transistors 40a and 40b are formed, respectively. The TFC signal line 16 and the TFT signal line 17 are connected by a compensation wiring 13. The TFC signal line 16 and the TFT signal line 17 correspond to the wiring 12 in FIG.

次に、図示しない電源を電源接続部14に接続して回路基板20の陽極酸化処理を行い、各信号線及び各パターンに絶縁膜を形成する。   Next, a power supply (not shown) is connected to the power supply connecting portion 14 to perform anodizing treatment of the circuit board 20 to form an insulating film on each signal line and each pattern.

次に、図4(b)に示すように、補償配線13の「×」印の部分において、TFC信号線16とTFT信号線17とを分断する。また、薄膜トランジスタ40bのゲート電極が形成されるパターン17bと、TFT信号線17とを「×」印で示した分断箇所17cにおいて分断する。なお、分断される前の分断箇所17c位置に存在した導体部は、本発明に係る電気的接続手段を構成する。すなわち、本発明に係る電気的接続手段は、線状に形成された配線同士を接続するものに限定されるものではなく、電子素子の電極が形成される電極形成導体部(例えばパターン17b)と線状の配線(例えばTFT信号線17)とを接続するもの、電極形成導体部同士を接続するもの、電極が形成されない導体部同士を接続するもの等も含むものである。   Next, as shown in FIG. 4B, the TFC signal line 16 and the TFT signal line 17 are divided at the portion of the compensation wiring 13 marked with “×”. Further, the pattern 17b in which the gate electrode of the thin film transistor 40b is formed and the TFT signal line 17 are divided at a dividing portion 17c indicated by “x”. In addition, the conductor part which existed in the part 17c position before parting comprises the electrical connection means which concerns on this invention. In other words, the electrical connecting means according to the present invention is not limited to connecting the wirings formed in a linear shape, but an electrode forming conductor portion (for example, pattern 17b) on which an electrode of an electronic element is formed. Examples include those that connect linear wiring (for example, the TFT signal line 17), those that connect the electrode forming conductors, and those that connect the conductors where no electrode is formed.

続いて、画素形成領域15に発光素子のための画素電極を形成した後、薄膜デバイス及び各信号線を形成する。具体的には、薄膜コンデンサ30の上側電極をパターン16a上に形成する(図3(a)参照)。また、薄膜トランジスタ40a及び40bをパターン17a及び17b上にそれぞれ形成する(図3(b)参照)。ここで、薄膜トランジスタ40aのソース電極(図3(b)の符号41相当)は、各画素にデータを伝送する画素データ線18の形成と兼用して同時に製作することができる。また、薄膜トランジスタ40aのドレイン電極(図3(b)の符号42相当)は、電源供給線19と接続する。   Subsequently, after forming a pixel electrode for the light emitting element in the pixel forming region 15, a thin film device and each signal line are formed. Specifically, the upper electrode of the thin film capacitor 30 is formed on the pattern 16a (see FIG. 3A). Thin film transistors 40a and 40b are formed on the patterns 17a and 17b, respectively (see FIG. 3B). Here, the source electrode (corresponding to the reference numeral 41 in FIG. 3B) of the thin film transistor 40a can be simultaneously manufactured in combination with the formation of the pixel data line 18 for transmitting data to each pixel. The drain electrode of the thin film transistor 40a (corresponding to reference numeral 42 in FIG. 3B) is connected to the power supply line 19.

以上のように、本実施の形態における回路基板10によれば、複数の配線12の間を接続する複数の補償配線13を設ける構成としたので、配線12の特定箇所に断線が生じている場合でも、電源接続部14から供給される電荷が補償配線13を含む経路を介して断線箇所より先に供給されるため、配線絶縁膜12bを複数の配線12に確実に形成することができる。   As described above, according to the circuit board 10 in the present embodiment, since the plurality of compensation wirings 13 that connect the plurality of wirings 12 are provided, a disconnection occurs at a specific portion of the wiring 12. However, since the charge supplied from the power supply connection portion 14 is supplied before the disconnection portion via the path including the compensation wiring 13, the wiring insulating film 12 b can be reliably formed on the plurality of wirings 12.

したがって、本実施の形態における回路基板10は、配線絶縁膜12b含む薄膜デバイスを複数の配線12上に形成することができ、例えばディスプレイの背面基板として適用される際にその製造歩留を向上させることができる。この製造歩留は補償配線13の本数が増加するほど向上し、好ましい構成となる。   Therefore, the circuit board 10 in the present embodiment can form a thin film device including the wiring insulating film 12b on the plurality of wirings 12, and improves the manufacturing yield when applied as a back substrate of a display, for example. be able to. This manufacturing yield improves as the number of the compensation wirings 13 increases and becomes a preferable configuration.

また、本実施の形態における回路基板10によれば、陽極酸化処理を用いて室温で絶縁膜を形成する構成としたので、例えばプラスチックフィルムのような柔軟性を有する基板に対しても絶縁膜を確実に形成することができる。   In addition, according to the circuit board 10 in the present embodiment, since the insulating film is formed at room temperature using anodizing treatment, the insulating film is also applied to a flexible substrate such as a plastic film. It can be reliably formed.

なお、前述の実施の形態において、配線12と補償配線13とをバルブ金属で一体に形成する構成を例に挙げて説明したが、本発明はこれに限定されるものではなく、例えば、配線12と補償配線13とを互いに異なる金属で別個に形成して電気的に接続する構成としても同様な効果が得られる。   In the above-described embodiment, the configuration in which the wiring 12 and the compensation wiring 13 are integrally formed of a valve metal has been described as an example. However, the present invention is not limited to this. For example, the wiring 12 The same effect can be obtained by a configuration in which the compensation wiring 13 and the compensation wiring 13 are separately formed of different metals and electrically connected.

以上のように、本発明に係る回路基板及び電子素子の製造方法並びに回路基板は、配線に断線箇所がある場合でも絶縁膜を確実に形成することができるという効果を有し、プラスチックフィルム上に形成される薄型ディスプレイの背面基板、集積回路用の電子素子、アクティブマトリクス方式を用いたディスプレイの駆動素子等として有用である。   As described above, the circuit board and the method for manufacturing an electronic element and the circuit board according to the present invention have an effect that an insulating film can be surely formed even when there is a disconnection portion in the wiring, and on the plastic film. It is useful as a back substrate of a thin display to be formed, an electronic element for an integrated circuit, a driving element for a display using an active matrix system, and the like.

本発明の一実施の形態における回路基板の構成を示す概念図 (a)回路基板の平面概念図 (b)回路基板の断面概念図(断面AA) (c)回路基板の断面概念図(断面BB)1 is a conceptual diagram showing a configuration of a circuit board according to an embodiment of the present invention. (A) A conceptual plan view of a circuit board. (B) A schematic sectional view of a circuit board (cross section AA). ) 本発明の一実施の形態における回路基板の製造工程を示す図 (a)基板上に金属薄膜を形成した状態を示す図 (b1)基板上に所定の配線パターンを形成した状態を示す図(断面AA) (b2)基板上に所定の配線パターンを形成した状態を示す図(断面BB) (c)陽極酸化処理の説明図 (d1)ドライエッチング法により電気配線を加工する状態を示す図(断面AA) (d2)ドライエッチング法により電気配線を加工する状態を示す図(断面BB) (e1)補償配線を除去した状態を示す図(断面AA) (e2)補償配線を除去した状態を示す図(断面BB)The figure which shows the manufacturing process of the circuit board in one embodiment of this invention (a) The figure which shows the state which formed the metal thin film on the board | substrate (b1) The figure which shows the state which formed the predetermined wiring pattern on the board | substrate (cross section AA) (b2) A diagram showing a state in which a predetermined wiring pattern is formed on a substrate (cross section BB) (c) An explanatory diagram of anodizing treatment (d1) A diagram showing a state in which electrical wiring is processed by a dry etching method (cross section) (A2) (d2) A diagram showing a state where electrical wiring is processed by a dry etching method (cross section BB) (e1) A diagram showing a state where compensation wiring is removed (cross section AA) (e2) A diagram showing a state where compensation wiring is removed (Cross section BB) 本発明の一実施の形態の第1の実施例における回路基板上に形成した薄膜デバイスを示す概念図 (a)薄膜コンデンサを示す断面概念図 (b)薄膜トランジスタを示す断面概念図The conceptual diagram which shows the thin film device formed on the circuit board in 1st Example of one embodiment of this invention (a) The cross-sectional conceptual diagram which shows a thin film capacitor (b) The cross-sectional conceptual diagram which shows a thin-film transistor 本発明の一実施の形態の第2の実施例における回路基板上に形成した薄膜コンデンサ及び薄膜トランジスタを示す図 (a)回路基板の平面概念図 (b)E部の拡大概念図The figure which shows the thin film capacitor and thin film transistor which were formed on the circuit board in 2nd Example of one embodiment of this invention. (A) The plane conceptual diagram of a circuit board (b) The expansion conceptual diagram of the E section

符号の説明Explanation of symbols

10、20 回路基板
11 基板
12 配線
12a 配線導体部
12b 配線絶縁膜
12c、12d 配線
13 補償配線(電気的接続手段)
13a 補償配線導体部
13b 補償配線絶縁膜
13c、13d 補償配線
14 電源接続部
15(15a、15b) 画素形成領域
16 TFC信号線
16a 薄膜コンデンサの一方の電極が形成されるパターン
17 TFT信号線
17a、17b ゲート電極が形成されるパターン
17c TFT信号線の分断箇所
18 画素データ線
19 電源供給線
21 金属薄膜
22 電源
23 陰極板
24 電解液
30 薄膜コンデンサ
31 対向電極
40 薄膜トランジスタ
41 ソース電極
42 ドレイン電極
43 有機半導体
10, 20 Circuit board 11 Substrate 12 Wiring 12a Wiring conductor 12b Wiring insulation film 12c, 12d Wiring 13 Compensation wiring (electrical connection means)
13a Compensation wiring conductor part 13b Compensation wiring insulation film 13c, 13d Compensation wiring 14 Power supply connection part 15 (15a, 15b) Pixel formation region 16 TFC signal line 16a Pattern in which one electrode of thin film capacitor is formed 17 TFT signal line 17a, 17b Pattern in which gate electrode is formed 17c TFT signal line segmentation point 18 Pixel data line 19 Power supply line 21 Metal thin film 22 Power supply 23 Cathode plate 24 Electrolyte 30 Thin film capacitor 31 Counter electrode 40 Thin film transistor 41 Source electrode 42 Drain electrode 43 Organic semiconductor

Claims (3)

基板上に複数の配線を形成する工程と、前記複数の配線の予め定められた箇所同士を電気的に接続する電気的接続手段を形成する工程と、前記複数の配線のそれぞれに絶縁膜を電気的に形成する工程と、前記電気的接続手段を除去する工程とを含むことを特徴とする回路基板の製造方法。 Forming a plurality of wirings on the substrate; forming an electrical connection means for electrically connecting predetermined portions of the plurality of wirings; and electrically connecting an insulating film to each of the plurality of wirings. Forming a circuit board and removing the electrical connection means. A method of manufacturing a circuit board, comprising: 請求項1に記載の前記基板上に電子素子を形成する電子素子の製造方法であって、
前記絶縁膜上に電極を形成する工程を含むことを特徴とする電子素子の製造方法。
An electronic device manufacturing method for forming an electronic device on the substrate according to claim 1,
The manufacturing method of the electronic element characterized by including the process of forming an electrode on the said insulating film.
請求項1に記載の回路基板の製造方法で製造される回路基板であって、
前記電気的接続手段が除去された痕跡を有することを特徴とする回路基板。
A circuit board manufactured by the method for manufacturing a circuit board according to claim 1,
A circuit board having a trace from which the electrical connection means has been removed.
JP2008017565A 2008-01-29 2008-01-29 Electronic device manufacturing method and circuit board Expired - Fee Related JP5044427B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008017565A JP5044427B2 (en) 2008-01-29 2008-01-29 Electronic device manufacturing method and circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008017565A JP5044427B2 (en) 2008-01-29 2008-01-29 Electronic device manufacturing method and circuit board

Publications (2)

Publication Number Publication Date
JP2009182015A true JP2009182015A (en) 2009-08-13
JP5044427B2 JP5044427B2 (en) 2012-10-10

Family

ID=41035780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008017565A Expired - Fee Related JP5044427B2 (en) 2008-01-29 2008-01-29 Electronic device manufacturing method and circuit board

Country Status (1)

Country Link
JP (1) JP5044427B2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503279A (en) * 1973-05-11 1975-01-14
JPH0629279A (en) * 1992-05-09 1994-02-04 Semiconductor Energy Lab Co Ltd Electronic circuit and manufacture thereof
JPH08264799A (en) * 1995-03-24 1996-10-11 Semiconductor Energy Lab Co Ltd Forming method of semiconductor integrated circuit
JPH09318973A (en) * 1996-05-28 1997-12-12 Matsushita Electric Ind Co Ltd Thin-film transistor array and its production
JPH10233568A (en) * 1997-02-20 1998-09-02 Sony Corp Manufacturing method of printed wiring board, and jig for plating used therefor
JP2003215616A (en) * 2002-01-21 2003-07-30 Matsushita Electric Ind Co Ltd Method for manufacturing electrode or wiring, and method for manufacturing active matrix type liquid crystal display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503279A (en) * 1973-05-11 1975-01-14
JPH0629279A (en) * 1992-05-09 1994-02-04 Semiconductor Energy Lab Co Ltd Electronic circuit and manufacture thereof
JPH08264799A (en) * 1995-03-24 1996-10-11 Semiconductor Energy Lab Co Ltd Forming method of semiconductor integrated circuit
JPH09318973A (en) * 1996-05-28 1997-12-12 Matsushita Electric Ind Co Ltd Thin-film transistor array and its production
JPH10233568A (en) * 1997-02-20 1998-09-02 Sony Corp Manufacturing method of printed wiring board, and jig for plating used therefor
JP2003215616A (en) * 2002-01-21 2003-07-30 Matsushita Electric Ind Co Ltd Method for manufacturing electrode or wiring, and method for manufacturing active matrix type liquid crystal display device

Also Published As

Publication number Publication date
JP5044427B2 (en) 2012-10-10

Similar Documents

Publication Publication Date Title
KR20240049788A (en) Organic light emitting display and manufacturing method thereof
US10186562B2 (en) Thin film transistor and manufacturing method thereof, array substrate and organic light emitting display panel
US20220140046A1 (en) Display panel and fabrication method thereof
EP2475009B1 (en) Method of manufacturing an organic light emitting display device
JP2010040897A (en) Organic thin film transistor, production method thereof, and electronic device
JP6519073B2 (en) THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE
US20120280229A1 (en) Flexible semiconductor device, method for manufacturing the same and image display device
JP2007193313A (en) Organic light emitting display and method of fabricating the same
CN101569001B (en) Method for manufacturing flexible semiconductor device and flexible semiconductor device
WO2010058541A1 (en) Flexible semiconductor device and method for manufacturing same
JP2006146205A (en) Flat panel display and its method of fabrication
JP2005268099A (en) Organic el display panel, organic el display device, and method of manufacturing organic el display panel
CN102812541A (en) Flexible semiconductor device and method for producing same, image display device using the flexible semiconductor device and manufacturing method thereof
WO2019012769A1 (en) Display device and method for producing display device
CN106384740A (en) Frameless display device and preparation method therefor
US10204922B2 (en) Thin film transistor, array substrate and manufacturing method thereof, and display device
US10403694B2 (en) OLED substrate comprising corresponding pixel definition layer patterns, manufacturing method thereof, and display device
US20120176299A1 (en) Organic light emitting diode display
JP2016111105A (en) Thin film transistor, manufacturing method thereof, and display device
CN107591416B (en) Array substrate and manufacturing method thereof
US8993387B2 (en) Flexible semiconductor device, method for manufacturing the same, image display device using the same and method for manufacturing the image display device
US20150206982A1 (en) Thin film transistor for a display device, display device and method of manufacturing a display device
US9401394B2 (en) Method of manufacturing display apparatus
CN107680992B (en) Display device, manufacturing method thereof and repairing method of display device
WO2015086621A1 (en) Source/drain conductors for transistor devices

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100310

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120412

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120508

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120530

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120619

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120713

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150720

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees