JPH0629234A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0629234A
JPH0629234A JP18206392A JP18206392A JPH0629234A JP H0629234 A JPH0629234 A JP H0629234A JP 18206392 A JP18206392 A JP 18206392A JP 18206392 A JP18206392 A JP 18206392A JP H0629234 A JPH0629234 A JP H0629234A
Authority
JP
Japan
Prior art keywords
substrate
temperature
processed
molecular
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP18206392A
Other languages
Japanese (ja)
Inventor
Yasuhiro Endo
康浩 遠藤
Eizo Miyauchi
榮三 宮内
Takao Taguchi
孝雄 田口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18206392A priority Critical patent/JPH0629234A/en
Publication of JPH0629234A publication Critical patent/JPH0629234A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To achieve that impurities are hard to be left on a treated surface, that the treated surface is hard to damage, that the impurities are hard to diffuse and that an element characteristic is hard to deteriorate by a method wherein the following are executed simultaneously or alternately: a process wherein a substrate to be treated is heated for a short time by a rapid thermal annealing method; and a process wherein the beam of the constituent substance of the substrate to be treated is irradiated. CONSTITUTION:A substrate holder 11 has a shape which sandwiches edges of a substrate 12 in such a way that the surface on the side of an element formation region on the substrate 12 and the rear on its opposite side are not covered; the substrate 12 is arranged in such a way that its surface is faced downward; an infrared lamp 13 which can irradiate the rear is provided. Three X three pieces of molecular-beam cells 14 are arranged in a direction perpendicular to the surface of the substrate 12; the surface of the substrate 12 can be irradiated uniformly with molecular beams. The molecular beams are charged with high-purity Si. The Gi substrate 12 is moved between the infrared lamp 13 and the molecular-beam cells 14; its surface temperature is held at about 300 deg.C by the infrared lamp 13; the temperature of the molecular-beam cells 14 is raised to about 1400 deg.C; the temperature of the substrate 12 is raised and it is lowered immediately after the molecular beams have been irradiated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、詳しくは、半導体結晶製造技術及び電子デバイ
ス製造プロセスに用いるシリコン等の基板の表面処理方
法に適用することができ、特に、被処理基板の自然酸化
膜を除去する際、処理表面に不純物残渣及びダメージ等
を生じ難くして素子特性の劣化を生じ難くすることがで
きる半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, it can be applied to a semiconductor crystal manufacturing technique and a surface treatment method for a substrate such as silicon used in an electronic device manufacturing process. The present invention relates to a method for manufacturing a semiconductor device, which can prevent impurity residues, damages, and the like from easily occurring on a processed surface when a natural oxide film on a substrate to be processed is removed, and prevent deterioration of element characteristics.

【0002】近年、256Mbや1GbクラスのDRA
M等のULSI集積回路の実現に向けて、その基礎技術
の開発研究が活発に行われている。そして、このクラス
の集積回路では、最小加工寸法ルールが 0.3μm以下と
極めて小さく、そのうえ各プロセスにおいては、低温化
とともに高品質化が要求されている。しかも、素子の高
集積化の要求に伴い、加工工程も大きく変わってきてい
る。
Recently, DRA of 256Mb or 1Gb class
In order to realize a ULSI integrated circuit such as M, the research and development of its basic technology are being actively conducted. In this class of integrated circuit, the minimum processing dimension rule is 0.3 μm or less, which is extremely small, and in addition, in each process, high quality as well as low temperature is required. Moreover, with the demand for higher integration of elements, the processing steps have changed significantly.

【0003】[0003]

【従来の技術】図7はシリコン表面の自然酸化膜がデバ
イス基本構造に与える悪影響を示す図である。図7
(a)に示すように、シリコン基板31表面に自然酸化膜
32が生じた状態でSiO2 絶縁膜33及びポリSi配線層
34を順次形成すると、SiO2 絶縁膜33及びポリSi配
線層34内にガス、不純物等が拡散してSiO2 絶縁膜33
及びポリSi配線層34の膜質が悪くなり、耐圧不良等が
生じ易くなる等素子特性が劣化し易くなる。
2. Description of the Related Art FIG. 7 is a diagram showing the adverse effect of a natural oxide film on the surface of silicon on the basic structure of a device. Figure 7
As shown in (a), a natural oxide film is formed on the surface of the silicon substrate 31.
SiO 2 insulating film 33 and poly-Si wiring layer with 32
When the 34 are sequentially formed, SiO 2 insulating film 33 gas SiO 2 insulating film 33 and the poly-Si wiring layer 34, impurities are diffused
In addition, the film quality of the poly-Si wiring layer 34 is deteriorated, and breakdown characteristics and the like are likely to occur, so that element characteristics are easily deteriorated.

【0004】また、図7(b)に示すように、シリコン
基板31表面に自然酸化膜32が生じた状態でSiO2 絶縁
膜33及びAl配線層34を順次形成すると、、SiO2
縁膜33及びAl配線層34内にガス、不純物等が拡散して
SiO2 絶縁膜33及びAl配線層34の膜質が悪くなり、
Al配線層34内に欠陥が誘起される等素子特性が劣化し
易くなる。
[0004] Figure 7 (b), the silicon substrate 31 surface in a natural state where the oxide film 32 is caused to sequentially formed SiO 2 insulating film 33 and the Al wiring layer 34 ,, SiO 2 insulating film 33 And gases, impurities, etc. diffuse into the Al wiring layer 34, and the film quality of the SiO 2 insulating film 33 and the Al wiring layer 34 deteriorates.
Element characteristics such as defects induced in the Al wiring layer 34 are likely to deteriorate.

【0005】また、図7(c)に示すように、SiO2
絶縁膜33に形成された開口部33a内のシリコン基板31表
面に自然酸化膜32が生じた状態でポリSi配線層34を形
成し、更にこのポリSi配線層34表面に自然酸化膜が生
じた状態でSiN絶縁膜35を形成すると、ポリSi配線
層34及びSiN絶縁膜35にガス、不純物等が拡散してポ
リSi配線層34及びSiN絶縁膜35の膜質が悪くなり、
シリコン基板31とポリSi配線層34とでコンタクト不良
が生じ易くなったり、キャパシタ容量が低下して不良が
生じ易くなったりして素子特性が劣化し易くなる。この
図7での問題は特に 0.3μmレベルのULSI集積回路
等のプロセスで顕著になる。
Further, as shown in FIG. 7 (c), SiO 2
A poly-Si wiring layer 34 is formed in a state where the natural oxide film 32 is formed on the surface of the silicon substrate 31 in the opening 33a formed in the insulating film 33, and a natural oxide film is further formed on the surface of the poly-Si wiring layer 34. If the SiN insulating film 35 is formed in this state, gas, impurities, etc. diffuse into the poly Si wiring layer 34 and the SiN insulating film 35, and the film quality of the poly Si wiring layer 34 and the SiN insulating film 35 deteriorates.
Contact characteristics are likely to occur between the silicon substrate 31 and the poly-Si wiring layer 34, or the capacitance of the capacitor is lowered to easily cause defects, resulting in deterioration of element characteristics. The problem shown in FIG. 7 becomes remarkable especially in the process of 0.3 μm level ULSI integrated circuits.

【0006】このように、自然酸化膜が生じた状態で次
層を成膜してしまうと素子特性が劣化してしまうので、
従来では、成膜する前に、アルゴンスパッタエッチング
や水素プラズマエッチング、あるいはフッ素ラジカルエ
ッチング等により表面処理して、自然酸化膜の汚れを除
去していた。
As described above, if the next layer is formed in the state where the natural oxide film is formed, the device characteristics will be deteriorated.
Conventionally, before forming a film, a surface treatment is performed by argon sputter etching, hydrogen plasma etching, fluorine radical etching, or the like to remove stains on the natural oxide film.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記し
た従来の半導体装置の製造方法では、アルゴンスパッタ
エッチングや水素プラズマエッチング、あるいはフッ素
ラジカルエッチング等により表面処理していたため、処
理表面に水素、フッ素等の不純物が残留し易く、不純物
が残留した状態で次層を成膜すると、成膜された膜内に
上記不純物が拡散してしまい、その結果、成膜された膜
の膜質が悪くなって素子特性が劣化し易いという問題が
あった。また、エッチングにより表面処理していたた
め、処理表面にダメージが入り易いという問題があっ
た。表面にダメージが入ると、表面モホロジーが悪くな
ったり、また下地に拡散層があるような場合、拡散層ま
でエッチングしてしまうことがあった。
However, in the above-described conventional method for manufacturing a semiconductor device, the surface treatment is performed by argon sputter etching, hydrogen plasma etching, fluorine radical etching, or the like. Impurities tend to remain, and if the next layer is formed with impurities remaining, the impurities will diffuse into the formed film, and as a result, the quality of the formed film will deteriorate and the device characteristics Has a problem that it is easily deteriorated. Further, since the surface treatment is performed by etching, there is a problem that the treated surface is easily damaged. If the surface is damaged, the surface morphology may be deteriorated, or if the underlying layer has a diffusion layer, the diffusion layer may be etched.

【0008】このため、処理表面に不純物が残留し、処
理表面にダメージが入ってしまうという問題を解消する
ために、従来では、シリコン被処理基板を加熱炉を用い
て約1000℃程度で高温加熱し、更にSiビームを十数秒
照射することによりSiO2自然酸化膜を除去する方法
が知られている。なお、シリコン基板に前処理を行わず
SiO2 自然酸化膜の除去を行う場合は、基板温度を約
1000℃にし、十数秒のSiビームを照射することにより
清浄な基板表面を得ることができる。
For this reason, in order to solve the problem that impurities remain on the treated surface and damage the treated surface, conventionally, the silicon substrate is heated at a high temperature of about 1000 ° C. using a heating furnace. Then, a method is known in which the SiO 2 natural oxide film is removed by irradiating with a Si beam for more than 10 seconds. When removing the SiO 2 natural oxide film without pretreatment on the silicon substrate, the substrate temperature should be about
A clean substrate surface can be obtained by setting the temperature to 1000 ° C. and irradiating the Si beam for 10 seconds or more.

【0009】しかしながら、この方法では、1000℃とい
う高温に基板温度を上げるのに、炉を用いて昇温してい
たため、昇温時間に長時間を要してしまう。このため、
この長時間における高温保持のために、素子形成領域の
拡散層等の不純物の拡散が生じてしまい、結局、上記し
たと同様不純物拡散に伴う素子特性が劣化してしまうと
いう問題があった。
However, in this method, since the temperature is raised in the furnace to raise the substrate temperature to a high temperature of 1000 ° C., it takes a long time to raise the temperature. For this reason,
Due to this high temperature holding for a long time, diffusion of impurities such as the diffusion layer in the element formation region occurs, and as a result, similar to the above, there is a problem that element characteristics are deteriorated due to impurity diffusion.

【0010】そこで、本発明では、被処理基板表面の自
然酸化膜を除去する際、処理表面に不純物残渣を生じ難
くすることができるとともに、処理表面にダメージを入
り難くすることができ、しかも不純物拡散を生じ難くす
ることができ、素子特性の劣化を生じ難くすることがで
きる半導体装置の製造方法を提供することを目的として
いる。
Therefore, according to the present invention, when the natural oxide film on the surface of the substrate to be processed is removed, it is possible to prevent impurities from remaining on the surface to be processed, and to prevent damage to the surface to be processed, and further It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent diffusion and prevent deterioration of element characteristics.

【0011】[0011]

【課題を解決するための手段】本発明による半導体装置
の製造方法は上記目的達成のため、被処理基板をRTA
(Rapid Thermal Annealing)法により短時間加熱する加
熱工程と、該被処理基板に該被処理基板の構成物質のビ
ームを照射するビーム照射工程とを同時に行うか、ある
いは交互に少なくとも1回ずつ行うことにより、該被処
理基板の表面処理を行う工程とを含むものである。
In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention uses an RTA for a substrate to be processed.
A heating step of heating for a short time by a (Rapid Thermal Annealing) method and a beam irradiation step of irradiating the substrate to be processed with a beam of a constituent material of the substrate to be processed are performed at the same time or alternately at least once. The step of performing a surface treatment on the substrate to be processed is included.

【0012】本発明に係る被処理基板には、Si、Ga
As、InP等の基板が挙げられ、これに対する被処理
基板の構成物質のビームにはSi、As、P等のビーム
が挙げられる。また、RTA法による加熱には、赤外線
照射加熱等が挙げられる。本発明においては、前記ビー
ム照射は、複数の分子線セルにより行われる場合が好ま
しく、この場合、被処理基板に対して適宜均等に分布よ
く分子線セルを配置することで単一の分子線セルで行う
場合よりも均等に分布よく被処理基板に照射することが
できる。
The substrate to be processed according to the present invention includes Si and Ga.
Substrates made of As, InP and the like can be cited, and the beams of the constituent material of the substrate to be treated therefor can be beams of Si, As, P and the like. In addition, examples of heating by the RTA method include infrared irradiation heating. In the present invention, the beam irradiation is preferably carried out by a plurality of molecular beam cells, in which case a single molecular beam cell can be obtained by arranging the molecular beam cells appropriately and evenly with respect to the substrate to be treated. It is possible to irradiate the substrate to be processed with a more even distribution than in the case of.

【0013】本発明においては、加熱工程とビーム照射
工程とを同時に行う際は、例えば赤外線照射線等の加熱
を被処理基板裏面(素子形成領域と反対側の面)から行
い、ビーム照射を被処理基板表面(素子形成領域側の
面)から行うようにすればよく、また、加熱工程とビー
ム照射工程とを交互に行う際は、例えば赤外線照射等の
加熱とビーム照射とを被処理基板表面から交互に行うよ
うにすればよい。前者の場合は、後者の場合よりも装置
システムを簡略化することができるとともに、容易に表
面処理することができる。後者の場合は、両工程を被処
理基板の表面側から行うことができるので、前者の場合
よりも基板表面温度のばらつきを少なくすることができ
る。
In the present invention, when the heating step and the beam irradiation step are performed at the same time, for example, infrared rays or the like are heated from the back surface of the substrate to be processed (the surface opposite to the element formation region) to perform the beam irradiation. The heating may be performed from the surface of the substrate to be processed (the surface on the side of the element formation region), and when the heating step and the beam irradiation step are alternately performed, heating such as infrared irradiation and beam irradiation are performed on the surface of the substrate to be processed. It should be done alternately from. In the former case, the device system can be simplified and the surface can be easily treated as compared with the latter case. In the latter case, both steps can be performed from the front surface side of the substrate to be processed, so that the variation in the substrate surface temperature can be made smaller than in the former case.

【0014】本発明においては、Al等の配線やSiO
2 等の絶縁膜等の成膜前の前処理に好ましく適用させる
ことができ、特に、CVDやスパッタ装置等、複数のチ
ャンバーを有するマルチチャンバー装置における前処理
工程に好ましく適用させることができる。
In the present invention, wiring such as Al and SiO
It can be preferably applied to a pretreatment before forming an insulating film such as 2 and the like, and particularly preferably to a pretreatment step in a multi-chamber apparatus having a plurality of chambers such as a CVD or sputtering apparatus.

【0015】[0015]

【作用】従来では、前述した如く、炉で基板温度を昇温
していたため、図1(a)に示す如く、目的の温度であ
る1000℃に達するまでに長時間を必要とし、実際には10
00℃という温度を十数秒だけあれば自然酸化膜が除去で
きるにもかかわらず、数分から数十分という長時間の高
温下に基板が曝されてしまうため、不純物の拡散やダメ
ージがおこり実用上問題があった。
Since the substrate temperature is conventionally raised in the furnace as described above, it takes a long time to reach the target temperature of 1000 ° C. as shown in FIG. Ten
Even if the natural oxide film can be removed by keeping the temperature of 00 ° C for only ten and a few seconds, the substrate is exposed to a high temperature for a long time of several minutes to several tens of minutes, which causes impurity diffusion and damage, and is practical. There was a problem.

【0016】これに対し、本発明では、RTA法を用い
るので、図1(b)に示す如く、1000℃まで昇温するの
に数秒程度あればよく、降温にも数秒から数十秒程度で
よいので、基板を高温に保っている時間は従来の炉を用
いる場合よりも極めて短くて済む。これは、不純物の拡
散による影響が現れる前にプロセスを終わらせることが
できるので、低温プロセスと等価的プロセスであるとい
える。このため、ダメージや不純物の拡散といった問題
は起こらない。
On the other hand, since the RTA method is used in the present invention, as shown in FIG. 1B, it takes only a few seconds to raise the temperature to 1000 ° C., and the temperature can be lowered in a few seconds to several tens of seconds. Because it is good, the time to keep the substrate at a high temperature is much shorter than that in the case of using a conventional furnace. This can be said to be an equivalent process to the low temperature process because the process can be terminated before the influence of the diffusion of impurities appears. Therefore, problems such as damage and diffusion of impurities do not occur.

【0017】このように、本発明では、基板をRTA法
を用いて短時間昇温することで基板表面の自然酸化膜を
除去し易い状態にし、この状態で基板の構成物質のSi
等のビームを照射することで自然酸化膜を物理的に除去
している。このように、基板の構成物質のビームを照射
しているため、処理表面に不純物残渣を生じ難くするこ
とができる。仮に、基板構成物質の原子(Si等)が処
理表面に残っても、従来のF等エッチングによる場合の
F等のような不純物ではないので、その後、成膜アニー
ル等の熱処理をしてもほとんど悪影響はない。そして、
昇温されて除去し易い状態になった自然酸化膜をビーム
照射によって除去しているため、従来のエッチングによ
る場合のような処理表面へのダメージを入り難くするこ
とができる。しかも、RTA法により短時間の基板昇温
で済ませることができるため、従来の炉による高温時間
による場合よりも生じ難くすることができる。
As described above, according to the present invention, the temperature of the substrate is raised for a short time by the RTA method so that the natural oxide film on the surface of the substrate can be easily removed.
The natural oxide film is physically removed by irradiating the same beam. As described above, since the beam of the constituent material of the substrate is irradiated, it is possible to prevent impurities residues from being easily generated on the treated surface. Even if the atoms (Si, etc.) of the substrate constituent substances remain on the processed surface, they are not impurities such as F in the case of conventional F etc. etching. There is no adverse effect. And
Since the natural oxide film, which has been heated and is in a state where it is easy to remove, is removed by beam irradiation, it is possible to prevent damage to the surface to be treated unlike in the case of conventional etching. Moreover, since the substrate temperature can be raised in a short time by the RTA method, it can be more difficult to occur than in the case of the high temperature time in the conventional furnace.

【0018】なお、基板をRTA法で短時間昇温しただ
けでは、自然酸化膜を除去することはできないことは言
うまでもない。また、基板にビーム照射しただけでは、
例えば常温でのSiビームだと、Siが堆積されるだけ
で自然酸化膜を除去することはできないのは言うまでも
ない。
Needless to say, the natural oxide film cannot be removed only by raising the temperature of the substrate by the RTA method for a short time. Also, if the substrate is irradiated with a beam,
For example, with a Si beam at room temperature, it goes without saying that the natural oxide film cannot be removed but only Si is deposited.

【0019】[0019]

【実施例】(実施例1)図2は本発明の実施例1に則し
たマルチチャンバー装置の構成を示す概略図である。図
2において、各々のチャンバーは超高真空あるいは高真
空に保持され、ゲートバルブ1で仕切られている。チャ
ンバーはCVD室2、スパッタ室3,4、準備室5及び
UHV(ウルトラハイバキューム、超高真空)処理室6
からなり、準備室5を中心として各チャンバー間をウエ
ハが移動できるようになっている。
(Embodiment 1) FIG. 2 is a schematic view showing the structure of a multi-chamber apparatus according to Embodiment 1 of the present invention. In FIG. 2, each chamber is maintained in an ultrahigh vacuum or a high vacuum and is partitioned by a gate valve 1. The chambers are the CVD chamber 2, the sputtering chambers 3 and 4, the preparation chamber 5, and the UHV (Ultra High Vacuum, Ultra High Vacuum) processing chamber 6.
The wafer can be moved between the chambers with the preparation chamber 5 as the center.

【0020】次に、図3は10-10 Torr台の超高真空
に保持されるUHV処理室内6に設置されている表面処
理装置の構成を示す平面及び断面概略図である。図3に
おいて、11は基板12を保持するための基板ホルダーであ
り、この基板ホルダー11は基板12の素子形成領域側の表
面及びこの反対側の裏面を覆うことのないように、基板
12の縁を挟むような形状をしており、基板12表面が下に
向くように配置されている。そして、基板12の裏から赤
外線を照射することのできるヒーターとして赤外線ラン
プ13を備えている。また、基板12表面の垂直方向に3×
3の分子線セル14が配置され、基板12表面に均一に分子
線を照射できるようになっている。分子線セル14には、
高純度のSiがチャージされている。
Next, FIG. 3 is a plan view and a cross-sectional schematic view showing the structure of the surface treatment apparatus installed in the UHV treatment chamber 6 which is maintained in an ultrahigh vacuum of the order of 10 -10 Torr. In FIG. 3, reference numeral 11 denotes a substrate holder for holding the substrate 12, and the substrate holder 11 does not cover the surface of the substrate 12 on the element formation region side and the back surface on the opposite side thereof.
It has a shape sandwiching the edges of 12 and is arranged so that the surface of the substrate 12 faces downward. An infrared lamp 13 is provided as a heater that can radiate infrared rays from the back of the substrate 12. Also, 3 × in the vertical direction of the surface of the substrate
Three molecular beam cells 14 are arranged so that the surface of the substrate 12 can be uniformly irradiated with the molecular beam. In the molecular beam cell 14,
High-purity Si is charged.

【0021】まず、高真空に保たれている準備室5から
UHV処理室6へSi基板12を移動させる。次いで、S
i基板12を赤外線ランプ13と分子線セル14の間に移動
し、赤外線ランプ13により基板12表面温度を 300℃に保
持する。その間に分子線セル14の温度をシャッターを閉
めたままで1400℃程度に上げておく。この分子線セル14
の温度は、基板12表面における分子線成長のレートとし
て約1Å/秒になるように設定する。その後、基板12表
面温度を上昇させ、1000℃に達すると同時に分子線セル
14のシャッターを15秒間開ける。そして、分子線セル14
のシャッターを閉じたと同時に基板12温度を下降させ
る。基板12温度の下降は急速に温度が下がることのない
ように20秒程度で 300℃まで下げる。これにより、基板
12表面の数十Åの自然酸化膜を除去することができ、清
浄な基板12表面を得ることができる。ここで、この方法
を用いた場合の経時変化に対する基板表面温度変化を図
4に示す。
First, the Si substrate 12 is moved from the preparatory chamber 5 kept in a high vacuum to the UHV processing chamber 6. Then S
The i substrate 12 is moved between the infrared lamp 13 and the molecular beam cell 14, and the surface temperature of the substrate 12 is kept at 300 ° C. by the infrared lamp 13. Meanwhile, the temperature of the molecular beam cell 14 is raised to about 1400 ° C. with the shutter closed. This molecular beam cell 14
Is set so that the rate of molecular beam growth on the surface of the substrate 12 is about 1Å / sec. After that, the surface temperature of the substrate 12 is increased to reach 1000 ° C and at the same time the molecular beam cell is reached.
Open 14 shutters for 15 seconds. And molecular beam cell 14
The substrate 12 temperature is lowered at the same time when the shutter of is closed. The temperature of the substrate 12 is lowered to 300 ° C. in about 20 seconds so that the temperature does not fall rapidly. This allows the substrate
It is possible to remove several tens of liters of natural oxide film on the 12th surface and obtain a clean substrate 12 surface. Here, FIG. 4 shows changes in the substrate surface temperature with time when this method is used.

【0022】そして、清浄な表面が得られた基板12は再
び準備室5に戻され、CVD室2、スパッタ室3、スパ
ッタ室4に各々移動し、所定の処理が加えられる。以上
のように、本実施例では、超高真空または高真空からな
るマルチチャンバー装置に極めて清浄な表面処理を行え
る表面処理装置を加えることによって、清浄な基板12表
面が得られ、汚染の心配がなく、次のチャンバーに移動
させ次の所定の処理を行うことができるので、優れた特
性を有する半導体デバイスを製作することができた。分
子線セル14からは高純度のSi分子ビームが照射される
ため、Si以外に不純物がなく、基板12上に不純物が残
存することもない。そして、分子線セル14を複数個用い
ているため、基板12に均一に分子線が照射され、8イン
チウエハを用いた場合でもむらなく表面処理が行える。
また、基板12昇温には赤外線ランプ13によるRTA法を
用いているため、高温に保っている時間は数十秒程度と
短く、不純物の拡散は起こらず、ダメージもない。
Then, the substrate 12 on which a clean surface is obtained is returned to the preparation chamber 5 again, moved to the CVD chamber 2, the sputtering chamber 3 and the sputtering chamber 4 and subjected to a predetermined treatment. As described above, in the present embodiment, a clean substrate 12 surface can be obtained by adding a surface treatment device capable of extremely clean surface treatment to a multi-chamber device composed of an ultra-high vacuum or a high vacuum, and there is a risk of contamination. Instead, it can be moved to the next chamber and subjected to the next predetermined treatment, so that a semiconductor device having excellent characteristics could be manufactured. Since the high-purity Si molecular beam is irradiated from the molecular beam cell 14, there are no impurities other than Si and no impurities remain on the substrate 12. Since a plurality of molecular beam cells 14 are used, the substrate 12 is uniformly irradiated with the molecular beam, and even if an 8-inch wafer is used, the surface treatment can be performed evenly.
Further, since the RTA method using the infrared lamp 13 is used to raise the temperature of the substrate 12, the high temperature keeping time is as short as several tens of seconds, diffusion of impurities does not occur, and there is no damage.

【0023】(実施例2)本実施例でも、マルチチャン
バー装置には実施例1の装置と同一のものを用いて説明
する。図5は10-10 Torr台の超高真空に保持される
真空装置の真空室であるUHV処理室6内に設置されて
いる表面処理装置の構成を示す平面及び断面概略図であ
る。図5において、図3と同一符号は同一または相当部
分を示し、11aは基板12を保持するための基板ホルダー
であり、この基板ホルダー11aは、基板12表面が下に向
くように基板12を4枚保持できる十字型をしており、中
心を軸として回転するようになっている。そして、基板
ホルダー11a下には、軸を中心に8方向に等分し、図2
の準備室5方向からローダー21、赤外線ランプ13a、分
子線セル14a、赤外線ランプ13b、分子線セル14b、赤
外線ランプ13c、分子線セル14c、アンローダー22の順
に配置されている。ここでの赤外線ランプ13a〜13c
は、各々基板12表面を照射するように上向きに配置され
ている。分子線セル14a〜14cは1ヵ所に付き3×3本
配置し、基板12表面に均一に分子線が照射されるように
する。この分子線セル14a〜14cには、高純度のSiが
チャージされている。ローダー21は、準備室5から移動
してきた基板12を十字型の基板ホルダー11aに取り付け
ることができるように、アンローダー22は、処理の終わ
った基板12を準備室5に移動させることができるような
構成になっている。
(Embodiment 2) In this embodiment, the same multichamber device as that of the first embodiment will be described. FIG. 5 is a plan view and a cross-sectional schematic view showing the configuration of a surface treatment apparatus installed in a UHV treatment chamber 6 which is a vacuum chamber of a vacuum apparatus which is maintained at an ultrahigh vacuum of 10 −10 Torr level. In FIG. 5, the same reference numerals as those in FIG. 3 indicate the same or corresponding portions, and 11a is a substrate holder for holding the substrate 12, and this substrate holder 11a holds the substrate 12 so that the surface of the substrate 12 faces downward. It has a cross shape that can hold one sheet, and it is designed to rotate about its center. Then, under the substrate holder 11a, it is equally divided into eight directions about the axis as shown in FIG.
The loader 21, the infrared lamp 13a, the molecular beam cell 14a, the infrared lamp 13b, the molecular beam cell 14b, the infrared lamp 13c, the molecular beam cell 14c, and the unloader 22 are arranged in this order from the preparation chamber 5 direction. Infrared lamps here 13a-13c
Are arranged so as to illuminate the surface of the substrate 12, respectively. The molecular beam cells 14a to 14c are arranged at 3 × 3 in one place so that the surface of the substrate 12 is uniformly irradiated with the molecular beam. High-purity Si is charged in the molecular beam cells 14a to 14c. The loader 21 can attach the substrate 12 moved from the preparation chamber 5 to the cross-shaped substrate holder 11a, and the unloader 22 can move the processed substrate 12 to the preparation chamber 5. It has a simple structure.

【0024】まず、高真空に保たれている準備室5から
UHV処理室6へ基板12を移動させる。その際、基板12
はローダー21により基板ホルダー11aに取り付けられ
る。次いで、基板ホルダー11aに取り付けられた基板12
は、基板ホルダー11aが回転し赤外線ランプ13a上に移
動して基板12表面温度が 300℃に保持される。その間に
分子線セル14aの温度を1400℃程度に上げておく。この
分子線セル14aの温度は、基板12表面における分子線成
長のレートとして約1Å/秒になるように設定する。基
板12表面は赤外線ランプ13a上で1200℃に加熱される。
基板12表面温度が1200℃になるとすぐに分子線セル14a
上に移動し分子線が5秒程度照射され、シャッターが閉
じる。その間に次の基板12が基板ホルダー11aに取り付
けられる。シャッターが閉じると基板12は分子線セル14
b上に移動する。次の基板12表面温度が 300℃になる
と、最初の基板12及び次の基板12の表面が1200℃に加熱
される。基板12表面温度が1200℃になると、すぐに次の
分子線セル上に移動し、分子線が5秒程度照射される。
この操作を1回転分行い基板12はローダー21により準備
室5に戻される。分子線セル14a〜14cからの分子流の
照射時間は合計10秒〜15秒程度になるように設定されて
いる。また、十字型の基板ホルダー11aは各々の動作に
合うように回転する。そして、基板12が一回りすると、
基板12表面の数十の自然酸化膜を除去することができ、
清浄な基板12表面を得ることができる。ここで、この方
法を用いた場合の経時変化に対する基板表面温度変化を
図6に示す。
First, the substrate 12 is moved from the preparatory chamber 5 which is kept in a high vacuum to the UHV processing chamber 6. At that time, the substrate 12
Is attached to the substrate holder 11a by the loader 21. Then, the substrate 12 attached to the substrate holder 11a
The substrate holder 11a rotates and moves onto the infrared lamp 13a so that the surface temperature of the substrate 12 is maintained at 300 ° C. Meanwhile, the temperature of the molecular beam cell 14a is raised to about 1400 ° C. The temperature of the molecular beam cell 14a is set so that the molecular beam growth rate on the surface of the substrate 12 is about 1Å / sec. The surface of the substrate 12 is heated to 1200 ° C. on the infrared lamp 13a.
As soon as the surface temperature of the substrate 12 reaches 1200 ° C, the molecular beam cell 14a
It moves up and the molecular beam is irradiated for about 5 seconds, and the shutter closes. Meanwhile, the next substrate 12 is attached to the substrate holder 11a. When the shutter is closed, the substrate 12 is a molecular beam cell 14
Move up b. When the surface temperature of the next substrate 12 reaches 300 ° C, the surfaces of the first substrate 12 and the next substrate 12 are heated to 1200 ° C. When the surface temperature of the substrate 12 reaches 1200 ° C., it immediately moves to the next molecular beam cell and the molecular beam is irradiated for about 5 seconds.
This operation is performed for one rotation, and the substrate 12 is returned to the preparation chamber 5 by the loader 21. The irradiation time of the molecular flow from the molecular beam cells 14a to 14c is set to be 10 seconds to 15 seconds in total. Further, the cross-shaped substrate holder 11a rotates to suit each operation. Then, when the substrate 12 goes around once,
It is possible to remove dozens of natural oxide films on the surface of the substrate 12,
A clean substrate 12 surface can be obtained. Here, FIG. 6 shows changes in the substrate surface temperature with respect to changes with time when this method is used.

【0025】そして、清浄な表面が得られた基板12は再
び準備室5に戻され、CVD室2、スパッタ室3、スパ
ッタ室4に各々移動し、所定の処理が加えられる。以上
のように、本実施例では、超高真空または、高真空から
なるマルチチャンバー装置に極めて清浄な表面処理を行
える表面処理装置を加えることによって、清浄な基板12
表面が得られ、汚染の心配がなく、次のチャンバーに移
動させ次の所定の処理を行うことができるので、優れた
特性を有する半導体デバイスを製作することができた。
分子線セル14a〜14cからは高純度のSi分子ビームが
照射されるため、Si以外に不純物がなく、基板12上に
不純物が残存することもない。そして、分子線セルを複
数個用いているため、基板12に均一に分子線が照射さ
れ、8インチウエハを用いた場合でもむらなく表面処理
が行える。そして、本実施例では、円周上に赤外線ラン
プ13a〜13cと分子線セル14a〜14cを交互に並べ次々
と基板12に処理を加えることができるので、極めて効率
的に表面処理を行うことができる。また、基板12昇温に
は赤外線ランプ13〜13cによるRTA法を用いているた
め、高温に保っている時間は数十秒程度と短く、不純物
の拡散は起こらず、ダメージもない。
Then, the substrate 12 on which a clean surface is obtained is returned to the preparation chamber 5 again, moved to the CVD chamber 2, the sputtering chamber 3 and the sputtering chamber 4, and subjected to a predetermined treatment. As described above, in the present embodiment, a clean substrate 12 is obtained by adding a surface treatment apparatus capable of extremely clean surface treatment to a multi-chamber apparatus consisting of ultra-high vacuum or high vacuum.
Since the surface is obtained and there is no fear of contamination, it can be moved to the next chamber and the next predetermined treatment can be performed, so that a semiconductor device having excellent characteristics could be manufactured.
Since the high-purity Si molecular beam is irradiated from the molecular beam cells 14a to 14c, there are no impurities other than Si and no impurities remain on the substrate 12. Since a plurality of molecular beam cells are used, the substrate 12 is uniformly irradiated with the molecular beam, and even if an 8-inch wafer is used, surface treatment can be performed evenly. In this embodiment, since the infrared lamps 13a to 13c and the molecular beam cells 14a to 14c can be alternately arranged on the circumference and the treatment can be applied to the substrate 12 one after another, the surface treatment can be performed extremely efficiently. it can. Further, since the RTA method using the infrared lamps 13 to 13c is used to raise the temperature of the substrate 12, the time kept at high temperature is as short as several tens of seconds, diffusion of impurities does not occur, and there is no damage.

【0026】[0026]

【発明の効果】本発明によれば、被処理基板表面の自然
酸化膜を除去する際、処理表面に不純物残渣を生じ難く
することができるとともに、処理表面にダメージを入り
難くすることができ、しかも不純物拡散を生じ難くする
ことができ、素子特性の劣化を生じ難くすることができ
るという効果がある。
According to the present invention, when the natural oxide film on the surface of the substrate to be processed is removed, it is possible to prevent impurities from remaining on the processed surface and to prevent damage to the processed surface. Moreover, there is an effect that it is possible to make it difficult to cause impurity diffusion and to make it difficult to cause deterioration of element characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の炉を用いて基板を昇温した場合と本発明
のRTA法を用いて基板を昇温した場合との経時変化に
対する基板表面温度の変化を示す図である。
FIG. 1 is a diagram showing changes in a substrate surface temperature with respect to time when a substrate is heated using a conventional furnace and when the substrate is heated using an RTA method of the present invention.

【図2】本発明の実施例1に則したマルチチャンバー装
置の構成を示す概略図である。
FIG. 2 is a schematic diagram showing a configuration of a multi-chamber apparatus according to the first embodiment of the present invention.

【図3】本発明の実施例1に則した表面処理装置の構成
を示す平面及び断面概略図である。
FIG. 3 is a plan view and a cross-sectional schematic view showing a configuration of a surface treatment apparatus according to the first embodiment of the present invention.

【図4】本発明の実施例1に則した経時変化に対する基
板表面温度の変化を示す図である。
FIG. 4 is a diagram showing changes in the substrate surface temperature with time according to Example 1 of the present invention.

【図5】本発明の実施例2に則した表面処理装置の構成
を示す平面及び断面概略図である。
5A and 5B are schematic plan and sectional views showing the configuration of a surface treatment apparatus according to a second embodiment of the present invention.

【図6】本発明の実施例2に則した経時変化に対する基
板表面温度の変化を示す図である。
FIG. 6 is a diagram showing changes in the substrate surface temperature with time according to Example 2 of the present invention.

【図7】シリコン表面の自然酸化膜がデバイス基本構造
に与える悪影響を示す図である。
FIG. 7 is a diagram showing an adverse effect of a natural oxide film on a silicon surface on a basic structure of a device.

【符号の説明】[Explanation of symbols]

1 ゲートバルブ 2 CVD室 3,4 スパッタ室 5 準備室 6 UHV処理室 11,11a 基板ホルダー 12 基板 13,13a〜13c 赤外線ランプ 14,14a〜14c 分子線セル 21 ローダー 22 アンローダー 1 Gate Valve 2 CVD Room 3, 4 Sputtering Room 5 Preparation Room 6 UHV Processing Room 11, 11a Substrate Holder 12 Substrates 13, 13a-13c Infrared Lamp 14, 14a-14c Molecular Beam Cell 21 Loader 22 Unloader

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 被処理基板をRTA(Rapid Thermal An
nealing)法により短時間加熱する加熱工程と、該被処理
基板に該被処理基板の構成物質のビームを照射するビー
ム照射工程とを同時に行うか、あるいは交互に少なくと
も1回ずつ行うことにより、該被処理基板の表面処理を
行う工程とを含むことを特徴とする半導体装置の製造方
法。
1. A substrate to be processed is a RTA (Rapid Thermal An
by simultaneously performing a heating step of heating for a short time by a (nealing) method and a beam irradiation step of irradiating the substrate to be processed with a beam of a constituent material of the substrate to be processed, or alternately performing at least once. And a step of performing a surface treatment on the substrate to be processed.
【請求項2】 前記ビーム照射は、複数の分子線セルに
より行うことを特徴とする請求項1記載の半導体装置の
製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the beam irradiation is performed by a plurality of molecular beam cells.
【請求項3】 前記加熱は、赤外線照射加熱であること
を特徴とする請求項1乃至2記載の半導体装置の製造方
法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the heating is infrared irradiation heating.
【請求項4】 前記加熱工程と前記ビーム照射行程を同
時に行う際は、前記赤外線照射加熱を前記被処理基板の
素子形成領域の反対側の裏面から行い、該ビーム照射を
該被処理基板の素子形成領域側の表面から行うことを特
徴とする請求項3記載の半導体装置の製造方法。
4. When performing the heating step and the beam irradiation step at the same time, the infrared irradiation heating is performed from the back surface of the substrate to be processed, which is opposite to the element formation region, and the beam irradiation is performed to the elements of the substrate to be processed. The method for manufacturing a semiconductor device according to claim 3, wherein the process is performed from the surface on the formation region side.
【請求項5】 前記加熱工程と前記ビーム照射工程とを
交互に行う際は、前記赤外線照射加熱と該ビーム照射工
程とを前記被処理基板の素子形成領域側の面から行うこ
とを特徴とする請求項3記載の半導体装置の製造方法。
5. When the heating step and the beam irradiation step are performed alternately, the infrared irradiation heating and the beam irradiation step are performed from the surface of the substrate to be processed on the element formation region side. The method for manufacturing a semiconductor device according to claim 3.
【請求項6】 前記表面処理工程は、成膜前の前処理で
あることを特徴とする請求項5記載の半導体装置の製造
方法。
6. The method of manufacturing a semiconductor device according to claim 5, wherein the surface treatment step is a pretreatment before film formation.
【請求項7】 前記前処理は、複数のチャンバーを有す
るマルチチャンバー装置における前処理であることを特
徴とする請求項6記載の半導体装置の製造方法。
7. The method for manufacturing a semiconductor device according to claim 6, wherein the pretreatment is pretreatment in a multi-chamber apparatus having a plurality of chambers.
JP18206392A 1992-07-09 1992-07-09 Manufacture of semiconductor device Withdrawn JPH0629234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18206392A JPH0629234A (en) 1992-07-09 1992-07-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18206392A JPH0629234A (en) 1992-07-09 1992-07-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0629234A true JPH0629234A (en) 1994-02-04

Family

ID=16111698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18206392A Withdrawn JPH0629234A (en) 1992-07-09 1992-07-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0629234A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008283086A (en) * 2007-05-14 2008-11-20 Panasonic Corp Jointing device and jointing method
JP2019515490A (en) * 2016-04-20 2019-06-06 トルンプフ フォトニクス インコーポレイテッドTrumpf Photonics Inc. Laser facet passivation and system for performing such passivation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008283086A (en) * 2007-05-14 2008-11-20 Panasonic Corp Jointing device and jointing method
JP2019515490A (en) * 2016-04-20 2019-06-06 トルンプフ フォトニクス インコーポレイテッドTrumpf Photonics Inc. Laser facet passivation and system for performing such passivation

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