JPH06291655A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To provide the frequency synthesizer which improves the stability of an oscillation frequency and shortens frequency switching time by extracting the output signal of an integrating means containing ripple for each half cycle of an output from a first frequency dividing means by using sample/hold. CONSTITUTION:When frequency division data M are changed and an output A of a first frequency dividing means 2 is changed at a time t1, phase difference between waveforms A and B is enlarged and the duty ratio of an output C from a phase comparing means 5 is enlarged. As a result, an output D of an integrating means 6 gets an increase amount larger than a decrease amount, a waveform E obtd. by extracting the output D of the means 6 for each half cycle of the output A of the means 2 is increased by a sample/hold means 7, the output frequency of a VCO 3 is increased, feedback to return shifted phase difference to original 90 deg. is applied, and a finally new output frequency is stabilized. At such a time, the output waveform D of the means 6 contains the large ripple component but the output waveform E of the means 7 does not contain the ripple at all, therefore the integration time constant of the means 6 can be reduced, and frequency switching response speed can be accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer.

[0002]

2. Description of the Related Art In the communication field, a frequency hopping spread spectrum communication system in which frequencies are switched one after another in a short time is in the limelight, and a research on a frequency synthesizer has been actively conducted to realize it.

A conventional frequency synthesizer will be described below with reference to FIG. FIG. 5 is a block diagram showing a configuration of a conventional frequency synthesizer, which constitutes a PLL (phase lock loop). Reference numeral 1 is a reference frequency generating means (hereinafter abbreviated as OSC) which generates a frequency fr. Reference numeral 2 denotes a first frequency dividing means (hereinafter abbreviated as DEVa) which sets the fr to 1 / M in accordance with the frequency division data M input to the frequency division data input terminal 21. 3 is a voltage controlled oscillator (hereinafter referred to as VC
The oscillation frequency fo changes depending on the control input voltage. Reference numeral 4 denotes a second frequency dividing means (hereinafter abbreviated as DEVb) which sets fo to 1 / N according to the frequency division data N input to the frequency division data input terminal 41. Reference numeral 5 is a phase comparison means (hereinafter abbreviated as PC) for comparing the phases of the two signals DEVa and DEVb. Reference numeral 8 is a low-pass filter (hereinafter abbreviated as LPF) having a large time constant, and takes the long-term average of the output of the PC to generate the control input voltage of the VCO.

The operation of the conventional frequency synthesizer configured as described above will be described with reference to FIG. 5 and FIG. 6 showing signal waveforms of respective parts.

The PLL is the output frequency fr / M of DEVa.
And the output frequency fo / N of DEVb match, and
It operates to keep the phase difference at 90 degrees. Therefore, D
The two rectangular wave output signals ab of EVa2 and DEVb4 include the change timing t1 of the divided data M in the steady state.
There is a phase difference of 90 degrees before, the output signal c of the PC5 becomes a rectangular wave with a duty ratio of 50%, and the output signal of the LPF8, that is, the input signal g of the VCO3 maintains a constant value. At this time, the output frequency fo becomes fr · N / M.

Now, if the divided data M is changed at time t1 and the output a of the DEVa2 changes, the phase difference between the waveforms ab increases, the duty ratio of the output c of the PC5 increases, and the output d of the LPF8 increases. Is increased, the output frequency of the VCO 3 is increased, feedback is applied to return the phase difference to the original 90 degrees, and finally the output frequency is stabilized at the new output frequency. Frequency hopping is realized by changing data M and N one after another and hopping fo one after another.

[0007]

SUMMARY OF THE INVENTION In the above conventional configuration,
As shown in the waveform of FIG. 6d, if the time constant of the LPF 8 is not increased, the ripple component of the output is applied to the VCO 3,
The output frequency or phase will have large fluctuations. However, in frequency hopping, it is necessary to switch more frequencies in as short a time as possible.
The time constant of PF8 cannot be increased. That is, there is a problem that the stability of the frequency and the shortening of the switching time are not compatible with each other.

At present, a plurality of frequency synthesizers are operated in parallel in order to achieve an apparent compatibility between the two, but this leads to an increase in cost and power consumption and an increase in the size of equipment, resulting in miniaturization and cost reduction. The development of a frequency synthesizer that can switch frequencies in a short time to achieve low power consumption has been a challenge.

[0009]

In order to solve the above-mentioned problems, the present invention provides a reference frequency generating means (hereinafter abbreviated as OSC) and a first frequency dividing for dividing a reference frequency fr generated by the OSC. Means (hereinafter abbreviated as DEVa), a voltage controlled oscillator (hereinafter abbreviated as VCO) whose oscillation frequency changes according to an input voltage value, and second frequency dividing means (hereinafter abbreviated as DEVb) for dividing the output frequency fo of the VCO. ) And the above D
Phase comparison means (hereinafter abbreviated as PC) that compares the phases of the output signals of EVa and DEVb, integration means (hereinafter abbreviated as INT) that integrates the output of the PC, and the output of the INT is half of the output of the DEVa. Sample and hold means (hereinafter abbreviated as S / H) that extracts every cycle and holds until the next extraction
The VCO is a frequency synthesizer having an S / H output as an oscillation frequency control signal input.

[0010]

According to the above construction, since the INT output signal containing ripples is extracted by S / H for each half cycle of the DEVa output, the S / H output, that is, the control input of the VCO does not contain any ripples and oscillates. The frequency is stable. Therefore, the INT integration time constant can be set to an extremely small value to improve the response speed of frequency switching, and since this frequency synthesizer can support frequency hopping, downsizing of equipment and reduction of power consumption, Cost reduction is possible.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the block diagram of FIG. 1 and FIG. 4 showing signal waveforms of respective parts. The same parts as those in the conventional example are designated by the same reference numerals and the description thereof will be omitted.

Reference numeral 6 is an INT for integrating the output of the PC 5, and reference numeral 7 is an S / H for extracting the output of the INT 6 every half cycle of the output of the DEVa 2 and holding it until the next extraction.

Assuming that the frequency division data M is changed at time t1 and the output A of DEVa2 is changed as in the conventional example,
Since the phase difference between the waveforms AB becomes large, the duty ratio of the output C of the PC 5 becomes large. As a result, the output D of INT6 is larger in the amount of increase than in the amount of decrease, and the output D of INT6 is extracted by S / H7 every half cycle of the output of DEVa2 (each edge of waveform A in the example of FIG. 4). Waveform E
Rises, the output frequency of the VCO 3 rises, feedback is applied to return the shifted phase difference to the original 90 degrees, and finally stabilizes at the new output frequency.

At this time, the output waveform D of the INT 6 contains a large ripple component, but the output waveform E of the S / H 7 contains no ripple. That is, there is no frequency fluctuation. Therefore, it is possible to reduce the integral time constant of INT6 and increase the frequency switching response speed.

FIG. 2 is a diagram showing a specific configuration of the INT 6, and if C is at a high level according to the output C of the PC 5, the switching means (hereinafter abbreviated as SW) 61 is turned up and the first constant is set. A capacitor 64 is charged by a current source (hereinafter abbreviated as CCa) 62, and if C is at a low level, the SW 61 is turned down, and a capacitor 64 is discharged by a second constant current source (hereinafter abbreviated as CCb) 63. . With this configuration, the frequency control signal proportional to the phase difference of the waveform AB can be supplied to the VCO 3 through the periodic extraction by the S / H 7.

Next, a second embodiment of the present invention is shown in FIG.
FIG. 3 shows the configuration in which the INT 6 of FIG. 1 is composed of a resistor 65 and a capacitor 64. The difference from the conventional LPF is that its time constant is extremely small, which is about 1/2 to 2 times the cycle of the output waveform A of DEVa2. The point is that it is set to a value. The parts other than the integrating means are the same as those in the first embodiment, and the operation at this time is also the same as in the above-mentioned first embodiment.

Even with such a small time constant, due to the action of S / H7, the VCO 3 has no librable portion, and the frequency control signal proportional to the phase difference of the waveform AB can be supplied. Similarly, the frequency switching response speed can be increased.

In the above-mentioned embodiment, as the integrating means,
The present invention has been realized as a combination of a switching means, a capacitor and a constant current source resistance and a combination of a resistance and a capacitor, but this does not unduly limit the present invention, and any other general integration means may be used. Absent.

[0019]

As described above, according to the present invention, the combination of the sample hold means and the integrating means having a small time constant allows the VCO to respond to the change in frequency in spite of its fast response to the ripple. It is possible to supply an oscillation frequency control signal that is not included at all, and as a result, only one frequency synthesizer, which was conventionally required for multiple units, can be used, resulting in downsizing of equipment,
It is possible to reduce power consumption and cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a frequency synthesizer according to a first embodiment of the present invention.

FIG. 2 is a block diagram of the integrating means of the frequency synthesizer of the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a low-pass filter of a frequency synthesizer according to a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram of each part of the frequency synthesizer according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional frequency synthesizer.

FIG. 6 is a signal waveform diagram of each part of a conventional frequency synthesizer.

[Explanation of symbols]

 1 Reference Frequency Generating Means 2 First Dividing Means 3 Voltage Controlled Oscillator 4 Second Dividing Means 5 Phase Comparing Means 6 Integrating Means 7 Sample Hold Means 8 Low Pass Filters

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9182-5J H03L 7/10 Z

Claims (1)

[Claims] 1. A reference frequency generating means, a first frequency dividing means for dividing a reference frequency generated by the reference frequency generating means, a voltage controlled oscillator whose oscillation frequency changes according to an input voltage value, and the voltage control. Second frequency dividing means for dividing the output frequency of the oscillator, phase comparing means for comparing the phases of the output signals of the first and second frequency dividing means, and integrating means for integrating the output of the phase comparing means. And a sample hold means for extracting the output of the integrating means for each half cycle of the output of the first frequency dividing means and holding it until the next extraction time. The output of the sample hold means is the voltage controlled oscillator. A frequency synthesizer characterized by being used as an input.