JPH06291200A - Side-wall and forming method - Google Patents

Abstract

PURPOSE:To provide a side wall and its manufacturing method, in which the side wall has a forward taper shape that prevents a residue of wiring material like polysilicon remaining in a patterning step. CONSTITUTION:Each side wall is formed beside one or more given films 3 and 4 formed by patterning. The side wall is made up of two or more multilayer films 5a and 6b. Each multilayer film 5a or 5b has a descending-step shape and projected outward from the side of the given one or more films 3 and 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sidewall and a method for forming the same, and more particularly to a sidewall having a forward tapered shape and a method for forming the same.

[0002]

2. Description of the Related Art SOI (Silicon On Insulating Substr)
ate) In a DRAM (Dynamic Random Access Memory) and an SRAM, a bit contact hole for connecting a bit line and a silicon substrate has an S on the gate electrode.
An iO ₂ film is formed so as to be insulated from the gate electrode, and a sidewall is formed on the side wall of the gate electrode and the SiO ₂ film, so that the gate electrode is formed in a self-aligned manner.

FIG. 4 is a diagram showing a conventional method for forming a side wall.

As shown in FIG. 4A, the silicon substrate 1
A gate oxide film 2 is formed thereon, and then a polysilicon film and a SiO ₂ film are formed on the entire surface. Next, the SiO ₂ film and the polysilicon film are patterned by lithography and RIE to form the SiO ₂ film 4 and the gate electrode 3.

Next, as shown in FIG.
The O ₂ film 100 is formed, and then the SiO ₂ film 1 is formed by RIE.
00 is etched back, and side walls 101 are formed on the side surfaces of the gate electrode 3 and the SiO ₂ film 4 as shown in FIG.
And the unnecessary gate oxide film 2 is removed. Next, interlayer SiO ₂ 200 is deposited, and the bit contact is opened in a self-aligned manner so as to overlap the gate electrode 3.

Next, a second polysilicon film (not shown) is formed, and this second polysilicon film is patterned to form bit lines.

[0007]

Due to the miniaturization of semiconductor devices, the gap between adjacent gate electrodes 3 becomes narrower, and SiO ₂
When a contact hole is to be opened after the film 4 and the sidewall 101 in a self-aligning manner, the distance between the adjacent gate electrodes 3 and the film thickness of the gate electrode 3 and the SiO ₂ film 4 are added. The aspect ratio, which is the ratio of the two, becomes large, and the sidewall 101 becomes steep as shown in FIG.

However, when the bit line is formed by opening the contact hole in a self-aligning manner and patterning the second polysilicon film, the sidewall 10 is formed as described above.
Since 1 is steep, a silicon residue 102, which is an etching residue of the second polysilicon film, remains on a side portion of the sidewall 101 in a region other than the bit line as shown in FIG. This silicon residue 102 extends laterally (perpendicular to the paper surface), causing a problem that the bit lines are short-circuited to each other.

Therefore, an object of the present invention is to provide a sidewall having a forward taper shape so as not to remain when a wiring material such as polysilicon is patterned at the time of wiring, and a manufacturing method thereof.

[0010]

According to the present invention, the above-mentioned problem is achieved in a sidewall formed on a predetermined film having one or more patterned layers, wherein the sidewall is composed of a multilayer film having two or more layers. This is solved by a sidewall characterized in that the multilayer film has a stepwise downward shape from the side surface of a predetermined film including one or more patterned layers to the outside.

Further, according to the present invention, the above-mentioned problems include a step of patterning and forming a predetermined film consisting of one or more layers on or above a semiconductor substrate, and two or more layers in which the etching rate increases sequentially from the lower layer to the upper layer. A step of forming a multilayer film over the entire surface of the semiconductor substrate, and a stepwise descending step of forming a multilayer film by etching back the multilayer film at the etching rate to the outside from the side surface of a predetermined film composed of one or more layers. And a step of forming a side wall of the present invention.

Further, according to the present invention, the above problem is preferably solved by a sidewall forming method, wherein the multilayer film is a TEOS film and a silicon nitride film from the bottom layer.

Further, according to the present invention, the above-mentioned problems can be preferably solved by a sidewall forming method, wherein the multilayer film is a TEOS film and a PSG film from the bottom layer.

Further, according to the present invention, the above problem is preferably solved by a sidewall forming method, wherein the multilayer film is a silicon nitride film and a TEOS film from the bottom.

[0015]

According to the present invention, as shown in FIG. 1, the sidewalls of the gate electrode 3 and the insulating film 4 on the gate electrode 3 are formed of a multilayer film, for example, the first insulating film 5a and the second insulating film. Since the side wall made of 6b is formed and there is a step on the contact surface between the layers of the side wall, the side wall has a forward tapered shape. Therefore, the material film such as the electrodes formed on the sidewalls can be etched without etching residues, and problems such as a short circuit due to etching residues can be eliminated.

Further, according to the present invention, after patterning one or more predetermined films, as shown in FIG. 2 (b), a multilayer film of two or more layers, such as an etching rate increasing from the lower layer to the upper layer, for example, When the TEOS film 5 and the silicon nitride film 6 are sequentially formed and etched back to form sidewalls as shown in FIG. 3A, since the upper layer has a higher etching rate, the upper layer is more etched and the lower layer is formed. The upper end of the film is located higher than the upper end of the upper film, and the sidewall has a forward tapered shape.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a sidewall according to the present invention.

As shown in FIG. 1, a gate oxide film 2 is formed on a silicon substrate 1, and a gate electrode 3 is formed on the gate oxide film 2 to insulate the gate electrode 3 from the wiring formed in the upper layer. Therefore, the SiO ₂ film 4 is formed. Sidewalls composed of the TEOS film 5a and the silicon nitride film 6b are formed on the side surfaces of the gate electrode 3 and the SiO ₂ film 4, and the upper end of the TEOS film 5a is silicon at the boundary between the TEOS film 5a and the silicon nitride film 6b. Nitride film 6b
Since it is located above the upper end of the sidewall, the sidewall has a forward tapered shape.

Therefore, in the SRAM or the like between the gate electrodes 3, an interlayer insulating film is deposited in the post-process of FIG. 1, a second polysilicon is deposited after the bit contact opening, and the second polysilicon is patterned to form the bit. Although a line is formed, since the etching residue of the second polysilicon is not left on the interlayer insulating film on the sidewall portion when the patterning of the second polysilicon is performed, the bit lines are shorted with each other. There is nothing to do.

2 and 3 are process sectional views showing a sidewall forming method according to the first embodiment of the present invention.

First, as shown in FIG.
The gate oxide film 2 having a thickness of 10 nm is formed on the plate 1 by the thermal oxidation method.
To form. Next, by low pressure CVD (chemical vapor deposition) method
To form a 140 nm thick polysilicon film,
After doping with N-type impurities such as phosphorus (P)
Activates the membrane. Then contact the contacts in a self-aligning manner.
Thickness of 240 nm by CVD method to open
Sano SiO₂Form a film. Then lithography and R
SiO by IE (Reactive Ion Etching) ₂Membrane and
The polysilicon film is patterned to form a 0.4 μm wide film.
Electrode 3 and SiO₂The film 4 is formed.

Next, a film having a lower etching rate is formed as a first insulating film in the lower layer, and a film having a higher etching rate is formed as a second insulating film in the upper layer of the first insulating film. For example, tetraethoxysilane (hereinafter referred to as TEOS) is used as the first insulating film, and a silicon nitride film is used as the second insulating film. Next, these will be described.

As shown in FIG. 2 (b), for example, tetraethoxysilane (Si
(OC ₂ H ₅ ) ₄ ) is pyrolyzed to give 100 nm thick T
The EOS film 5 is formed. Next, 150 by the low pressure CVD method.
A silicon nitride film 6 having a thickness of nm is formed.

Next, with the use of O ₂ and CHF ₃ as source gases, the silicon nitride film 6 and TE are etched under the etching conditions of a flow rate ratio O ₂ / CHF ₃ = 35/75, a pressure of 40 m Torr, and an electric power of 600 W.
The OS film 5 is etched back. Under this etching condition, the etching rate of the silicon nitride film 6 is TEO.
It is 1.5 times larger than the etching rate of the S film 5.

FIG. 2C shows a state in which the silicon nitride film 6 above the gate electrode 4 has been etched. As shown in this figure, the upper ends of the silicon nitride film 6a and the TEOS film 5 are aligned with each other. . When the etching is further advanced from this state, both the silicon nitride film 6a and the TEOS film 5 are etched, but the etching rate of the silicon nitride film 6a is higher than the etching rate of the TEOS film 5, so that it is shown in FIG. Thus, the upper end of the silicon nitride film 6b is lower than the upper end of the surface of the TEOS film 5a in contact with the silicon nitride film 6b. Therefore, the gate electrode 3 and Si
The side wall formed of the TEOS film 5a and the silicon nitride film 6a formed on the side wall of the O ₂ film 4 has a forward tapered shape. Further, when the TEOS film 5 is etched, the extra gate oxide film 2 is removed. Next, interlayer SiO ₂ 200 is deposited (70 nm) and bit contacts are formed on the gate electrode 3.
The contact holes are formed so as to overlap with the contact holes in a self-aligning manner.

Next, the second polysilicon film 7 is formed by the low pressure CVD method, and then N-type impurities such as phosphorus (P) are implanted into the second polysilicon film 7 to activate it. Next, the second polysilicon film 7 is patterned by lithography and RIE to have a shape as shown in FIG.
At this time, as described above, since the TEOS film 5a and the silicon nitride film 6b have a forward taper shape, when patterning the second polysilicon 7, the interlayer SiO ₂ on this portion is patterned.
Since the residue of silicon on 200 can be eliminated, the bit contacts due to the residue do not short-circuit with each other.

Next, a second embodiment of the sidewall forming method according to the present invention will be described. In the second embodiment, the same T as in the first embodiment is used as the first insulating film having a lower etching rate.
A PSG film was used as the EOS film and the second insulating film having a higher etching rate.

First, similarly to the first embodiment, as shown in FIG. 1A, a gate oxide film 2, a gate electrode 3 and a SiO ₂ film 4 are formed on a silicon substrate 1. Similar to the first embodiment, a TEOS film having a thickness of 100 nm, SiH ₄ , PH ₃
Then, a PSG film having a thickness of 100 nm is sequentially formed by a low temperature oxidation method using O ₂ and O ₂ as raw materials.

[0030] Next O ₂ and CHF ₃ flow ratio O ₂ / CHF ₃ = 8/75 as a raw material gas, pressure 50 m Torr, etching back the PSG film and the TEOS film by etching conditions of power 1150 W. Under this etching condition, the etching rate of the PSG film is about 1.3 times higher than the etching rate of the TEOS film. Therefore, as in the first embodiment, the upper end of the PSG film is in contact with the TE which is in contact with the PSG film.
Since it is below the upper end of the OS film, the gate electrodes 3 and S
The side wall of the io ₂ film 4 has a forward tapered TEOS film and PS.
A sidewall made of a G film is formed.

Next, a third embodiment of the sidewall forming method according to the present invention will be described. In the third embodiment, the sidewall has a three-layer structure including the first insulating film, the second insulating film, and the third insulating film from the lower layer, and the etching rate of the first insulating film <
An insulating film was used such that the etching rate of the second insulating film <the etching rate of the third insulating film. The following insulating films were used as the insulating film satisfying these etching rate relationships.

The TEOS film used in the first and second embodiments as the first insulating film, the PSG film used in the second embodiment as the second insulating film, and the third insulating film used in the first embodiment. Each silicon nitride film was used.

When these insulating films are etched under the same etching conditions as in the first embodiment, the etching rate of the silicon nitride film: the etching rate of the PSG film: TEOS
Since the etching rate of the film is about 1.6: about 1.3: 1 and the above relationship is satisfied, when these three layers are etched back, the shape of the side wall becomes more than that of the first and second embodiments. It becomes a forward taper.

In this embodiment, the sidewall having a two-layer structure and a three-layer structure has been described. However, even a sidewall having a multilayer structure of more than that, an insulating film having a higher etching rate sequentially from the lower layer to the upper layer. In this case, the sidewall can be forward tapered.

Next, a fourth embodiment of the sidewall forming method according to the present invention will be described. In the fourth embodiment, the same T as in the first embodiment is used as the first insulating film having a lower etching rate.
Although the EOS film 5 and the silicon nitride film 6 are used, the order of deposition and the conditions for etching back these films are different.

The etch back conditions in this case are the same as those described in the second embodiment, with O ₂ and CHF ₃ as the source gases, the flow rate ratio O ₂ / CHF ₃ = 8/75, and the pressure 50 mTo.
The etching conditions are rr and power of 1150 W. Under this condition, the etching rate of the TEOS film 5 is about 1.6 times larger than that of the silicon nitride film 6. Therefore,
Similar to the first embodiment, since the upper end of the TEOS film 5 is lower than the silicon nitride film 6 which is in contact with the TEOS film 5, the sidewalls of the gate electrode 3 and the SiO ₂ film 4 are forward-tapered with silicon nitride. A sidewall composed of the film 6b and the TEOS film 5a is formed.

[0037]

As described above, according to the present invention, it is possible to form a sidewall having a forward tapered shape,
When the upper layer wiring is processed on the interlayer insulating film on the sidewall end portion, the etching residue is eliminated, and there is no problem that the wiring is short-circuited by the etching residue, and the yield can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a sidewall according to an embodiment.

FIG. 2 is a sectional view (I) of a sidewall forming process according to an example.

FIG. 3 is a sectional view (II) of a sidewall forming process according to an example.

FIG. 4 is a sectional view of a sidewall forming process according to a conventional example.

FIG. 5 is a diagram for explaining the problems of the conventional example.

[Explanation of symbols]

1 Silicon Substrate 2 Gate Oxide Film 3 Gate Electrode 4 SiO ₂ Film 5, 5a TEOS Film 6, 6a, 6b Silicon Nitride Film 7 Second Polysilicon Film

Claims (5)

[Claims] 1. A sidewall formed on a patterned film consisting of one or more layers, said sidewall comprising a multilayer film comprising two or more layers, said patterned film comprising one or more patterned layers. The sidewall is characterized in that the multilayer film has a stepwise downward shape from the side surface to the outside. 2. A step of patterning and forming a predetermined film consisting of one or more layers on or above a semiconductor substrate, and a multi-layer film of two or more layers having an etching rate which sequentially increases from a lower layer to an upper layer, the entire surface above the semiconductor substrate. And a step of etching back the multilayer film at the etching rate and forming sidewalls of the multilayer film in a stepwise downward shape from the side surface of the predetermined film composed of one or more patterned layers to the outside. A method of forming a sidewall, comprising: 3. A step of thermally oxidizing a silicon substrate to form a gate oxide film, and forming an electrode material film and an insulating film on the gate oxide film,
A step of patterning the electrode material film and the insulating film to form an electrode; a step of forming a multilayer film of two or more layers having an etching rate that sequentially increases from a lower layer to an upper layer, and a step of forming a multilayer film above the silicon substrate. Etching back the multi-layer film to form side walls of the multi-layer film in a stepwise descending shape on the multiple sides from the side surfaces of the electrode and the insulating film. 4. The sidewall forming method according to claim 2, wherein the multilayer film is a TEOS film and a silicon nitride film from the bottom. 5. The multilayer film comprises a TEOS film and a PS
It is a G film, The sidewall formation method in any one of Claim 2 or 3 characterized by the above-mentioned.