JPH06286372A - Ic card - Google Patents
Ic cardInfo
- Publication number
- JPH06286372A JPH06286372A JP4134913A JP13491392A JPH06286372A JP H06286372 A JPH06286372 A JP H06286372A JP 4134913 A JP4134913 A JP 4134913A JP 13491392 A JP13491392 A JP 13491392A JP H06286372 A JPH06286372 A JP H06286372A
- Authority
- JP
- Japan
- Prior art keywords
- dtcpic
- connector
- terminal
- card
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 claims description 29
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 3
- 101100153168 Arabidopsis thaliana TIC21 gene Proteins 0.000 description 1
- 101100273813 Homo sapiens CDKN1A gene Proteins 0.000 description 1
- 108700038981 SUMO-1 Proteins 0.000 description 1
- 101100083337 Schizosaccharomyces pombe (strain 972 / ATCC 24843) pic1 gene Proteins 0.000 description 1
- 102100026940 Small ubiquitin-related modifier 1 Human genes 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
Landscapes
- Credit Cards Or The Like (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、ＤＴＣＰ（Dual Tap
e Carrier Package）ＩＣを搭載した複数の基板を備え
たＩＣカードに関するものである。BACKGROUND OF THE INVENTION The present invention relates to DTCP (Dual Tap).
(e Carrier Package) The present invention relates to an IC card having a plurality of substrates on which ICs are mounted.
【０００２】[0002]
【従来の技術】図６は、従来のＩＣカードを示す構成図
である。図６において、１はＴＳＯＰＩＣ、２はＴＳＯ
ＰＩＣ１の足である。３は表面及び裏面にＴＳＯＰＩＣ
１を搭載したＩＣ搭載基板であり、表面及び裏面には足
２にハンダ付けによって接続された配線パターンが形成
されている。４はこの配線パターンに接続された端子、
５は端子４にハンダ付けによって接続されたコネクタ電
極、６はコネクタ電極５に接続されたコネクタである。2. Description of the Related Art FIG. 6 is a block diagram showing a conventional IC card. In FIG. 6, 1 is TSOPIC, 2 is TSO
It is the foot of PIC1. 3 is TSOPIC on the front and back
1 is an IC mounting board on which wiring patterns connected to the feet 2 by soldering are formed on the front and back surfaces. 4 is a terminal connected to this wiring pattern,
Reference numeral 5 is a connector electrode connected to the terminal 4 by soldering, and 6 is a connector connected to the connector electrode 5.
【０００３】次に、図６に示した従来のＩＣカードの動
作について説明する。ＴＳＯＰＩＣ１とコネクタ６との
間は、足２、ＩＣ搭載基板３上の配線パターン、端子
４、及びコネクタ電極５を介して接続される。従って、
ＴＳＯＰＩＣ１とコネクタ６との間で信号伝達が可能で
ある。Next, the operation of the conventional IC card shown in FIG. 6 will be described. The TSOPIC 1 and the connector 6 are connected via the foot 2, the wiring pattern on the IC mounting substrate 3, the terminal 4, and the connector electrode 5. Therefore,
Signal transmission is possible between the TSOPIC 1 and the connector 6.
【０００４】[0004]
【発明が解決しようとする課題】従来のＩＣカードは、
以上のように、厚さのあるＴＳＯＰＩＣ１を使用してお
り、ＩＣカードの厚さｔを一定値内に収める必要から、
ＩＣ搭載基板３を１枚しか用いることができないため、
大容量化等の高機能化を図れないという問題点があっ
た。The conventional IC card is
As described above, the thick TSOPIC1 is used, and it is necessary to keep the thickness t of the IC card within a fixed value.
Since only one IC mounting board 3 can be used,
There is a problem in that high functionality such as large capacity cannot be achieved.
【０００５】この発明は、上記のような問題点を解決す
るためになされたもので、厚さを一定値内に収めつつ、
大容量化等の高機能化を図ることができるＩＣカードを
得ることを目的とする。The present invention has been made in order to solve the above problems, and keeps the thickness within a fixed value.
It is an object of the present invention to obtain an IC card capable of achieving high functionality such as large capacity.
【０００６】[0006]
【課題を解決するための手段】この発明の請求項１に係
るＩＣカードは、ＤＴＣＰＩＣを搭載し、ＤＴＣＰＩＣ
に接続されたスルーホールを端部に有し、スルーホール
の位置が揃った状態で平行に並べて配置された複数のＤ
ＴＣＰＩＣ搭載基板と、Ｌ字形の形状をなし、導体から
構成され、一端が複数のＤＴＣＰＩＣ搭載基板の各スル
ーホールに貫通状態で接続されたＬ字形コネクタ電極
と、Ｌ字形コネクタ電極の他端が接続されたＬ字形電極
用コネクタとを備えたものである。An IC card according to claim 1 of the present invention has a DTCPIC mounted thereon,
A plurality of Ds having through holes connected to the end are arranged in parallel with the positions of the through holes aligned.
An L-shaped connector electrode, which has an L-shaped configuration and is composed of a conductor and has one end connected to each through hole of a plurality of DTCPIC mounting substrates in a penetrating state, and the other end of the L-shaped connector electrode is connected. And an L-shaped electrode connector that has been prepared.
【０００７】この発明の請求項２に係るＩＣカードは、
ＤＴＣＰＩＣを搭載し、ＤＴＣＰＩＣに接続された端子
を端部に有し、平行に並べて配置された２枚のＤＴＣＰ
ＩＣ搭載基板と、両端部に配置された第１の端子及び第
２の端子を有し、第１の端子は２枚のＤＴＣＰＩＣ搭載
基板の各端子に接続され、第１の端子と第２の端子との
間は導通されている補助基板と第２の端子が接続された
コネクタとを備えたものである。The IC card according to claim 2 of the present invention is
Two DTCPs mounted with a DTCPIC, having terminals connected to the DTCPIC at their ends and arranged side by side in parallel
It has an IC mounting board and a first terminal and a second terminal arranged at both ends. The first terminal is connected to each terminal of two DTCPIC mounting boards, and the first terminal and the second terminal are connected. The auxiliary board is electrically connected between the terminals and the connector to which the second terminal is connected.
【０００８】この発明の請求項３に係るＩＣカードは、
ＤＴＣＰＩＣであるメモリＩＣを搭載し、メモリＩＣに
接続された端子を端部に有し、平行に並べて配置された
複数のメモリＩＣ搭載基板と、メモリＩＣ用の周辺ＩＣ
を搭載し、周辺ＩＣに接続されるとともに両端部に配置
された第１の端子及び第２の端子を有し、第１の端子は
複数のメモリＩＣ搭載基板の各端子に接続されている周
辺ＩＣ搭載基板と、第２の端子が接続されるコネクタと
を備えたものである。An IC card according to claim 3 of the present invention is
A plurality of memory IC mounting boards mounted with a memory IC, which is a DTCPIC, having terminals connected to the memory IC at their ends and arranged in parallel, and peripheral ICs for the memory IC
And a peripheral having a first terminal and a second terminal which are connected to a peripheral IC and are arranged at both ends, the first terminal being connected to each terminal of the plurality of memory IC mounting boards. An IC mounting board and a connector to which the second terminal is connected are provided.
【０００９】この発明の請求項４に係るＩＣカードは、
ＤＴＣＰＩＣ、ＤＴＣＰＩＣ搭載基板、及びＬ字形コネ
クタ電極の全体を覆い、導体から構成されたパネルを備
え、Ｌ字形コネクタ電極のうちのＧＮＤ電極のみをパネ
ルに接続したものである。An IC card according to claim 4 of the present invention is
The DTCPIC, the DTCPIC mounting substrate, and the L-shaped connector electrode are entirely covered, and a panel including a conductor is provided, and only the GND electrode of the L-shaped connector electrode is connected to the panel.
【００１０】[0010]
【作用】この発明の請求項１に係るＩＣカードにおいて
は、ＤＴＣＰＩＣとＬ字形電極用コネクタとの間は、Ｄ
ＴＣＰＩＣの足、ＤＴＣＰＩＣ搭載基板上の配線パター
ン、スルーホール、及びＬ字形コネクタ電極を介して接
続される。In the IC card according to the first aspect of the present invention, the DTCPIC and the connector for the L-shaped electrode are connected by D
Connection is made via the legs of the TCPIC, the wiring pattern on the DTCPIC mounting substrate, the through holes, and the L-shaped connector electrodes.
【００１１】この発明の請求項２に係るＩＣカードにお
いては、ＤＴＣＰＩＣとコネクタとの間は、ＤＴＣＰＩ
Ｃの足、ＤＴＣＰＩＣ搭載基板上の配線パターン、端
子、第１の端子、補助基板上の配線パターン、第２の端
子、及びコネクタ電極を介して接続される。In the IC card according to the second aspect of the present invention, the DTCPI is provided between the DTCPIC and the connector.
Connection is made via the C leg, the wiring pattern on the DTCPIC mounting substrate, the terminal, the first terminal, the wiring pattern on the auxiliary substrate, the second terminal, and the connector electrode.
【００１２】この発明の請求項３に係るＩＣカードにお
いては、メモリＩＣと周辺ＩＣとの間は、メモリＩＣの
足、メモリＩＣ搭載基板上の配線パターン、端子１９
ａ、１９ｂ、補助基板、第１の端子、周辺ＩＣ搭載基板
上の配線パターン、及び周辺ＩＣの足を介して接続され
る。また、周辺ＩＣとコネクタとの間は、周辺ＩＣの
足、周辺ＩＣ搭載基板上の配線パターン、第２の端子、
及びコネクタ電極を介して接続される。In the IC card according to claim 3 of the present invention, between the memory IC and the peripheral IC, the legs of the memory IC, the wiring pattern on the memory IC mounting substrate, and the terminals 19 are provided.
a, 19b, the auxiliary board, the first terminal, the wiring pattern on the peripheral IC mounting board, and the legs of the peripheral IC. Between the peripheral IC and the connector, the legs of the peripheral IC, the wiring pattern on the peripheral IC mounting board, the second terminal,
And a connector electrode.
【００１３】この発明の請求項４に係るＩＣカードにお
いては、パネルによって、ＤＴＣＰＩＣ、ＤＴＣＰＩＣ
搭載基板、及びＬ字形コネクタ電極の全体を覆い、さら
に、Ｌ字形コネクタ電極のうちＧＮＤ電極のみをパネル
に接続するIn the IC card according to claim 4 of the present invention, depending on the panel, DTCPIC, DTCPIC
The mounting substrate and the entire L-shaped connector electrode are covered, and only the GND electrode of the L-shaped connector electrode is connected to the panel.
【００１４】[0014]
実施例１．図１はこの発明の実施例１を示す構成図であ
り、図６と同一または相当部分には同一符号を付し、そ
の説明は省略する。７はＤＴＣＰＩＣであり、厚さはＴ
ＳＯＰＩＣ１よりも薄いものである。８ａ、８ｂは表面
及び裏面にＤＴＣＰＩＣ７を搭載したＤＴＣＰＩＣ搭載
基板であり、表面及び裏面には足２にハンダ付けによっ
て接続された配線パターンが形成されている。９ａ、９
ｂはＤＴＣＰＩＣ搭載基板８ａ、８ｂの端部に形成さ
れ、この配線パターンに接続されたスルーホールであ
る。ＤＴＣＰＩＣ搭載基板８ａ、８ｂはスルーホール９
ａ、９ｂの位置が、図１で上下方向に揃った状態で平行
に並べて配置されている。１０はＬ字形の形状をなし、
導体から構成され、一端がスルーホール９ａ、９ｂに貫
通状態でハンダ付けによって接続されたＬ字形コネクタ
電極、１１はＬ字形コネクタ電極１０の他端が接続され
たＬ字形電極用コネクタである。Example 1. First Embodiment FIG. 1 is a configuration diagram showing a first embodiment of the present invention. The same or corresponding parts as in FIG. 7 is a DTCPIC and has a thickness of T
It is thinner than SOPIC1. Reference numerals 8a and 8b denote DTCPIC mounting boards having DTCPIC 7 mounted on the front and back surfaces, and wiring patterns connected to the feet 2 by soldering are formed on the front and back surfaces. 9a, 9
Reference numeral b is a through hole formed at the end of the DTCPIC mounting boards 8a and 8b and connected to this wiring pattern. Through holes 9 are formed in the DTCPIC mounting boards 8a and 8b.
The positions of a and 9b are arranged in parallel in a state where they are aligned in the vertical direction in FIG. 10 has an L shape,
The L-shaped connector electrode is made of a conductor and has one end connected to the through holes 9a and 9b by soldering in a penetrating state.
【００１５】次に、図１に示したこの発明の実施例１の
動作について説明する。ＤＴＣＰＩＣ７とＬ字形電極用
コネクタ１１との間は、足２、ＤＴＣＰＩＣ搭載基板８
ａ、８ｂ上の配線パターン、スルーホール９ａ、９ｂ、
及びＬ字形コネクタ電極１０を介して接続される。この
とき、Ｌ字形コネクタ電極１０は２つのスルーホール９
ａ、９ｂを貫通する構造になっているため、ＤＴＣＰＩ
Ｃ搭載基板８ａ、８ｂに共通の信号を容易に接続するこ
とができる。また、共通でない信号を、一方の配線パタ
ーンを足２まで到達しないようにすることにより、他方
のＤＴＣＰＩＣ７のみに伝達させることができる。Next, the operation of the first embodiment of the present invention shown in FIG. 1 will be described. Between the DTCPIC 7 and the L-shaped electrode connector 11, the foot 2 and the DTCPIC mounting board 8 are provided.
a, 8b wiring pattern, through holes 9a, 9b,
And an L-shaped connector electrode 10. At this time, the L-shaped connector electrode 10 has two through holes 9
DTCPI has a structure that penetrates a and 9b.
A common signal can be easily connected to the C mounting boards 8a and 8b. In addition, a signal that is not common can be transmitted only to the other DTCPIC 7 by preventing one wiring pattern from reaching the foot 2.
【００１６】実施例２．図２はこの発明の実施例２を示
す構成図である。１２ａ、１２ｂは表面及び裏面にＤＴ
ＣＰＩＣ７を搭載したＤＴＣＰＩＣ搭載基板であり、表
面及び裏面には足２にハンダ付けによって接続された配
線パターンが形成されている。１３ａ、１３ｂはＤＴＣ
ＰＩＣ搭載基板１２ａ、１２ｂの端部に設けられた端子
である。ＤＴＣＰＩＣ搭載基板１２ａ、１２ｂは端子１
３ａ、１３ｂの位置が、図２で上下方向に揃った状態で
平行に並べて配置されている。１４は両端部に第１の端
子１５ａ、１５ｂ及び第２の端子１６ａ、１６ｂを有す
る補助基板であり、第１の端子１５ａ、１５ｂは端子１
３ａ、１３ｂとハンダ付けによって接続されており、第
１の端子１５ａ、１５ｂと第２の端子１６ａ、１６ｂと
の間は補助基板１４の表面及び裏面に形成された配線パ
ターンによって導通されている。５、６は従来のもの
（図６参照）と同一のコネクタ電極、コネクタである。
第２の端子１６ａ、１６ｂはコネクタ電極５にハンダ付
けによって接続されている。Example 2. Second Embodiment FIG. 2 is a configuration diagram showing a second embodiment of the present invention. 12a and 12b are DT on the front and back
This is a DTCPIC mounting board on which the CPIC 7 is mounted, and wiring patterns connected to the legs 2 by soldering are formed on the front and back surfaces. 13a and 13b are DTC
These are terminals provided at the ends of the PIC mounting boards 12a and 12b. The DTCPIC mounting boards 12a and 12b are terminals 1
The positions of 3a and 13b are arranged in parallel in a state where they are aligned in the vertical direction in FIG. Reference numeral 14 is an auxiliary substrate having first terminals 15a and 15b and second terminals 16a and 16b at both ends, and the first terminals 15a and 15b are the terminals 1
3a and 13b are connected by soldering, and the first terminals 15a and 15b and the second terminals 16a and 16b are electrically connected by a wiring pattern formed on the front and back surfaces of the auxiliary substrate 14. Reference numerals 5 and 6 are the same connector electrodes and connectors as the conventional ones (see FIG. 6).
The second terminals 16a and 16b are connected to the connector electrode 5 by soldering.
【００１７】次に、図２に示したこの発明の実施例２の
動作について説明する。ＤＴＣＰＩＣ７とコネクタ６と
の間は、足２、ＤＴＣＰＩＣ搭載基板１２ａ、１２ｂ上
の配線パターン、端子１３ａ、１３ｂ、第１の端子１５
ａ、１５ｂ、補助基板１４上の配線パターン、第２の端
子１６ａ、１６ｂ、及びコネクタ電極５を介して接続さ
れる。このとき、補助基板１４上の配線パターンを適当
に形成することにより、ＤＴＣＰＩＣ搭載基板１２ａ、
１２ｂに共通の信号を容易に接続することができ、ま
た、共通でない信号をＤＴＣＰＩＣ搭載基板１２ａ、１
２ｂのうちの一方のみに接続することも容易にできる。Next, the operation of the second embodiment of the present invention shown in FIG. 2 will be described. Between the DTCPIC 7 and the connector 6, the foot 2, the wiring pattern on the DTCPIC mounting boards 12a and 12b, the terminals 13a and 13b, and the first terminal 15 are provided.
a, 15b, the wiring pattern on the auxiliary substrate 14, the second terminals 16a, 16b, and the connector electrode 5 are connected. At this time, by properly forming the wiring pattern on the auxiliary substrate 14, the DTCPIC mounting substrate 12a,
It is possible to easily connect a common signal to 12b, and to connect a non-common signal to the DTCPIC mounting boards 12a, 1
It is also easy to connect to only one of 2b.
【００１８】なお、実施例２においては、端子１３ａ、
１３ｂと第１の端子１５ａ、１５ｂとの間、及び第２の
端子１６ａ、１６ｂとコネクタ電極５との間の接続はハ
ンダ付けによったが、他の方法でもよい。In the second embodiment, the terminals 13a,
The connection between 13b and the first terminals 15a and 15b, and between the second terminals 16a and 16b and the connector electrode 5 is by soldering, but other methods may be used.
【００１９】実施例３．図３はこの発明の実施例３を示
す構成図、図４は同じく斜視図である。１７はＤＴＣＰ
ＩＣであるメモリＩＣ、１８ａ、１８ｂはメモリＩＣ１
７が搭載されたメモリＩＣ搭載基板であり、表面及び裏
面には足２にハンダ付けによって接続された配線パター
ンが形成されている。１９ａ、１９ｂはメモリＩＣ搭載
基板１８ａ、１８ｂの端部に設けられた端子である。メ
モリＩＣ搭載基板１８ａ、１８ｂは、端子１９ａ、１９
ｂの位置が図３で上下方向に揃った状態で平行に並べて
配置されている。Example 3. 3 is a configuration diagram showing a third embodiment of the present invention, and FIG. 4 is a perspective view of the same. 17 is DTCP
The memory ICs 18a and 18b, which are ICs, are the memory IC1.
7 is a memory IC mounting substrate on which wiring patterns connected to the legs 2 by soldering are formed on the front and back surfaces. Reference numerals 19a and 19b denote terminals provided at the ends of the memory IC mounting boards 18a and 18b. The memory IC mounting boards 18a, 18b are provided with terminals 19a, 19
The positions of b are aligned in parallel in the vertical direction in FIG.
【００２０】２０ａ、２０ｂは端子１９ａ、１９ｂにハ
ンダ付けによって接続された補助基板、２１はメモリＩ
Ｃ１７用の周辺ＩＣ２２ａ、２２ｂを搭載し、両端部に
第１の端子２３ａ、２３ｂ及び第２の端子２４ａ、２４
ｂを有する周辺ＩＣ搭載基板である。第１の端子２３
ａ、２３ｂは、ハンダ付けによって補助基板２０ａ、２
０ｂに接続されるとともに、周辺ＩＣ２２ａ、２２ｂの
足２ａに周辺ＩＣ搭載基板２１上の配線パターンを介し
て接続されている。第２の端子２４ａ、２４ｂは、周辺
ＩＣ２２ａ、２２ｂの足２ａに周辺ＩＣ搭載基板２１上
の配線パターンを介して接続されるとともに、コネクタ
電極５（従来と同一のもの）にハンダ付けによって接続
されている。Reference numerals 20a and 20b denote auxiliary boards connected to the terminals 19a and 19b by soldering, and 21 denotes a memory I.
The peripheral ICs 22a and 22b for C17 are mounted, and the first terminals 23a and 23b and the second terminals 24a and 24 are provided at both ends.
It is a peripheral IC mounting substrate having b. First terminal 23
a and 23b are auxiliary boards 20a and 2 by soldering.
0b as well as the legs 2a of the peripheral ICs 22a and 22b via a wiring pattern on the peripheral IC mounting board 21. The second terminals 24a and 24b are connected to the legs 2a of the peripheral ICs 22a and 22b via a wiring pattern on the peripheral IC mounting board 21 and are also connected to the connector electrodes 5 (the same as conventional ones) by soldering. ing.
【００２１】次に、図３、図４に示したこの発明の実施
例３の動作について説明する。メモリＩＣ１７と周辺Ｉ
Ｃ２２ａ、２２ｂとの間は、足２、メモリＩＣ搭載基板
１８ａ、１８ｂ上の配線パターン、端子１９ａ、１９
ｂ、補助基板２０ａ、２０ｂ、第１の端子２３ａ、２３
ｂ、周辺ＩＣ搭載基板２１上の配線パターン、及び足２
ａを介して接続される。また、周辺ＩＣ２２ａ、２２ｂ
とコネクタ６との間は、足２ａ、周辺ＩＣ搭載基板２１
上の配線パターン、第２の端子２４ａ、２４ｂ、及びコ
ネクタ電極５を介して接続される。こうして、メモリＩ
Ｃ１７は周辺ＩＣ２２ａ、２２ｂに制御されて機能する
ことになる。このように、メモリＩＣ１７用の基板と周
辺ＩＣ２２ａ、２２ｂ用の基板とを分離すれば、メモリ
容量の変更は、メモリＩＣ搭載基板１８ａ、１８ｂを交
換するだけで容易に行うことができる。Next, the operation of the third embodiment of the present invention shown in FIGS. 3 and 4 will be described. Memory IC 17 and peripheral I
Between C22a and 22b, foot 2, wiring pattern on the memory IC mounting boards 18a and 18b, terminals 19a and 19
b, auxiliary boards 20a, 20b, first terminals 23a, 23
b, the wiring pattern on the peripheral IC mounting substrate 21, and the foot 2
It is connected via a. In addition, peripheral ICs 22a, 22b
Between the connector and the connector 6, the foot 2a and the peripheral IC mounting board 21
Connection is made via the upper wiring pattern, the second terminals 24a and 24b, and the connector electrode 5. Thus, the memory I
The C17 functions under the control of the peripheral ICs 22a and 22b. In this way, by separating the substrate for the memory IC 17 from the substrate for the peripheral ICs 22a and 22b, the memory capacity can be easily changed only by replacing the memory IC mounting substrates 18a and 18b.
【００２２】なお、実施例３においては、端子１９ａ、
１９ｂと補助基板２０ａ、２０ｂとの間等の接続はハン
ダ付けによったが、他の方法でもよい。また、端子１９
ａ、１９ｂと第１の端子２３ａ、２３ｂとの間の接続の
ために補助基板２０ａ、２０ｂを用いたが、他の手段を
用いてもよい。In the third embodiment, the terminals 19a,
Although the connection between 19b and the auxiliary boards 20a and 20b is by soldering, other methods may be used. Also, the terminal 19
Although the auxiliary boards 20a and 20b are used for the connection between the terminals a and 19b and the first terminals 23a and 23b, other means may be used.
【００２３】実施例４．実施例１において、導体から構
成されたパネル２５ａ、２５ｂによって、ＤＴＣＰＩＣ
７、ＤＴＣＰＩＣ搭載基板８ａ、８ｂ、及びＬ字形コネ
クタ電極１０の全体を覆い、さらに、Ｌ字形コネクタ電
極１０のうちＧＮＤ電極１０ａのみをパネル２５ａ、２
５ｂに接続することにより（図５参照）、静電気耐量が
向上する。なお、パネル２５ａ、２５ｂは互いに導通さ
れており、２６は絶縁物から構成されるフレームであ
る。Example 4. In the first embodiment, the DTCPIC is formed by the panels 25a and 25b made of conductors.
7, the DTCPIC mounting boards 8a and 8b, and the L-shaped connector electrode 10 as a whole, and further, only the GND electrode 10a of the L-shaped connector electrode 10 is covered by the panels 25a, 2
By connecting to 5b (see FIG. 5), the electrostatic withstand capability is improved. The panels 25a and 25b are electrically connected to each other, and 26 is a frame made of an insulating material.
【００２４】[0024]
【発明の効果】以上のように、この発明の請求項１のＩ
Ｃカードによれば、ＤＴＣＰＩＣを搭載し、ＤＴＣＰＩ
Ｃに接続されたスルーホールを端部に有し、スルーホー
ルの位置が揃った状態で平行に並べて配置された複数の
ＤＴＣＰＩＣ搭載基板と、Ｌ字形の形状をなし、導体か
ら構成され、一端が複数のＤＴＣＰＩＣ搭載基板の各ス
ルーホールに貫通状態で接続されたＬ字形コネクタ電極
と、Ｌ字形コネクタ電極の他端が接続されたＬ字形電極
用コネクタとを備えたので、厚さを一定値内に収めつ
つ、大容量化等の高機能化を図ることができるＩＣカー
ドが得られる効果がある。As described above, according to claim 1 of the present invention,
According to C card, DTCPIC is installed and DTCPI
It has a plurality of DTCPIC mounting boards that have through holes connected to C at their ends and are arranged in parallel in a state where the positions of the through holes are aligned with each other. Since the L-shaped connector electrode connected to each through hole of the plurality of DTCPIC mounting boards in a penetrating state and the L-shaped electrode connector to which the other end of the L-shaped connector electrode is connected, the thickness is kept within a certain value. In addition to the above, there is an effect that an IC card capable of achieving high functionality such as large capacity can be obtained.
【００２５】この発明の請求項２のＩＣカードによれ
ば、ＤＴＣＰＩＣを搭載し、ＤＴＣＰＩＣに接続された
端子を端部に有し、平行に並べて配置された２枚のＤＴ
ＣＰＩＣ搭載基板と、両端部に配置された第１の端子及
び第２の端子を有し、第１の端子は２枚のＤＴＣＰＩＣ
搭載基板の各端子に接続され、第１の端子と第２の端子
との間は導通されている補助基板と第２の端子が接続さ
れたコネクタとを備えたので、厚さを一定値内に収めつ
つ、大容量化等の高機能化を図ることができるＩＣカー
ドが得られる効果がある。According to the IC card of claim 2 of the present invention, two DTs mounted with the DTCPIC, having terminals connected to the DTCPIC at their ends and arranged side by side in parallel
It has a CPIC mounting board and a first terminal and a second terminal arranged at both ends, and the first terminal has two DTCPICs.
Since the auxiliary board, which is connected to each terminal of the mounting board and is electrically connected between the first terminal and the second terminal, and the connector to which the second terminal is connected are provided, the thickness is kept within a certain value. In addition to the above, there is an effect that an IC card capable of achieving high functionality such as large capacity can be obtained.
【００２６】この発明の請求項３のＩＣカードによれ
ば、ＤＴＣＰＩＣであるメモリＩＣを搭載し、メモリＩ
Ｃに接続された端子を端部に有し、平行に並べて配置さ
れた複数のメモリＩＣ搭載基板と、メモリＩＣ用の周辺
ＩＣを搭載し、周辺ＩＣに接続されるとともに両端部に
配置された第１の端子及び第２の端子を有し、第１の端
子は複数のメモリＩＣ搭載基板の各端子に接続されてい
る周辺ＩＣ搭載基板と、第２の端子が接続されるコネク
タとを備えたので、厚さを一定値内に収めつつ、大容量
化等の高機能化を図ることができるとともに、メモリ容
量の変更は、メモリＩＣ搭載基板を交換するだけで容易
に行うことができるＩＣカードが得られる効果がある。According to the IC card of claim 3 of the present invention, the memory IC which is the DTCP IC is mounted, and the memory I
A plurality of memory IC mounting boards having terminals connected to C at their ends and arranged side by side in parallel, and peripheral ICs for memory ICs were mounted, connected to the peripheral ICs and arranged at both ends. It has a first terminal and a second terminal, and the first terminal includes a peripheral IC mounting board connected to each terminal of the plurality of memory IC mounting boards, and a connector to which the second terminal is connected. Therefore, while the thickness can be kept within a certain value, high functionality such as large capacity can be achieved, and the memory capacity can be easily changed only by replacing the memory IC mounting board. There is an effect that you can get a card.
【００２７】この発明の請求項４のＩＣカードによれ
ば、ＤＴＣＰＩＣ、ＤＴＣＰＩＣ搭載基板、及びＬ字形
コネクタ電極の全体を覆い、導体から構成されたパネル
を備え、Ｌ字形コネクタ電極のうちのＧＮＤ電極のみを
パネルに接続したので、厚さを一定値内に収めつつ、大
容量化等の高機能化を図ることができるとともに、静電
気耐量が向上するＩＣカードが得られる効果がある。According to the IC card of claim 4 of the present invention, the DTCPIC, the DTCPIC mounting substrate, and the L-shaped connector electrode are entirely covered with a panel formed of a conductor, and the GND electrode of the L-shaped connector electrodes is provided. Since only the panel is connected to the panel, it is possible to obtain an IC card that can achieve high functionality such as a large capacity while keeping the thickness within a fixed value and that can improve the electrostatic withstand capability.
【図１】この発明の実施例１を示す構成図である。FIG. 1 is a configuration diagram showing a first embodiment of the present invention.
【図２】この発明の実施例２を示す構成図である。FIG. 2 is a configuration diagram showing a second embodiment of the present invention.
【図３】この発明の実施例３を示す構成図である。FIG. 3 is a configuration diagram showing a third embodiment of the present invention.
【図４】この発明の実施例３を示す斜視図である。FIG. 4 is a perspective view showing a third embodiment of the present invention.
【図５】この発明の実施例４を示す構成図である。FIG. 5 is a configuration diagram showing a fourth embodiment of the present invention.
【図６】従来のＩＣカードを示す構成図である。FIG. 6 is a configuration diagram showing a conventional IC card.
６ コネクタ ７ ＤＴＣＰＩＣ ８ａ、８ｂ ＤＴＣＰＩＣ搭載基板 ９ａ、９ｂ スルーホール １０ Ｌ字形コネクタ電極 １０ａ ＧＮＤ電極 １１ Ｌ字形電極用コネクタ １２ａ、１２ｂ ＤＴＣＰＩＣ搭載基板 １３ａ、１３ｂ 端子 １４ 補助基板 １５ａ、１５ｂ 第１の端子 １６ａ、１６ｂ 第２の端子 １７ メモリＩＣ １８ａ、１８ｂ メモリＩＣ搭載基板 １９ａ、１９ｂ 端子 ２１ 周辺ＩＣ搭載基板 ２２ａ、２２ｂ 周辺ＩＣ ２３ａ、２３ｂ 第１の端子 ２４ａ、２４ｂ 第２の端子 ２５ａ、２５ｂ パネル 6 connector 7 DTCPIC 8a, 8b DTCPIC mounting substrate 9a, 9b through hole 10 L-shaped connector electrode 10a GND electrode 11 L-shaped electrode connector 12a, 12b DTCPIC mounting substrate 13a, 13b terminal 14 auxiliary substrate 15a, 15b first terminal 16a , 16b Second terminal 17 Memory IC 18a, 18b Memory IC mounting board 19a, 19b Terminal 21 Peripheral IC mounting board 22a, 22b Peripheral IC 23a, 23b First terminal 24a, 24b Second terminal 25a, 25b Panel
Claims (4)
Ｃに接続されたスルーホールを端部に有し、前記スルー
ホールの位置が揃った状態で平行に並べて配置された複
数のＤＴＣＰＩＣ搭載基板と、 Ｌ字形の形状をなし、導体から構成され、一端が前記複
数のＤＴＣＰＩＣ搭載基板の各前記スルーホールに貫通
状態で接続されたＬ字形コネクタ電極と、 前記Ｌ字形コネクタ電極の他端が接続されたＬ字形電極
用コネクタと、を備えたＩＣカード。1. A DTCPIC is mounted, and the DTCPI is installed.
A plurality of DTCPIC mounting boards, which have through holes connected to C at their ends and are arranged in parallel in a state where the positions of the through holes are aligned; Is an IC card including an L-shaped connector electrode connected to each of the through holes of the plurality of DTCPIC mounting substrates in a penetrating state, and an L-shaped electrode connector to which the other end of the L-shaped connector electrode is connected.
Ｃに接続された端子を端部に有し、平行に並べて配置さ
れた２枚のＤＴＣＰＩＣ搭載基板と、 両端部にそれぞれ配置された第１の端子及び第２の端子
を有し、前記第１の端子は前記２枚のＤＴＣＰＩＣ搭載
基板の各前記端子に接続され、前記第１の端子と前記第
２の端子との間は導通されている補助基板と、 前記第２の端子が接続されたコネクタと、を備えたＩＣ
カード。2. A DTCPIC is mounted, and the DTCPI is installed.
The two DTCPIC mounting boards, which have terminals connected to C at their ends and are arranged side by side in parallel, and the first and second terminals respectively arranged at both ends, Is connected to each of the terminals of the two DTCPIC mounting boards, and the second terminal is connected to an auxiliary board that is electrically connected between the first terminal and the second terminal. An IC including a connector
card.
し、前記メモリＩＣに接続された端子を端部に有し、平
行に並べて配置された複数のメモリＩＣ搭載基板と、 前記メモリＩＣ用の周辺ＩＣを搭載し、前記周辺ＩＣに
接続されるとともに両端部に配置された第１の端子及び
第２の端子を有し、前記第１の端子は前記複数のメモリ
ＩＣ搭載基板の各前記端子に接続されている周辺ＩＣ搭
載基板と、 前記第２の端子が接続されるコネクタと、を備えたＩＣ
カード。3. A plurality of memory IC mounting boards mounted with a memory IC, which is a DTCPIC, having terminals connected to the memory IC at their ends and arranged in parallel, and peripheral ICs for the memory IC. And having a first terminal and a second terminal connected to the peripheral IC and arranged at both ends, and the first terminal is connected to each of the terminals of the plurality of memory IC mounting boards. Provided with a peripheral IC mounting substrate and a connector to which the second terminal is connected
card.
及びＬ字形コネクタ電極の全体を覆い、導体から構成さ
れたパネルを備え、 Ｌ字形コネクタ電極のうちのＧＮＤ電極のみを前記パネ
ルに接続したことを特徴とする請求項１記載のＩＣカー
ド。4. A DTCPIC, a DTCPIC mounting board,
2. The IC card according to claim 1, further comprising: a panel which covers the entire L-shaped connector electrode and is made of a conductor, and only the GND electrode of the L-shaped connector electrode is connected to the panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04134913A JP3098854B2 (en) | 1992-05-27 | 1992-05-27 | IC card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04134913A JP3098854B2 (en) | 1992-05-27 | 1992-05-27 | IC card |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06286372A true JPH06286372A (en) | 1994-10-11 |
| JP3098854B2 JP3098854B2 (en) | 2000-10-16 |
Family
ID=15139466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04134913A Expired - Fee Related JP3098854B2 (en) | 1992-05-27 | 1992-05-27 | IC card |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3098854B2 (en) |
-
1992
- 1992-05-27 JP JP04134913A patent/JP3098854B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3098854B2 (en) | 2000-10-16 |
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