JPH02224363A - Pin grid array integrated circuit case - Google Patents

Abstract

PURPOSE:To double an integrated circuit in mounting density so as to make the delay time difference of signal negligibly small by a method wherein holes whose diameter and pitch are the same as those of pins are bored in a circuit case of this design surrounding the pin in such a manner that the hole is equally distant from the pins adjacent to each other, and the pins of the same type of a pin grid array integrated circuit case can be inserted into the holes concerned. CONSTITUTION:Holes whose diameter and pitch are the same as those of pins are bored in a circuit case of this design surrounding the pin in such a manner that the hole is equally distant from the pins adjacent to each other, and the pins of the same type of a pin grid array integrated circuit case can be inserted into the holes concerned. For instance, holes 2 whose diameter and pitch are the same as those of pins 3 are provided surrounding the pin. A second case 1B is mounted deviating from a first case 1A by a distance between the pin 3 and the hole 2. Therefore, a two-stage mounting can be realized. By this setup, an integrated circuit of this design can be improved in mounting density and a signal delay time difference can be made negligibly small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pin grid array integrated circuit case, particularly to a pin grid array integrated circuit case for two-stage mounting.

[Conventional technology]

A conventional pin grid array integrated circuit case will be described in detail with reference to the drawings.

FIGS. 3(a) and 3(b) are a sectional view and a plan view including an example of a conventional pin grid array integrated circuit case.

The cases 10 are arranged and mounted on the printed circuit board 9 one step at a time.

[Problem to be solved by the invention]

The conventional pin grid array integrated circuit case mentioned above is
The disadvantage was that the packaging density was low and the difference in signal delay time could not be ignored.

[Means to solve the problem]

In the pin grid array integrated circuit case of the present invention, holes with the same diameter and the same spacing as the pins are bored at the same distance as the adjacent pins and so as to enclose the pins, and the pins of the pin grid array integrated circuit case of the same type are penetrated into the holes. This made it possible.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a sectional view and a plan view showing an embodiment of the present invention.

In the pin grid array integrated circuit case shown in FIGS. 1(a) and 1(b), holes 2 having the same diameter and the same spacing as the pins 3 are formed so as to surround the pins 3.

FIGS. 2(a) and 2(b) are a sectional view and a plan view showing an example of use of the present invention.

The second case IB is repin 3 from the first case IA.
and are mounted shifted by the distance of the through hole 2. This allows two-stage mounting.

〔Effect of the invention〕

The pin grid array integrated circuit case of the present invention has the effect of doubling the packaging density and making the difference in signal delay times negligible.

...Insulating substrate, 5...Integrated circuit, 6.
...Cover, 7...Connection line, 8...
...Conductor pattern, 9...Printed circuit board.

Claims (1)

[Claims] A pin grid array integrated circuit characterized in that holes with the same diameter and the same spacing as the pins are bored at the same distance as adjacent pins and so as to surround the pins, and the pins of a pin grid array integrated circuit case of the same type can pass through the holes. Case.