JPH06283653A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06283653A
JPH06283653A JP5092468A JP9246893A JPH06283653A JP H06283653 A JPH06283653 A JP H06283653A JP 5092468 A JP5092468 A JP 5092468A JP 9246893 A JP9246893 A JP 9246893A JP H06283653 A JPH06283653 A JP H06283653A
Authority
JP
Japan
Prior art keywords
wiring
wires
wire
bonding
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5092468A
Other languages
Japanese (ja)
Inventor
Norio Nitta
法生 新田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP5092468A priority Critical patent/JPH06283653A/en
Publication of JPH06283653A publication Critical patent/JPH06283653A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/225Correcting or repairing of printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a wiring mounting technique which can be applied to the COB by only changing the bonder program on a bonding device. CONSTITUTION:When it becomes necessary to increase the number of wires after wiring the wires on a printed wiring board, insulated bonding wires 30 are lengthily hung down onto the wiring board and the wires 30 are ball-bonded to electrode pads 23 and 25 on the printed wiring board. The jumper line which has been used conventionally at the time of modifying wiring can be used in a small mounting area on a bonding device by using the insulated wires 30 and the remaking work of the printed wiring board for changing the wiring can be minimized and the occupying space of the wiring can be reduced. In addition, the wiring can be performed in a short time, because the wiring length of this semiconductor device is reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体実装法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting method.

【0002】[0002]

【従来の技術】従来、プリント配線板上に集積回路素子
を構成しているような半導体装置では装置自体、開発当
初から正常動作することは希で、正常に動作させるため
の変更操作が多少なりとも存在する。搭載素子の変更や
回路配線の変更等によって正常動作させるべく改良を行
っていく。特に配線の変更を行うためには回路基板上の
改良のための任意の電極端子間を電気的な接触なしで結
ぶためにプリント基板上で暴露していても十分な耐侯性
が得られる被覆された導線によってプリント配線上を新
たにプリント配線に替わる回路線を形成する。この被覆
電線を一般にジャンパー線と呼ぶ。ジャンパー線による
配線修復等を行い、正常動作を確認した後再びプリント
配線板を作り直すのが一般的な手法であった。
2. Description of the Related Art Conventionally, in a semiconductor device having an integrated circuit element formed on a printed wiring board, the device itself rarely operates normally from the beginning of development, and some change operations are required to operate the device normally. Also exists. Improvements will be made to ensure normal operation by changing the mounted elements and circuit wiring. In particular, in order to change the wiring, it is possible to connect any electrode terminals for improvement on the circuit board without electrical contact so that even if exposed on the printed circuit board, sufficient weather resistance can be obtained. A circuit line that replaces the printed wiring is newly formed on the printed wiring by the conductive wire. This covered electric wire is generally called a jumper wire. It was a general method to repair the wiring with a jumper wire, confirm the normal operation, and then remake the printed wiring board.

【0003】[0003]

【発明が解決しようとする課題】近年では半導体集積回
路素子をパッケージングせずにベアチップで直接回路基
板上に載せ、ボンディングワイヤーやTAB(Tape Aut
omated Bonding)等で配線するチップオンボード(CO
B、Chip On Board )技術を使った半導体装置が体積効
率や動作速度の点等で注目されるようになった。コンピ
ュータの高性能化(高速、多機能化)を達成させるため
の動作周波数のさらなる高周波化、通信の高速化、暗号
化に伴う高速で高度な処理が集積回路(DSP、Digita
l Signal Processor、等)に求められ、パッケージに使
用されるリードフレームの配線ですら信号の遅延が問題
になっているほどである。機能を集約して、配線長
小化した大面積集積回路チップが理想であるが、半導体
集積回路作成上、面積に反比例する歩留まりの関係から
複数集積回路チップの組み合わせに頼らざるを得ないの
が現状である。それ故、できる限り集積回路素子間の距
離を短く配線した機能集合体としてのモジュール化され
た素子として、ベアチップを高密度で配置、配線した実
装技術が要求されている。しかし、実装後の補修(リペ
ア)作業、とくに素子部品交換や上記のジャンパー線等
による正常動作のための措置は微小面積での作業を必要
とするCOB技術には未だ困難な問題として残っている
のが現実である。
In recent years, a semiconductor integrated circuit element is directly mounted on a circuit board by a bare chip without packaging, and a bonding wire or a TAB (Tape Aut) is formed.
Chip-on-board (CO
B, semiconductor devices using Chip On Board technology have come to the fore in terms of volume efficiency and operating speed. Higher operating frequency to achieve higher performance (higher speed, more functions) of computers, higher speed of communication, high speed and advanced processing associated with encryption are integrated circuits (DSP, Digita
signal processor, etc.), even the wiring of the lead frame used for the package is such that signal delay is a problem. To aggregate function, but the wiring length large area integrated circuit chips outermost <br/> ginger is ideal, relying semiconductor integrated circuit creation, from the relationship of the yield is inversely proportional to the area on a combination of multiple integrated circuit chips The current situation is unavoidable. Therefore, there is a demand for a mounting technique in which bare chips are arranged and wired at a high density as a modularized device as a functional assembly in which the distance between integrated circuit devices is wired as short as possible. However, the repair work after mounting, especially the replacement of the element parts and the measures for the normal operation by the jumper wires, etc., still remain as a difficult problem in the COB technology which requires work in a small area. Is the reality.

【0004】この発明は、上記した従来のリペア技術の
一環として、ボンディング装置上でのボンダープログラ
ムの変更のみでCOBに使用でき得る配線実装技術を提
供するものである。
As a part of the above-mentioned conventional repair technique, the present invention provides a wiring mounting technique which can be used for COB only by changing a bonder program on a bonding apparatus.

【0005】[0005]

【課題を解決するための手段】この発明の実施には、通
常のボンディング装置を特別な改造をせずに、ワイヤー
間や配線基板と接触しても十分な絶縁耐力をもち、裸金
ワイヤーと同程度の接合性をもつ絶縁被覆ワイヤーを配
線基板上のミクロなジャンパー線として使用する。ジャ
ンパー線として使用するボンディングワイヤーは直径1
0μm〜50μmで、絶縁被覆の厚みはワイヤー径の1
%〜5%が望ましい。汎用ボンディング装置を使用する
ことによって再プログラム可能な実装レベルの配線作業
を行う。
In order to carry out the present invention, the ordinary bonding apparatus has a sufficient dielectric strength even when it is brought into contact with wires or a wiring board without special modification, and a bare gold wire is used. Insulated wires with similar bondability are used as micro jumper wires on the wiring board. Bonding wire used as a jumper wire has a diameter of 1
0 μm to 50 μm, the thickness of the insulation coating is 1 of the wire diameter.
% To 5% is desirable. Perform reprogrammable mounting level wiring work by using a general purpose bonding machine.

【0006】[0006]

【作用】短絡の危険性のない絶縁被覆ワイヤーによるジ
ャンパー配線をプリント配線基板上に配線すれば、ボン
ディング装置上での回路修復ができ、従来集積回路素子
の微小電極端子をプリント配線で取り扱えるピッチの配
線に取り出す空間でしかなかった実装レベルでの変更が
できることになる。さらに、プリント配線板上に既に張
られている絶縁被覆ワイヤーの上からツールによってワ
イヤーを切断せずに被覆を破壊する程度の圧着を行う
か、ボールボンディングやウェッジボンディングを行っ
て金ボールや金ワイヤーによる被覆破壊とプリント板上
への圧着を行えば基板上電極とのコンタクトがとれて電
気信号の分岐ができる。ボンダーのプログラム変更だけ
で行うことのできるボンディングワイヤーと同じ実装ス
ケールでの素早い回路配線変更は半導体装置の特に配線
変更にともなうプリント板試作開発期間を大幅に削減
し、プリント板上配線の大きな変更が行われることのな
い製品は薄型、小型化を容易に達成し、プリント配線基
板の限界にとらわれずに実装レベルでの性能向上に貢献
する。
[Function] If jumper wiring with an insulation coating wire that does not cause a short circuit is wired on the printed wiring board, the circuit can be repaired on the bonding device, and the fine electrode terminals of the conventional integrated circuit element can be handled by the printed wiring. It will be possible to make changes at the mounting level, which was only available in the wiring space. Furthermore, the insulation coated wire already stretched on the printed wiring board is crimped to the extent that the coating is destroyed without cutting the wire with a tool, or ball bonding or wedge bonding is used to perform gold ball or gold wire. If the coating is destroyed and pressure is applied to the printed board, the contact with the electrode on the board is made and the electric signal can be branched. A quick circuit wiring change at the same mounting scale as the bonding wire that can be done only by changing the program of the bonder drastically reduces the development period of the printed circuit board prototype, especially with the wiring change of the semiconductor device. Products that are never manufactured can easily achieve thinness and miniaturization, and contribute to performance improvement at the mounting level without being bound by the limits of printed wiring boards.

【0007】[0007]

【実施例】以下本発明を実施例に従って説明する。 (実施例1)図1はCOB実装したマルチチップモジュ
ールの配線修正をしたときの概略図である。図1に示す
マルチチップモジュールは、ICベアチップ11と、そ
のICベアチップに設けられたIC電極パッド12と、
プリント板上電極パッド13と、ボンディングワイヤー
14と、修正用絶縁被覆ボンディングワイヤー15とを
有する。30μmφ、ポリアリレート0.46μmの被
覆厚みの絶縁被覆金ボンディングワイヤー15を使用し
てプリント板上の電極パッド13,13間を配線するこ
とにより、ベアチップ実装されたマルチチップモジュー
ルの配線変更を行った(図1)。従来廃棄していた配線
変更の必要のあるCOB実装でのマルチチップモジュー
ルを配線変更し、同時に全体の大きさを変える事なしで
実現した。
EXAMPLES The present invention will be described below with reference to examples. (Embodiment 1) FIG. 1 is a schematic view of a COB-mounted multichip module in which wiring is corrected. The multi-chip module shown in FIG. 1 includes an IC bare chip 11, an IC electrode pad 12 provided on the IC bare chip,
It has an electrode pad 13 on a printed board, a bonding wire 14, and a correction insulating coating bonding wire 15. The wiring of the multi-chip module mounted on the bare chip was changed by wiring between the electrode pads 13 and 13 on the printed board using the insulating coated gold bonding wire 15 having a coating thickness of 30 μmφ and polyarylate 0.46 μm. (Figure 1). This was achieved without changing the wiring of the COB-mounted multichip module that had to be changed, which was previously discarded, and at the same time changing the overall size.

【0008】(実施例2)図2はプリント配線板上の絶
縁被覆ワイヤーに配線した概略図である。図2に示すマ
ルチチップモジュールはIC121と、IC1上に設け
られたIC電極パッド22と、絶縁被覆ワイヤー固定用
電極パッド23と、ボールボンディング24と、信号取
り出し用電極パッド25と、分岐されたプリント配線2
6と、中継共通電極パッド27と、IC229と、IC
2上に設けられたIC2電極パッド28と、絶縁被覆ボ
ンディングワイヤー30とを有する。プリント配線板上
に後から配線を増やす必要が生じたため、実施例1と同
様な絶縁被覆ボンディングワイヤー30を基板上に長く
垂らし、絶縁被覆ボンディングワイヤー30とプリント
板上の電極パッド23,25とをボールボンディングし
た。第1ボンディングによってボール押しつけにより絶
縁被覆破壊、接合し、ワイヤーをボール直上で切断、電
気的接触とワイヤーの固定を同時に行うことによって配
線した(図2)。
(Embodiment 2) FIG. 2 is a schematic view of wiring on an insulating coating wire on a printed wiring board. The multi-chip module shown in FIG. 2 includes an IC 121, an IC electrode pad 22 provided on the IC 1, an insulating coating wire fixing electrode pad 23, a ball bonding 24, a signal extracting electrode pad 25, and a branched print. Wiring 2
6, relay common electrode pad 27, IC 229, IC
2 has an IC2 electrode pad 28 and an insulating coating bonding wire 30. Since it was necessary to increase the number of wirings on the printed wiring board later, the same insulating coating bonding wire 30 as in Example 1 was hung on the substrate for a long time to separate the insulating coating bonding wire 30 and the electrode pads 23, 25 on the printed board. Ball bonded. The insulation coating was broken and joined by pressing the ball by the first bonding, the wire was cut immediately above the ball, and electrical contact and fixing of the wire were performed at the same time for wiring (FIG. 2).

【0009】[0009]

【発明の効果】以上説明したように本発明によれば絶縁
被覆されたワイヤーによる半導体装置の実装レベルにお
いてボンダーのプログラムレベルにおける柔軟な配線変
更が信号遅延をもたらすような大きく外部に線路を引き
出す配線を設けなくとも実現でき、また、プリント配線
に替わって30μmφ程度のボンディングワイヤーレベ
ルでの配線が容易にでき、COB技術のより汎用的な適
用と半導体装置の高速、高機能、小型化をもたらす。
As described above, according to the present invention, in the mounting level of the semiconductor device by the wire covered with the insulation, the flexible wiring change at the program level of the bonder causes the signal delay, and the wiring is largely drawn to the outside. Can be realized without providing the wiring, and the wiring at the bonding wire level of about 30 μmφ can be easily replaced in place of the printed wiring, which brings about a more general application of the COB technology and a higher speed, higher performance and smaller size of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】COB実装したマルチチップモジュールの配線
修正をしたときの概略図である。
FIG. 1 is a schematic view of a COB-mounted multichip module when wiring is corrected.

【図2】プリント配線板上の絶縁被覆ワイヤーに配線し
た概略図である。
FIG. 2 is a schematic view of wiring on an insulation-coated wire on a printed wiring board.

【符号の説明】[Explanation of symbols]

11 ICベアチップ 12 IC電極パッド 13 プリント板上電極パッド 14 ボンディングワイヤー 15 修正用絶縁被覆ボンディングワイヤー 21 IC1 22 IC1電極パッド 23 絶縁被覆ワイヤー固定用電極パッド 24 ボールボンディング 25 信号取り出し用電極パッド 26 分岐されたプリント配線 27 中継共通電極パッド 28 IC2電極パッド 29 IC2 30 絶縁被覆ボンディングワイヤー 11 IC Bare Chip 12 IC Electrode Pad 13 Electrode Pad on Printed Board 14 Bonding Wire 15 Insulation Coating Bonding Wire for Correction 21 IC1 22 IC1 Electrode Pad 23 Insulation Coating Wire Fixing Electrode Pad 24 Ball Bonding 25 Signal Extraction Electrode Pad 26 Branched Printed wiring 27 Relay common electrode pad 28 IC2 electrode pad 29 IC2 30 Insulation coating bonding wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 回路基板上に電極端子間を接続するジャ
ンパー線として絶縁被覆ワイヤーを使用して配線実装し
た半導体装置。
1. A semiconductor device mounted on a circuit board by using an insulating coating wire as a jumper wire for connecting between electrode terminals.
【請求項2】 絶縁被覆ワイヤーをジャンパー線として
使用し、ワイヤーボンディング装置で実装を行う方法。
2. A method of using an insulation-coated wire as a jumper wire for mounting with a wire bonding device.
JP5092468A 1993-03-25 1993-03-25 Semiconductor device Pending JPH06283653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5092468A JPH06283653A (en) 1993-03-25 1993-03-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5092468A JPH06283653A (en) 1993-03-25 1993-03-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06283653A true JPH06283653A (en) 1994-10-07

Family

ID=14055177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5092468A Pending JPH06283653A (en) 1993-03-25 1993-03-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06283653A (en)

Similar Documents

Publication Publication Date Title
US4916519A (en) Semiconductor package
US6169331B1 (en) Apparatus for electrically coupling bond pads of a microelectronic device
US20030230805A1 (en) Semiconductor device and manufacturing method thereof
JPH0455341B2 (en)
US7638862B2 (en) Die attach paddle for mounting integrated circuit die
US20040152242A1 (en) Device package utilizing interconnect strips to make connections between package and die
JP2004349397A (en) Semiconductor device and lead frame used therefor
JPH06283653A (en) Semiconductor device
JP3316450B2 (en) Semiconductor device
JP4007917B2 (en) Semiconductor device and manufacturing method thereof
JPH05326817A (en) Multichip package
JPH06314720A (en) Semiconductor mounting substrate
JPH118260A (en) Manufacture of resin-sealed type semiconductor device
JPH0778903A (en) Method of bias voltage application in hybrid integrated circuit
JP2755032B2 (en) Semiconductor device
JP3249263B2 (en) Semiconductor package and manufacturing method thereof
JPH022289B2 (en)
JP2001053195A (en) Method for manufacturing semiconductor device
JPH03265148A (en) Semiconductor device and manufacture thereof
JPH05102223A (en) Manufacture of semiconductor device
TW530397B (en) Multi-chip module packaging process
JP2992408B2 (en) IC package and its mounting structure
KR20070057452A (en) Printed circuit board having dummy circuit pattern for semiconductor package using semiconductor chip with center pad
JPH08213537A (en) Lead frame structure and semiconductor device provided therewith
JPH10242189A (en) Semiconductor device, manufacture thereof, ic chip mounting structure and heating piece for wire bonding

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19981209