JPH06283371A - Manufacture of layered ceramic electronic components - Google Patents
Manufacture of layered ceramic electronic componentsInfo
- Publication number
- JPH06283371A JPH06283371A JP6779593A JP6779593A JPH06283371A JP H06283371 A JPH06283371 A JP H06283371A JP 6779593 A JP6779593 A JP 6779593A JP 6779593 A JP6779593 A JP 6779593A JP H06283371 A JPH06283371 A JP H06283371A
- Authority
- JP
- Japan
- Prior art keywords
- internal electrodes
- internal
- electrode
- sintered body
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/05—Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes
- H10N30/053—Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes by integrally sintering piezoelectric or electrostrictive bodies and electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/06—Forming electrodes or interconnections, e.g. leads or terminals
- H10N30/067—Forming single-layered electrodes of multilayered piezoelectric or electrostrictive parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/50—Piezoelectric or electrostrictive devices having a stacked or multilayer structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/06—Forming electrodes or interconnections, e.g. leads or terminals
- H10N30/063—Forming interconnections, e.g. connection electrodes of multilayered piezoelectric or electrostrictive parts
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、内部電極を介してセラ
ミック層が積層されている積層セラミック電子部品の製
造方法に関し、特に、内部電極形成工程及び内部電極と
外部電極との間の絶縁を確保するための工程が改良され
た積層セラミック電子部品の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated ceramic electronic component in which ceramic layers are laminated via internal electrodes, and more particularly to an internal electrode forming step and insulation between internal electrodes and external electrodes. The present invention relates to a method for manufacturing a monolithic ceramic electronic component having an improved manufacturing process.
【０００２】[0002]
【従来の技術】周知のように、積層コンデンサや積層型
圧電アクチュエータのように、内部電極を間に介して複
数のセラミック層を積層してなる積層セラミック電子部
品が種々の用途で用いられている。この種の積層セラミ
ック電子部品の製造方法を、積層コンデンサを例にとり
説明する。2. Description of the Related Art As is well known, a laminated ceramic electronic component such as a laminated capacitor or a laminated piezoelectric actuator, which is formed by laminating a plurality of ceramic layers via internal electrodes, is used for various purposes. . A method of manufacturing this type of monolithic ceramic electronic component will be described taking a monolithic capacitor as an example.
【０００３】従来の一般的な積層コンデンサの製造方法
では、矩形のセラミックグリーンシートの一方主面上
に、一方端縁から他方端縁側に向かって延び、但し他方
端縁側には至らないようにギャップ領域を残して導電ペ
ーストを印刷する。次に、上記導電ペーストが印刷され
た複数のセラミックグリーンシートを、上記ギャップ領
域が厚み方向に交互に位置するように積層し、積層体を
得る。しかる後、積層体を厚み方向に圧着した後、焼成
することにより焼結体を得、焼結体の一対の対向側面に
それぞれ外部電極を形成する。このようにして、内部電
極が厚み方向において一層おきに一対の対向側面に形成
された外部電極に交互に電気的に接続された積層コンデ
ンサが得られる。In a conventional general method for manufacturing a multilayer capacitor, a gap is formed on one main surface of a rectangular ceramic green sheet so as to extend from one edge toward the other edge but not to the other edge. The conductive paste is printed leaving the area. Next, a plurality of ceramic green sheets on which the conductive paste is printed are laminated so that the gap regions are alternately located in the thickness direction to obtain a laminated body. Then, the laminated body is pressure-bonded in the thickness direction and then fired to obtain a sintered body, and external electrodes are formed on the pair of opposed side surfaces of the sintered body. In this way, a multilayer capacitor is obtained in which the internal electrodes are alternately electrically connected to the external electrodes formed on the pair of opposite side surfaces alternately in the thickness direction.
【０００４】しかしながら、上記製造方法では、内部電
極がセラミックグリーンシート上に導電ペーストを印刷
することにより形成されていたため、内部電極と、その
内部電極が電気的に接続されてはならない外部電極との
間のギャップ領域を精度よくコントロールすることが困
難であった。その結果、ギャップ領域の幅、すなわち内
部電極と他方側の外部電極との間の距離を大きくせざる
を得ず、外部電極の先端において歪み応力が集中しが
ちであること並びにより一層の小型化を図ることがで
きないこと、等の問題があった。However, in the above manufacturing method, since the internal electrode is formed by printing the conductive paste on the ceramic green sheet, the internal electrode and the external electrode which should not be electrically connected to the internal electrode are formed. It was difficult to control the gap area between them with high accuracy. As a result, the width of the gap region, that is, the distance between the internal electrode and the external electrode on the other side must be increased, and strain stress tends to concentrate at the tip of the external electrode, and further miniaturization. There was a problem such as not being able to plan.
【０００５】他方、特開平２−２２４３１１号には、焼
結体を電気化学的な方法でエッチングして溶解除去する
ことにより、上記ギャップ領域を形成し、ギャップ領域
の幅を高精度にコントロールし得る方法が提案されてい
る。すなわち、この方法では、セラミックグリーンシー
ト上の全面に導電ペーストを印刷して内部電極を形成
し、次に、導電ペーストが印刷された複数枚のセラミッ
クグリーンシートを積層して積層体を得る。さらに、上
記積層体を焼結した後に、焼結体の一対の対向側面にお
いて、最終的にその対向側面に露出させるべきでない内
部電極について電気化学的にエッチングし、内部電極の
露出されていた部分及びその近傍を溶解除去して空隙を
形成する。さらに、該空隙に合成樹脂等の絶縁性材料を
充填し、しかる後一対の対向側面に、それぞれ、外部電
極を形成する方法が開示されている。On the other hand, in Japanese Patent Laid-Open No. 2-224311, the gap region is formed by etching and removing the sintered body by an electrochemical method to control the width of the gap region with high accuracy. How to get it is proposed. That is, in this method, a conductive paste is printed on the entire surface of the ceramic green sheet to form internal electrodes, and then a plurality of ceramic green sheets printed with the conductive paste are laminated to obtain a laminate. Furthermore, after sintering the above-mentioned laminated body, at a pair of opposed side surfaces of the sintered body, an internal electrode that should not be finally exposed to the opposed side surfaces is electrochemically etched to expose the exposed internal electrode portion. And its vicinity are dissolved and removed to form voids. Further, a method is disclosed in which the voids are filled with an insulating material such as synthetic resin, and then external electrodes are respectively formed on the pair of opposed side surfaces.
【０００６】[0006]
【発明が解決しようとする課題】特開平２−２２４３１
１号に開示されている方法では、上記のように焼結体の
一対の対向側面に露出している内部電極を、電気化学的
方法でエッチングして空隙を形成するものであるため、
上記ギャップ領域を狭くすることができる。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the method disclosed in No. 1, the internal electrodes exposed on the pair of opposed side surfaces of the sintered body as described above are etched by an electrochemical method to form voids.
The gap region can be narrowed.
【０００７】しかしながら、導電ペーストを印刷し、セ
ラミックスの焼成に際して該導電ペーストを焼き付ける
ことにより電極を形成するものであるため、電極材料の
連続性が十分でなく、内部電極の先端のギャップ領域に
臨む端縁の平滑性が必ずしも十分なものとはならなかっ
た。従って、ギャップ領域の幅を狭めた焼結体を得よう
とした場合、充填された絶縁材料の一部において電界集
中が生じやすく、絶縁破壊を引き起こしやすいという問
題があった。However, since the electrodes are formed by printing the conductive paste and baking the conductive paste when firing the ceramics, the continuity of the electrode material is not sufficient and the gap area at the tip of the internal electrode is encountered. The smoothness of the edges was not always sufficient. Therefore, when an attempt is made to obtain a sintered body in which the width of the gap region is narrowed, there is a problem that electric field concentration is likely to occur in a part of the filled insulating material, which easily causes dielectric breakdown.
【０００８】本発明の目的は、内部電極の先端側に幅の
狭いギャップ領域を高精度に構成し得るだけでなく、内
部電極先端のギャップ領域に臨む端縁の平滑性が高めら
れている積層セラミック電子部品を製造し得る方法を提
供することにある。The object of the present invention is not only to form a narrow gap region on the tip side of the internal electrode with high precision, but also to improve the smoothness of the edge facing the gap region at the tip of the internal electrode. It is to provide a method capable of manufacturing a ceramic electronic component.
【０００９】[0009]
【課題を解決するための手段】本発明の積層セラミック
電子部品の製造方法は、まず、セラミックグリーンシー
ト上に薄膜形成法により金属膜を形成する工程と、前記
金属膜が形成されたセラミックグリーンシートを少なく
とも用いて、セラミックグリーンシートと、前記金属膜
よりなる内部電極とが交互に積層された部分を有し、か
つ前記内部電極が少なくとも一対の対向側面に露出され
た積層体が用意される。この場合、上記薄膜形成法とし
ては、例えば、蒸着、スパッタリングまたはめっきある
いはこれらを組合せたような従来より公知の薄膜形成法
が用いられる。According to the method of manufacturing a laminated ceramic electronic component of the present invention, first, a step of forming a metal film on a ceramic green sheet by a thin film forming method, and a ceramic green sheet having the metal film formed thereon. By using at least the above, there is prepared a laminated body having a portion in which the ceramic green sheets and the internal electrodes made of the metal film are alternately laminated, and the internal electrodes are exposed to at least a pair of opposing side surfaces. In this case, as the thin film forming method, for example, a conventionally known thin film forming method such as vapor deposition, sputtering, plating, or a combination thereof is used.
【００１０】次に、上記積層体の一対の対向側面におい
て、最終的にその対向側面に露出させるべきでない内部
電極について、電気化学的にエッチングして内部電極の
露出されていた部分及びその近傍を溶解除去する。しか
る後、内部電極の溶解除去された部分に絶縁材料を充填
する。そして、積層体の一対の対向側面に、それぞれ、
外部電極を形成する。Next, in the pair of opposed side surfaces of the laminate, the internal electrodes which should not be finally exposed to the opposed side surfaces are electrochemically etched to expose the exposed portions of the internal electrodes and the vicinity thereof. Dissolve and remove. After that, the portion of the internal electrode that has been dissolved and removed is filled with an insulating material. Then, on the pair of opposed side surfaces of the laminated body,
Form external electrodes.
【００１１】なお、積層体の焼結は、上記エッチングの
前であっても、後であってもよい。The laminated body may be sintered before or after the etching.
【００１２】[0012]
【作用】本発明では、内部電極が、薄膜形成法により形
成された金属膜により構成されている。従って、導電ペ
ーストを印刷して内部電極を形成した場合に比べて、電
極材料が緻密かつ正確に付与されるので、電極材料の連
続性が飛躍的に高められる。その結果、電気化学的方法
によりエッチングして空隙を形成した場合、空隙に臨む
内部電極端縁部分の平滑性が高められる。In the present invention, the internal electrodes are made of a metal film formed by the thin film forming method. Therefore, as compared with the case where the internal electrode is formed by printing the conductive paste, the electrode material is applied densely and accurately, so that the continuity of the electrode material is dramatically improved. As a result, when the voids are formed by etching by the electrochemical method, the smoothness of the inner electrode edge portion facing the voids is enhanced.
【００１３】[0013]
【発明の効果】本発明の積層セラミック電子部品の製造
方法では、内部電極が薄膜形成法により形成されている
ので、ギャップ領域に臨む内部電極端縁の平滑性が高め
られる。従って、ギャップ領域の幅を狭めてより小型の
積層セラミック電子部品を得る場合であっても、エッチ
ングにより形成された空隙に充填された絶縁材料の一部
において電界集中が生じ難い。According to the method of manufacturing a monolithic ceramic electronic component of the present invention, since the internal electrodes are formed by the thin film forming method, the smoothness of the edges of the internal electrodes facing the gap region is enhanced. Therefore, even when the width of the gap region is narrowed to obtain a smaller monolithic ceramic electronic component, electric field concentration hardly occurs in a part of the insulating material filled in the void formed by etching.
【００１４】しかも、上記内部電極の形成は、薄膜形成
法で行われるため、導電ペーストをパターニングして印
刷する方法に比べ、セラミックグリーンシートへの内部
電極形成工程並びに内部電極の形成されたセラミックグ
リーンシートの積層に際しての省力化も果たすことがで
きる。Moreover, since the internal electrodes are formed by the thin film forming method, the internal electrode forming step on the ceramic green sheet and the ceramic green on which the internal electrodes are formed are different from the method of patterning and printing the conductive paste. Labor saving in stacking the sheets can also be achieved.
【００１５】さらに、電気化学的な方法により内部電極
の一部をエッチングすることにより空隙を形成すること
により、ギャップ領域の大きさが決定されるので、上記
ギャップ領域の幅を小さくすることが容易であり、かつ
ギャップ領域の幅を高精度にコントロールし得る。Further, since the size of the gap region is determined by forming the void by etching a part of the internal electrode by an electrochemical method, it is easy to reduce the width of the gap region. In addition, the width of the gap region can be controlled with high accuracy.
【００１６】よって、本発明によれば、ギャップ領域の
幅を狭めた場合においても絶縁破壊が生じ難いため、信
頼性に優れ、かつより小型の積層セラミック電子部品を
提供することが可能となる。Therefore, according to the present invention, even when the width of the gap region is narrowed, dielectric breakdown is unlikely to occur, so that it is possible to provide a monolithic ceramic electronic component having excellent reliability and a smaller size.
【００１７】[0017]
【実施例の説明】以下、図面を参照しつつ本発明の非限
定的な実施例を説明することにより、本発明を明らかに
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be clarified by describing non-limiting embodiments of the present invention with reference to the drawings.
【００１８】第１の実施例 Ｐｂ（Ｍｇ1/3 Ｎｂ2/3 ）Ｏ3 を主成分とする材料粉末
を有機バインダーと共に溶媒中に分散し、セラミックス
ラリーを得た。得られたスラリーを用い、１０μｍの均
一な厚みのセラミックグリーンシートを作製した。 First Example A material powder containing Pb (Mg 1/3 Nb 2/3 ) O 3 as a main component was dispersed in a solvent together with an organic binder to obtain a ceramic slurry. Using the obtained slurry, a ceramic green sheet having a uniform thickness of 10 μm was produced.
【００１９】上記セラミックグリーンシートの一方主面
に、銀を主成分とする内部電極を蒸着により形成し、し
かる後、６０ｍｍ×４０ｍｍの大きさに打ち抜いた。上
記のようにして用意され、かつ内部電極が一方主面に形
成された複数枚のセラミックグリーンシートと、さらに
内部電極の形成されていないセラミックグリーンシート
とを積層し、厚み方向に圧着した後、９００℃の温度で
焼成し、焼結体を得た。An internal electrode containing silver as a main component was formed on one main surface of the ceramic green sheet by vapor deposition, and then punched into a size of 60 mm × 40 mm. Prepared as described above, and a plurality of ceramic green sheets having internal electrodes formed on one main surface, and further laminating a ceramic green sheet on which internal electrodes are not formed, after pressure bonding in the thickness direction, It was fired at a temperature of 900 ° C. to obtain a sintered body.
【００２０】得られた焼結体をダイヤモンドカッターに
より厚み方向に切断し、３ｍｍ×３ｍｍの矩形形状の平
面形状を有する焼結体を得た。上記のようにして切断し
て得られた焼結体を図１（ａ）に断面図で示す。焼結体
１では、複数の内部電極２〜７がセラミック層を介して
厚み方向に重なり合うように配置されている。この内部
電極２〜７が、上述したように蒸着法により形成されて
いる。The obtained sintered body was cut in the thickness direction with a diamond cutter to obtain a sintered body having a rectangular planar shape of 3 mm × 3 mm. The sintered body obtained by cutting as described above is shown in a sectional view in FIG. In the sintered body 1, the plurality of internal electrodes 2 to 7 are arranged so as to overlap each other in the thickness direction via the ceramic layers. The internal electrodes 2 to 7 are formed by the vapor deposition method as described above.
【００２１】次に、図１（ｂ）で示すように、焼結体１
の端面１ａを覆うように共通電極８を形成した。次に、
図２に示すように、硝酸銀水溶液９中に上記焼結体１を
浸漬し、同じく硝酸銀水溶液９中に浸漬された銀電極１
０と、上記共通電極８との間に１．０Ｖの電位差を１０
分間与え、図１の焼結体１の側面１ｂ側に露出している
内部電極２〜７のうち、共通電極８に電気的に接続され
ている内部電極２，４，６の側面１ｂに露出している部
分及びその近傍を溶解・除去した。内部電極２，４，６
が部分的に溶解除去された焼結体を図３（ａ）に示す。
図３（ａ）に示されているように、内部電極２，４，６
と側面１ｂとの間に、空隙Ａが形成されている。この空
隙Ａの幅すなわち内部電極２，４，６の先端と側面１ｂ
との間の距離は１５μｍであった。Next, as shown in FIG. 1 (b), a sintered body 1
The common electrode 8 was formed so as to cover the end surface 1a of the. next,
As shown in FIG. 2, the above-mentioned sintered body 1 was dipped in an aqueous solution of silver nitrate 9, and a silver electrode 1 similarly dipped in the aqueous solution of silver nitrate 9.
0 and a potential difference of 1.0 V between the common electrode 8 and
Of the internal electrodes 2 to 7 electrically exposed to the side surface 1b of the sintered body 1 of FIG. 1 and electrically connected to the common electrode 8 and exposed to the side surface 1b of the internal electrodes 2, 4 and 6. The part and its vicinity were dissolved and removed. Internal electrodes 2, 4, 6
FIG. 3 (a) shows a sintered body in which is partially dissolved and removed.
As shown in FIG. 3A, the internal electrodes 2, 4, 6
A space A is formed between the side surface 1b and the side surface 1b. The width of the space A, that is, the tips of the internal electrodes 2, 4, 6 and the side surface 1b.
The distance between and was 15 μm.
【００２２】次に、上記空隙Ａに電気泳動法により絶縁
材料としてＰｂ−Ｓｉ−Ａｌ系ガラス微粉末を充填し、
８５０℃の温度で熱処理し、図３（ｂ）に示す絶縁層１
２，１４，１６を形成した。Next, the void A is filled with Pb-Si-Al-based glass fine powder as an insulating material by electrophoresis,
Heat treatment was performed at a temperature of 850 ° C., and the insulating layer 1 shown in FIG.
2, 14 and 16 were formed.
【００２３】さらに、焼結体１において、図３（ｂ）の
一点鎖線Ｂで示す部分まで該焼結体１を共通電極８が形
成されている側から研磨し、内部電極２〜７を側面１ａ
´に露出させた。この状態を図４に示す。Further, in the sintered body 1, the sintered body 1 is ground from the side where the common electrode 8 is formed up to the portion shown by the one-dot chain line B in FIG. 1a
Exposed to ´. This state is shown in FIG.
【００２４】次に、焼結体１の側面１ｂに、図５に示す
ように共通電極１８を形成し、上記と同様にして、硝酸
銀水溶液中に浸漬し電気化学的にエッチングすることに
より、共通電極１８に電気的に接続されている内部電極
３，５，７の側面１ａ´に露出されている部分及びその
近傍を除去し、空隙Ｃを形成した。Next, a common electrode 18 is formed on the side surface 1b of the sintered body 1 as shown in FIG. 5, and the common electrode 18 is dipped in a silver nitrate aqueous solution and electrochemically etched in the same manner as described above. Portions exposed in the side surface 1a 'of the internal electrodes 3, 5, 7 electrically connected to the electrode 18 and the vicinity thereof were removed to form a void C.
【００２５】さらに、上記空隙Ｃに、空隙Ａに絶縁層を
形成した場合と同様にして、絶縁層１３，１５，１７を
形成した（図６参照）。次に、焼結体１の側面１ａ´上
に共通電極１９を形成し、図７及び図８に示す積層型圧
電アクチュエータ２１を得た。なお、積層型圧電アクチ
ュエータ２１においては、上記共通電極１８，１９が、
それぞれ、外部と電気的に接続される外部電極を構成し
ている。Further, insulating layers 13, 15 and 17 were formed in the void C in the same manner as when the insulating layer was formed in the void A (see FIG. 6). Next, the common electrode 19 was formed on the side surface 1 a ′ of the sintered body 1 to obtain the laminated piezoelectric actuator 21 shown in FIGS. 7 and 8. In the laminated piezoelectric actuator 21, the common electrodes 18 and 19 are
Each constitutes an external electrode electrically connected to the outside.
【００２６】図９及び図１０を参照して、本実施例の製
造方法における内部電極端縁の平滑性と、従来の導電ペ
ーストの印刷により形成された内部電極の場合の端縁の
状態とを説明する。図９（ａ）に平面断面図に示すよう
に、焼結体３１内において、従来法では内部電極３２が
ある高さ位置において全面に形成されていたとしても、
図示のように電極材料の連続性が充分でない。従って、
焼結体３１をエッチングし、図９（ｂ）に示すようにギ
ャップ領域Ｘを形成した場合、内部電極３２の端縁３２
ａが充分な連続性を有しない。With reference to FIGS. 9 and 10, the smoothness of the edges of the internal electrodes in the manufacturing method of this embodiment and the state of the edges in the case of the internal electrodes formed by the conventional printing of a conductive paste will be described. explain. As shown in the plan sectional view of FIG. 9A, even if the internal electrode 32 is formed on the entire surface of the sintered body 31 by the conventional method at a certain height position,
As shown, the continuity of the electrode material is not sufficient. Therefore,
When the sintered body 31 is etched to form the gap region X as shown in FIG. 9B, the edge 32 of the internal electrode 32 is formed.
a does not have sufficient continuity.
【００２７】これに対して、本実施例の製造方法では、
図１０（ａ）に示すように、薄膜形成法により内部電極
４２が焼結体４１のある高さ位置において緻密にかつ正
確に形成されている。従って、上記電気化学的方法によ
りエッチングしてギャップ領域４３を形成した場合、内
部電極４２の端縁４２ａが図示のように充分な平滑性を
有することになる。On the other hand, in the manufacturing method of this embodiment,
As shown in FIG. 10A, the internal electrodes 42 are precisely and accurately formed at a certain height position of the sintered body 41 by the thin film forming method. Therefore, when the gap region 43 is formed by etching by the electrochemical method, the edge 42a of the internal electrode 42 has sufficient smoothness as shown in the figure.
【００２８】上記のように、本実施例の積層圧電アクチ
ュエータ２１の製造方法では、ギャップ領域を構成する
ための空隙Ａ，Ｃが、電気化学的なエッチング方法によ
り形成されているため、幅１５μｍと非常に狭い幅のギ
ャップ領域を高精度に形成することができる。しかも、
内部電極２〜７が蒸着法により形成されており、内部電
極２〜７の上記空隙Ａ，Ｃに臨む先端部分の平滑性が保
たれているため、幅１５μｍのギャップ領域に絶縁層１
２〜１７を形成したとしても、該絶縁層１２〜１７にお
ける電界集中は生じ難い。As described above, in the method of manufacturing the laminated piezoelectric actuator 21 of the present embodiment, since the voids A and C for forming the gap region are formed by the electrochemical etching method, the width is 15 μm. A gap region having a very narrow width can be formed with high precision. Moreover,
Since the internal electrodes 2 to 7 are formed by the vapor deposition method and the smoothness of the tip portions of the internal electrodes 2 to 7 facing the voids A and C is maintained, the insulating layer 1 is formed in the gap region having a width of 15 μm.
Even if 2 to 17 are formed, electric field concentration is unlikely to occur in the insulating layers 12 to 17.
【００２９】第２の実施例 ＢａＴｉＯ3 を主成分とするセラミック粉末を有機バイ
ンダと共に溶媒中に分散し、セラミックスラリーを得
た。得られたスラリーを用い、１０μｍの均一な厚みの
セラミックグリーンシートを作製した。このセラミック
グリーンシートの一方主面に銀からなる内部電極を蒸着
により形成し、６０ｍｍ×４０ｍｍの大きさに打ち抜い
た。 Second Example Ceramic powder containing BaTiO 3 as a main component was dispersed in a solvent together with an organic binder to obtain a ceramic slurry. Using the obtained slurry, a ceramic green sheet having a uniform thickness of 10 μm was produced. An internal electrode made of silver was formed on one main surface of this ceramic green sheet by vapor deposition and punched into a size of 60 mm × 40 mm.
【００３０】上記のように内部電極が一方主面に形成さ
れたセラミックグリーンシート及び内部電極が印刷され
ていないセラミックグリーンシートを複数枚積層し、厚
み方向に圧着して積層体を得、得られた積層体を１３５
０℃の温度で焼成して焼結体を得た。As described above, a plurality of ceramic green sheets having the internal electrodes formed on the one main surface and a plurality of ceramic green sheets having no internal electrodes printed are laminated and pressure-bonded in the thickness direction to obtain a laminate. 135 stacks
Firing was performed at a temperature of 0 ° C. to obtain a sintered body.
【００３１】得られた焼結体を、平面形状が１．０ｍｍ
×１．５ｍｍの矩形形状となるように切断し、焼結体を
得た。上記のようにして得た焼結体を用いたことを除い
ては、以降の工程を第１の実施例と全く同様にして実施
し、最終的に焼結体の対向側面に外部電極がそれぞれ形
成された積層コンデンサを得た。The obtained sintered body has a planar shape of 1.0 mm.
It was cut into a rectangular shape of × 1.5 mm to obtain a sintered body. Except that the sintered body obtained as described above was used, the subsequent steps were carried out in exactly the same manner as in the first example, and finally the external electrodes were respectively formed on the opposite side surfaces of the sintered body. The formed multilayer capacitor was obtained.
【００３２】本実施例の積層コンデンサの製造方法にお
いても、電気化学的なエッチング方法によりギャップ領
域が形成されるため、幅１５μｍと非常に幅の狭いギャ
ップ領域を高精度に形成することが可能とされている。
しかも、内部電極が銀を蒸着することにより形成されて
いるため、内部電極における電極材料の連続性が高めら
れているため、上記電気化学的なエッチングにより除去
された内部電極端縁における平滑性も高められている。
従って、エッチング後に空隙に充填された絶縁材料にお
いて、異常な電界集中が生じ難い。Also in the method of manufacturing the multilayer capacitor of the present embodiment, since the gap region is formed by the electrochemical etching method, it is possible to form the gap region with a very narrow width of 15 μm with high accuracy. Has been done.
In addition, since the internal electrodes are formed by vapor-depositing silver, the continuity of the electrode material in the internal electrodes is enhanced, and the smoothness of the edges of the internal electrodes removed by the electrochemical etching is also improved. Has been elevated.
Therefore, abnormal electric field concentration is unlikely to occur in the insulating material filled in the voids after etching.
【００３３】第１，第２の実施例は、それぞれ、積層型
圧電アクチュエータ及び積層コンデンサの製造に適用し
たものであるが、本発明の積層セラミック電子部品の製
造方法は、その他、積層型コンデンサを含む複合部品や
積層型圧電共振部品等の積層型セラミック電子部品の製
造方法に広く適用することができる。The first and second embodiments are applied to the manufacture of a laminated piezoelectric actuator and a laminated capacitor, respectively. In the method of manufacturing a laminated ceramic electronic component of the present invention, a laminated capacitor is also used. The present invention can be widely applied to a manufacturing method of a multilayer ceramic electronic component such as a composite component including the same and a multilayer piezoelectric resonance component.
【００３４】また、第１，第２の実施例では、複数の内
部電極が焼結体の厚み方向において交互に焼結体の対向
側面に最終的に露出されていたが、本発明の積層型セラ
ミック電子部品の製造方法が適用される積層型セラミッ
ク電子部品としてはこのような構造を有するものに限定
されない。例えば、絶縁耐圧を高めるために、１の内部
電極をセラミック層を介して隔てられた２枚の内部電極
で構成した積層コンデンサのように、複数枚の内部電極
を一組の内部電極群とし、複数組の内部電極群が厚み方
向において交互に一対の対向側面に露出されている積層
型セラミック電子部品の製造方法にも適用し得る。In the first and second embodiments, the plurality of internal electrodes are finally exposed alternately on the opposite side surfaces of the sintered body in the thickness direction of the sintered body. The laminated ceramic electronic component to which the method for manufacturing a ceramic electronic component is applied is not limited to one having such a structure. For example, in order to increase the withstand voltage, one internal electrode is composed of two internal electrodes separated by a ceramic layer, such as a multilayer capacitor, a plurality of internal electrodes is a set of internal electrode group, It can also be applied to a method of manufacturing a multilayer ceramic electronic component in which a plurality of sets of internal electrode groups are alternately exposed in a pair of opposite side surfaces in the thickness direction.
【００３５】さらには、本発明は、焼結前の積層体にお
いても適用できることは言うまでもない。Further, it goes without saying that the present invention can be applied to a laminated body before sintering.
【図１】（ａ）及び（ｂ）は、それぞれ、第１の実施例
で用意される焼結体及び該焼結体の１の側面に共通電極
を形成した状態を示す各断面図。1A and 1B are cross-sectional views showing a sintered body prepared in a first embodiment and a state in which a common electrode is formed on one side surface of the sintered body, respectively.
【図２】前記化学的な方法で内部電極端縁及びその近傍
をエッチングする方法を示す略図的側面図。FIG. 2 is a schematic side view showing a method of etching an edge of an internal electrode and its vicinity by the chemical method.
【図３】（ａ）及び（ｂ）は、第１の実施例において、
エッチングにより空隙が形成された状態及び該空隙に絶
縁材料を充填した状態を示す各断面図。3 (a) and 3 (b) are schematic views of the first embodiment, FIG.
FIG. 6 is a cross-sectional view showing a state in which a void is formed by etching and a state in which the void is filled with an insulating material.
【図４】絶縁層が形成された焼結体の他方端面を研磨す
ることにより他方端面に内部電極が露出された状態を示
す断面図。FIG. 4 is a cross-sectional view showing a state in which internal electrodes are exposed on the other end surface by polishing the other end surface of the sintered body on which the insulating layer is formed.
【図５】他方側面上に電気化学的エッチング方法により
空隙を形成した状態を示す断面図。FIG. 5 is a cross-sectional view showing a state in which a void is formed on the other side surface by an electrochemical etching method.
【図６】図５に示した焼結体において空隙に絶縁材料を
充填した状態を示す断面図。6 is a cross-sectional view showing a state where voids are filled with an insulating material in the sintered body shown in FIG.
【図７】第１の実施例により得られた積層圧電アクチュ
エータを示す断面図。FIG. 7 is a cross-sectional view showing a laminated piezoelectric actuator obtained according to the first embodiment.
【図８】第１の実施例により得られた積層圧電アクチュ
エータの斜視図。FIG. 8 is a perspective view of the laminated piezoelectric actuator obtained according to the first embodiment.
【図９】（ａ）及び（ｂ）は、従来法において形勢され
た内部電極及び該内部電極の一の端縁及びその近傍を電
気化学的エッチングにより溶解除去した状態を示す部分
切欠平面図。9 (a) and 9 (b) are partially cutaway plan views showing a state in which the internal electrode formed by the conventional method and one edge of the internal electrode and its vicinity are dissolved and removed by electrochemical etching.
【図１０】（ａ）及び（ｂ）は、それぞれ、本発明の方
法において形成された内部電極及び該内部電極の一の端
縁及びその近傍を電気化学的方法により溶解除去した状
態を示す各部分切欠平面図。10 (a) and 10 (b) respectively show the internal electrodes formed in the method of the present invention, and one end edge of the internal electrodes and the vicinity thereof are dissolved and removed by an electrochemical method. FIG.
１…焼結体 １ａ，１ｂ…側面 ２〜７…内部電極 １２〜１７…絶縁層 １８，１９…共通電極（外部電極） DESCRIPTION OF SYMBOLS 1 ... Sintered body 1a, 1b ... Side surface 2-7 ... Internal electrode 12-17 ... Insulating layer 18, 19 ... Common electrode (external electrode)
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成５年５月１２日[Submission date] May 12, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００３０[Name of item to be corrected] 0030
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００３０】上記のように内部電極が一方主面に形成さ
れたセラミックグリーンシート及び内部電極が印刷され
ていないセラミックグリーンシートを複数枚積層し、厚
み方向に圧着して積層体を得、得られた積層体を焼成し
て焼結体を得た。[0030] The ceramic green sheet ceramic green sheets and internal electrodes are internal electrodes formed on one main surface as described above is not printed laminating a plurality, to obtain a laminate and pressed in a thickness direction, is obtained Firing the laminated body
To obtain a sintered body .
Claims (2)
法により金属膜を形成する工程と、 前記金属膜が形成されたセラミックグリーンシートを少
なくとも用いて、セラミックグリーンシートと、薄膜形
成法により形成された金属膜よりなる内部電極とが交互
に積層された部分を有し、かつ前記内部電極が少なくと
も一対の対向側面に露出された積層体を用意する工程
と、 前記積層体の一対の対向側面において、最終的にその対
向側面に露出させるべきでない内部電極について電気化
学的にエッチングして内部電極の露出されていた部分及
びその近傍を溶解除去する工程と、 前記内部電極の溶解除去された部分に絶縁材料を充填す
る工程と、 前記積層体の前記一対の対向側面に、それぞれ、外部電
極を形成する工程とを備えることを特徴とする、積層セ
ラミック電子部品の製造方法。1. A step of forming a metal film on a ceramic green sheet by a thin film forming method, a ceramic green sheet using at least the ceramic green sheet having the metal film formed thereon, and a metal formed by the thin film forming method. A step of preparing a laminate having portions in which internal electrodes made of a film are alternately laminated, and the internal electrodes being exposed on at least a pair of opposing side surfaces; A step of electrochemically etching an internal electrode that should not be exposed to the opposite side surface thereof to dissolve and remove the exposed portion of the internal electrode and the vicinity thereof, and an insulating material on the dissolved and removed portion of the internal electrode. And a step of forming external electrodes on the pair of opposed side surfaces of the laminate, respectively. That, the method of production of a multilayer ceramic electronic components.
グまたはめっきのいずれかの方法で行われる、請求項１
に記載の積層セラミック電子部品の製造方法。2. The thin film forming method is performed by any one of vapor deposition, sputtering, and plating.
A method for manufacturing a monolithic ceramic electronic component according to.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6779593A JP3149611B2 (en) | 1993-03-26 | 1993-03-26 | Manufacturing method of multilayer ceramic electronic component |
| DE19944410504 DE4410504B4 (en) | 1993-03-26 | 1994-03-25 | Method for producing a multilayer ceramic electronic component |
| US08/382,136 US5597494A (en) | 1993-03-26 | 1995-02-01 | Method of manufacturing multilayer ceramic electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6779593A JP3149611B2 (en) | 1993-03-26 | 1993-03-26 | Manufacturing method of multilayer ceramic electronic component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06283371A true JPH06283371A (en) | 1994-10-07 |
| JP3149611B2 JP3149611B2 (en) | 2001-03-26 |
Family
ID=13355250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6779593A Expired - Lifetime JP3149611B2 (en) | 1993-03-26 | 1993-03-26 | Manufacturing method of multilayer ceramic electronic component |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3149611B2 (en) |
| DE (1) | DE4410504B4 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015523725A (en) * | 2012-06-12 | 2015-08-13 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | Multilayer device manufacturing method and multilayer device |
| JP2015528199A (en) * | 2012-06-18 | 2015-09-24 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | Electronic device manufacturing method and electronic device |
| JP2015531168A (en) * | 2012-08-09 | 2015-10-29 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | A method for filling at least one cavity of a multilayer device with a filler and a multilayer device. |
| CN109994597A (en) * | 2017-12-29 | 2019-07-09 | 苏州攀特电陶科技股份有限公司 | Multilayer piezoelectric ceramic actuator and preparation method thereof |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19542365A1 (en) * | 1995-11-14 | 1997-05-15 | Philips Patentverwaltung | Process for producing a multilayer ceramic electronic component |
| DE10064606B4 (en) * | 2000-12-22 | 2004-04-01 | Kliem, Herbert, Prof. Dr.-Ing. | Piezoelectric actuator |
| DE10329028A1 (en) * | 2002-07-11 | 2004-01-29 | Ceram Tec Ag Innovative Ceramic Engineering | Preparation of piezoelectric multi layer actuators for e.g. injection valves, provided with heat insulation formed by sintering thick coating mixture of inorganic material and organic binder |
| DE102007004813B4 (en) * | 2007-01-31 | 2016-01-14 | Continental Automotive Gmbh | Method for producing a piezoceramic multilayer actuator |
| DE102007007113A1 (en) | 2007-02-13 | 2008-08-28 | Epcos Ag | Multilayer component |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4453199A (en) * | 1983-06-17 | 1984-06-05 | Avx Corporation | Low cost thin film capacitor |
| DD254269A1 (en) * | 1986-12-04 | 1988-02-17 | Elektronische Bauelemente Veb | METHOD FOR PRODUCING CERAMIC MULTILAYER CAPACITORS |
| JPH02224311A (en) * | 1989-02-27 | 1990-09-06 | Onoda Cement Co Ltd | Manufacture of laminated ceramic electronic part |
| US5179773A (en) * | 1991-08-30 | 1993-01-19 | Bmc Technology Corporation | Process of manufacturing multilayer ceramic capacitors |
-
1993
- 1993-03-26 JP JP6779593A patent/JP3149611B2/en not_active Expired - Lifetime
-
1994
- 1994-03-25 DE DE19944410504 patent/DE4410504B4/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015523725A (en) * | 2012-06-12 | 2015-08-13 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | Multilayer device manufacturing method and multilayer device |
| JP2015528199A (en) * | 2012-06-18 | 2015-09-24 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | Electronic device manufacturing method and electronic device |
| US10164167B2 (en) | 2012-06-18 | 2018-12-25 | Epcos Ag | Method for producing an electric component and electric component |
| JP2015531168A (en) * | 2012-08-09 | 2015-10-29 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | A method for filling at least one cavity of a multilayer device with a filler and a multilayer device. |
| US9595390B2 (en) | 2012-08-09 | 2017-03-14 | Epcos Ag | Method for filling at least one cavity of a multi-layer component with a filling material, and multi-layer component |
| CN109994597A (en) * | 2017-12-29 | 2019-07-09 | 苏州攀特电陶科技股份有限公司 | Multilayer piezoelectric ceramic actuator and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3149611B2 (en) | 2001-03-26 |
| DE4410504B4 (en) | 2005-03-24 |
| DE4410504A1 (en) | 1994-09-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5597494A (en) | Method of manufacturing multilayer ceramic electronic component | |
| JPH06349669A (en) | Manufacture of ceramic capacitor | |
| JP4843948B2 (en) | Multilayer piezoelectric element | |
| CN113140405B (en) | Multilayer ceramic capacitor | |
| JPH06283371A (en) | Manufacture of layered ceramic electronic components | |
| JPH09190946A (en) | Laminated ceramic electronic component | |
| JPH0613259A (en) | Multilayered ceramic capacitor and its manufacture | |
| JPH07122455A (en) | Manufacture of multilayered ceramic electronic component | |
| JPH11340081A (en) | Multilayer ceramic electronic component and its manufacture | |
| JPH11112046A (en) | Piezoelectric actuator and its manufacture | |
| JP2000340448A (en) | Laminated ceramic capacitor | |
| JPH09190947A (en) | Laminated ceramic electronic component | |
| JP5200331B2 (en) | Multilayer piezoelectric element | |
| JP2000277382A (en) | Multi-laminated ceramic capacitor and manufacturing method of the same | |
| JPH06318531A (en) | Multilayered ceramic electronic component | |
| JPH06151999A (en) | Manufacture of laminated piezoelectric/electrostrictive actuator element | |
| JPH10208979A (en) | Laminated electronic component and manufacture thereof | |
| JPH04170016A (en) | Manufacture of laminated ceramic electronic parts | |
| JP4724385B2 (en) | Laminated electronic components and laminated intermediates | |
| US20230320225A1 (en) | Piezoelectric element | |
| JPH0831393B2 (en) | Multilayer ceramic capacitor with fuse | |
| JPH06314630A (en) | Ceramic-lamination electronic component | |
| JP6035773B2 (en) | Multilayer piezoelectric actuator and manufacturing method thereof | |
| JP4373904B2 (en) | Multilayer piezoelectric element | |
| JP2000174581A (en) | Lamination type piezoelectric resonator and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090119 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090119 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100119 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110119 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110119 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120119 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120119 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130119 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130119 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140119 Year of fee payment: 13 |