JPH06282945A - Viterbi decoding device - Google Patents

Abstract

PURPOSE:To suppress the generation rate of errors low without generating a decoding mistake by dividing a transmission signal into plural blocks and performing a likeli-hood comparing discrimination en bloc to every unit of divided blocks. CONSTITUTION:A record read-out controlling means 11 switches the record read-out for the unit of a data block in a recording means 12 and records likelihood discrimination results 50 into the recording means 12 successively and simultaneously outputs likelihood discrimination results 51 stored at every unit of data blocks en bloc in the recording means 12 to a decoding pass deciding means 13. The decoding pass deciding means 13 decides a decoding pass by the likelihood discrimination results 51 and outputs decoded data 48. Thus, the generation rate of errors is suppressed low without generating a decoding mistake even when undecid-able states of the decoding pass are consecutive.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding device,
In particular, the present invention relates to a Viterbi decoding circuit that enables decoding without the limitation on the number of consecutive uncertain states of surviving paths in Viterbi decoding.

[0002]

2. Description of the Related Art Reduction of transmission errors due to the influence of intersymbol interference or the like is a major problem in data transmission systems such as broadcasting, communication and recording media, and Viterbi decoding is considered to be a means for overcoming this problem. ing. As a data transmission system, the data reproduction method applying Viterbi decoding to the data reproduction from the optical disk medium is, for example, "High density recording by Viterbi decoding", Technical Report of the Institute of Television Engineers, Vol.14, No.64,
pp.13-17, Vir'90-63, (Sep.1990) and "Optimization experiment of reproduction equalizer in digital magnetic recording", Technical Report of IEICE, Vol.14, No.47, pp.7 ~ 12, Vir'90-49, (Sep. 1990). In the Viterbi decoding shown in these, signal detection is performed by maximum likelihood decoding in which inter-code interference is inversely used to select the decoding path with the highest likelihood, and when the error rate for S / N uses waveform equalization. Can be smaller.
A specific example of the Viterbi decoding circuit according to the conventional technique is shown in, for example, Japanese Patent Laid-Open No. 4-21973, but here, the Viterbi decoding is performed by regarding the recording / reproducing characteristics of the optical disk as the partial response characteristics of class I (1 + D). The prior art will be described in the case of application.

FIG. 5 is a block diagram of a recording / reproducing system of an optical disc, and shows the position of Viterbi decoding. In FIG. 5, 1 is a precoder, 2 is a characteristic model of an optical disk, 3 is a Viterbi decoder, 4 is recording data input, and 5 is reproduction data output. The optical disc characteristic model 2 is 21 optical discs,
It consists of 6 noise inputs, 22 adders and 23 filters. The recording data input from the recording data input 4 is recorded on the optical disc 21 after the precoder 1 has performed 1 / (1 + D) arithmetic processing. The characteristics of the optical disc can be modeled by a random noise adder 22 having an average value of zero and a filter 23 having a class I (1 + D) partial response characteristic. The reproduced signal from the modeled optical disk is input to the Viterbi decoder 3 and reproduced data 5 is output by the Viterbi algorithm described below.

FIG. 6 shows an example of a reproduced waveform corresponding to an isolated pit in the partial response characteristic of class I (1 + D). The amplitude value is 1.0 at sample points t = 0 and t = 1T, and the other sample points are. It is 0.0. The reproduced signal waveform from the optical disk can be generated by superposing the isolated reproduced waveforms corresponding to the data series.

FIG. 7 shows an example of a Viterbi decoding prediction sample value based on the isolated reproduction waveform of FIG. 6, and three prediction sample values of T0 to T2 are obtained by superimposing the isolated reproduction waveform by a combination of adjacent 2 bits. Set. That is, when T0 is the bit combination "00", T1 is the bit combination "01" or "1".
In the case of 0 ", T2 is the respective prediction sample value in the case of the bit combination" 11 ". E0 to E2 are the values obtained by taking the absolute difference value between the reproduction signal amplitude Yn and these three prediction sample values T0 to T2. The Viterbi decoding handled here performs maximum likelihood decoding of obtaining a data sequence with the highest probability using these values.The details of the Viterbi algorithm are as follows.

Decoding passes "0" and "at some time n"
If the metric corresponding to 1 "is m _n (1), m _n (0)

[0007]

[Formula 1] m _n (1) = min {m _n-1 (1) + E2, m _n-1 (0) + E1} m _n (0) = min {m _n-1 (1) + E1, It is indicated by m _n-1 (0) + E0}. In this equation, min is a function that selects the smaller value, and a smaller metric means a higher likelihood. If these metric differences are Q _n

[0008]

[Number 2] Q _n = m _n (1) becomes _{-m n (0) = min {} Q n-1 + E2, E1} -min {Q n-1 + E1, E0}. Here, if Q _n-1 + E2 ≦ E1 and Q _n-1 + E1 ≦ E0, the decoding pass is “1”.
Can be merged as Qn = E2-E1.

When Q _n-1 + E2> E1 and Q _n-1 + E1 ≦ E0, the decoding paths cannot be merged and Qn = -Q _n-1 .

In the case of Q _n-1 + E2> E1 and Q _n-1 + E1> E0, it can be merged as a decoding path "0" and Qn = E1-E0.

FIG. 8 is a state transition diagram and a trellis diagram for four states (S00 to S11) of a combination of 2 bits of a reproduction signal. The broken line shows the state transition of bit "0", and the solid line shows the state transition of bit "1". For example, if the combination of two bits of the reproduction signal is "00" and the state is S00, the next bit can have the state S00.
It also indicates S01. FIG. 9 is a state transition diagram and a trellis diagram when S00 and S10 and S01 and S11 of the four states (S00 to S11) of FIG. It is determined that the decoding path connects to S0 under the above conditions, it is not determined whether the decoding path connects to S0 or S1 under the conditions, and it is determined that the decoding path connects to S1 under the conditions. To do. Decoded data is obtained by repeatedly performing this likelihood determination to obtain a surviving path.

FIG. 4 is a diagram showing a conventional example of a Viterbi decoding circuit corresponding to the above Viterbi algorithm. In FIG. 4, a block 41 indicated by a broken line is a likelihood determining means, 42 is a decoding path determining means, 43, 44 and 45 are level inputs corresponding to the above-mentioned predicted sample values of T0 to T2, and 46 is a reproduction signal input, 47
Is a clock input, and 48 is a data decoding output. In the likelihood determination means 41, 301 to 303 are absolute difference detection circuits, 304 and 30.
5 is an addition circuit, 306 and 308 are subtraction circuits, 307 is an inversion circuit, 30
9,310 is a comparison circuit, 311 is a 3-input selection circuit, and 312 is a latch circuit. Further, the decoding path determining means 42
Is a 2-input selection circuit, and 315 and 316 are register circuits.

The absolute difference detection circuit 301 of the likelihood discriminating means 41 shown in FIG. 4 obtains the absolute difference between the reproduction signal input 46 and the predicted sample value input 43 corresponding to the combination "11" of two adjacent bits, and the absolute difference value. Outputs E2. Absolute difference detection circuit 302
Takes the absolute difference between the reproduction signal input 46 and the predicted sample value input 44 corresponding to the combination "01" or "10" of two adjacent bits and outputs the absolute difference value E1. Absolute difference detection circuit 303
Takes the absolute difference between the reproduction signal input 46 and the predicted sample value input 45 corresponding to the combination "00" of two adjacent bits and outputs the absolute difference value E0. The adder circuit 304 outputs the absolute difference value E and the output Q _n-1 of the latch circuit 312 which is the metric difference one bit before.
2 is added, and the adder circuit 305 adds the output Q _n-1 of the latch circuit 312, which is the metric difference one bit before, and the absolute difference value E2. The comparator circuits 309 and 310 are the output Q of the adder circuit 304.
_n-1 + E2 and absolute difference value E1 and output of adder circuit 305 Q _n-1 + E1
And the absolute difference value E0 are compared with each other, and the comparison result is input selection circuit 311 and register circuit 31 of decoding path determination means 42.
Output to 5,316. From the comparison result, the above-mentioned likelihood determination condition is obtained. Subtraction circuits 306 and 308 are absolute difference values
The difference E2-E1 between E2 and the absolute difference value E1 and the difference E1-E0 between the absolute difference value E1 and the absolute difference value E0 are output to the 3-input selection circuit 311. The inverting circuit 307 inverts the polarity (positive or negative) of the output Q _n-1 of the latch circuit 312, which is the metric difference of 1 bit before, and the 3-input selection circuit 3
Output to 11. The 3-input selection circuit 311 compares the 3-inputs from the subtraction circuits 306 and 308 and the inverting circuit 307 with the comparison circuits 309 and 310.
According to the comparison result of (1), only one input that is the metric difference after the likelihood determination is selected corresponding to the above-described likelihood determination condition. The latch circuit 312 latches the metric difference selected by the 3-input selection circuit 311, and the output thereof is used for determining the likelihood of the next bit. Register circuit 31 of decoding path determination means 42
5 and 316 record the outputs of the comparator circuits 309 and 310 at the clock cycle of the clock input 37, respectively, and at the same time the outputs of the 2-input selection circuits 313 and 314. Two-input selection circuits 313 and 314 switch respective register outputs of a plurality of bits for switching serial or parallel shift of register circuits 315 and 316 according to outputs of comparison circuits 309 and 310. That is, when the outputs of the comparison circuits 309 and 310 are the above likelihood determination conditions, the two-input selection circuits 313 and 314 both operate so as to switch to the register output from the register circuit 315. Further, under the likelihood determination condition, the 2-input selection circuit 313 operates so as to switch to the register output from the register circuit 316, and the 2-input selection circuit 314 operates so as to switch to the register output from the register circuit 315.
Further, under the likelihood determination condition, both 2-input selection circuits 313 and 314 operate so as to switch to the register output from the register circuit 316. This allows the register circuit 315
The outputs of 316 and 316 coincide with each other when the likelihood determination condition is, and the data decoding before that time is confirmed. Also, when the likelihood determination condition is met, the two do not match and are indeterminate. Since the number of register stages of the normal register circuits 315 and 316 is more than the maximum number of continuous likelihood determination conditions, the decoded output 38 is obtained by delaying the number of register stages from the likelihood determination. The decoded output 48 is output from the register circuit 316 because the register circuits 315 and 316 always have the same output if the likelihood determination condition is merged into either "1" or "0". This is because the decoding output 48 is representative.

[0014]

In the likelihood comparison of the Viterbi decoding according to this conventional technique, if the state of the likelihood determination condition continues and the indeterminate state of the decoding paths continues, the decoding result is also inaccurate until the decoding paths are merged during that time. It will be confirmed. The number of continuous uncertain states of this decoding path depends on the reproduced signal waveform, but it is the maximum number of blocks of data that can be divided. Not only does the number of data register stages become enormous, but the number of switching bits of the switching circuit for switching serial or parallel shift between the two register outputs also increases and the circuit scale increases. Normally, the number of register stages is reduced by limiting the number to a certain number statistically in consideration of the error rate. In this case, however, the number of consecutive undefined states in the decoding path exceeds the number of register stages depending on the reproduced signal waveform. However, in this case, a decoding error occurs, and the reliability of the decoded data from that point is greatly impaired.

An object of the present invention is to solve the above-mentioned problems of the prior art and to cause a decoding error in a Viterbi decoding device even if the indeterminate state of the decoding path continues endlessly from the likelihood comparison result. An object of the present invention is to provide a Viterbi decoding circuit which can suppress the error rate to a small value without any error.

[0016]

In order to achieve the above object, in the present invention, a likelihood comparison determination means for determining a likelihood comparison result by a Viterbi algorithm, and a likelihood determination result by the likelihood comparison determination means are stored as data. Recording means for recording all in block units and recording / reading of the recording means to sequentially record the likelihood determination result in the recording means in data block units and at the same time determine the likelihood from the already recorded recording means. Recording / reading control means for reading out the result in data block units in the reverse order of recording order, and Viterbi decoding path is determined retrospectively for each data block unit in transmission order from the likelihood determination result read by the recording means by the recording / reading control means. A decoding path output means for outputting the decoded data is provided.

[0017]

In the present invention, the likelihood comparison / determination means compares the likelihoods by the Viterbi algorithm, and the decoding paths indicate three states of a state of merging to "0", a state of merging to "1", and a state of not merging. Output the discrimination result. The recording means sequentially records the likelihood determination results in data block units. The recording / reading control means controls recording on the recording means and reading from the recording means, records the likelihood determination result from the likelihood comparison determination means in a data block unit in the transmission order of the reproduction signal, and at the same time reverses the recording order. The likelihood determination result already recorded in is read out in data block units. The decoding path judging means judges the Viterbi decoding path from the read likelihood judgment result by tracing back to the transmission order of the reproduction signal and outputs the decoded data. As a result, even if the number of consecutive non-merged decoding paths is large, the likelihood determination results for all the reproduced signals of the data blocks are recorded, and the Viterbi decoding pass is collectively performed from the recorded likelihood determination results for each data block. Since it is determined retroactively, data can be decoded without causing a decoding error.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a Viterbi decoding apparatus according to the present invention. 2 is a circuit diagram showing details of the Viterbi decoding device shown in FIG. The configuration and operation of the embodiment will be described with reference to these drawings.

In FIG. 1, 41 is a likelihood determining means, 11 is a recording / reading controlling means, 12 is a recording means, and 13 is a decoding path determining means. Also, 46 is a reproduction signal input, 47 is a clock input,
Reference numeral 48 denotes a data decoding output, which is indicated by the same reference numeral as that shown in FIG. Further, 49 is a data load signal, and 50 and 51 are likelihood determination results.

In FIG. 1, the likelihood discriminating means 41 discriminates the likelihood from the relationship between the reproduced signal and the predicted sample value as described in the explanation of the prior art using FIG. The determination result 50 is output. The recording / reading control means 11 switches the recording / reading of the recording means 12 in units of data blocks, and simultaneously records the likelihood determination result 50 sent from the likelihood determination means 41 to the recording means 12 at the same time. The likelihood determination results, which are collectively recorded in the means 12 in data block units, are read out in the reverse order of the recording order, and the likelihood determination results 51 are decoded path determining means.
Output to 13. The decoding path judging means 13 judges the decoding path from the likelihood judgment result 51 and outputs the decoded data 48.

FIG. 2 shows the recording / reading control means 11 shown in FIG.
3 is a circuit diagram showing details of a plurality of series recording means 12 and a decoding path determination means 13. FIG. In FIG. 2, 101 is a switching control circuit, 1
02 and 103 are shift register circuits, 104 is exclusive OR
(EOR) circuit, 105 is a switching circuit, 106 is a latch circuit, and 107 is a logic inverting circuit. Reference numeral 47 is a clock input, 48 is a data decoding output, 49 is a data load signal, and 50 and 51 are likelihood determination results, which are indicated by the same reference numerals as those in FIG.

In FIG. 2, the likelihood determination result 50 is output to the switching control circuit 101 from the likelihood determining means 41 shown in FIG. This likelihood determination result 50 is the comparison circuit 309 and 3 shown in FIG.
2 bits output from 10. The switching control circuit 101 sequentially transfers the 2-bit likelihood determination result 50 to the shift register circuit 102 in the first half of the clock cycle using the clock input 47, and records it in the shift register circuit 103 in the second half of the clock cycle. The 2-bit likelihood determination result 51 is read and output to the decoding path determination means 13. The shift register circuits 102 and 103 record and read the likelihood determination results 50 and 51.
The output of the likelihood determination result 50 is sequentially recorded by shifting in the order of arrival by the clock input 47 until the entire data block is recorded. The shift register circuit 103 transfers and records the likelihood determination result 50 for each block by the data load signal 49 after the likelihood determination result 50 of all the data blocks is recorded in the shift register circuit 102. This data block is a data block for each segment that is divided, for example, like a sample format. The block-likelihood determination result 51 recorded in the shift register circuit 103 is sequentially read by the clock input 47 in the reverse order of the order recorded in the shift register circuit 102. That is, the final likelihood determination result recorded in the shift register circuit 102 is transferred to the shift register circuit 103 in a batch and then read first. The likelihood determination result 51 read from the shift register circuit 103 is sequentially transferred to the decoding path determination means 13.

Exclusive OR in decoding path determination means 13
The (EOR) circuit 104 takes the exclusive OR (EOR) of the 2-bit likelihood determination results 51 transferred from the switching control circuit 101 and outputs it to the switching circuit 105. The switching circuit 105 is the switching control circuit 101.
One bit of the 2-bit likelihood determination result 51 transferred by the above and the output obtained by inverting the output of the latch circuit 106 by the inverting circuit 107 are switched by the output of the exclusive OR (EOR) circuit 104. That is, when the result of the exclusive OR (EOR) is "0", it is switched to one bit of the likelihood determination result 51, and when it is "1", it is switched to the output of the inverting circuit 107. The latch circuit 106 latches the output of the switching circuit 105, and this output becomes the Viterbi decoding output 48.

FIG. 3 is a diagram showing an example of the Viterbi decoding path for the reproduced waveform, the likelihood determination result, and the Viterbi decoding output. As shown in FIG. 9, the Viterbi decoding path is merged with S0 among the possible three-state likelihood determination results (“0
It is determined only when it is merged with S1 (when it is "0") and when it is merged with S1 (when it is "11"). Other than that, it is undetermined. The likelihood determination results are collected in block units in the reverse direction of the reproduction signal transmission order by the operations of the means 12 and the decoding path determination means 13. Therefore, the Viterbi decoding output of the likelihood determination results shown in FIG. If the likelihood determination result is "00" (the output of the EOR circuit 104 is "0"), it is 1 from that point.
The Viterbi decoding result of the reproduced signal before the bit period is "0" and the 2-bit likelihood determination result is "01" (EOR circuit
The output "1" of 104 is the Viterbi decoding result of the reproduced signal one bit cycle before that time, which is the inverted value of the current Viterbi decoding result, and the 2-bit likelihood determination result is "11".
(The output of the EOR circuit 104 is "0"), and the Viterbi decoding result of the reproduction signal one bit period before that time is "1". As a result, the reproduction signal of the block unit can obtain the Viterbi decoding output in the order opposite to the transmission order. The final likelihood determination result of the block is always merged into S0 (in the case of "00") at the end of the reproduction signal divided into blocks, so all Viterbi decoding outputs before that point are fixed. Become. The Viterbi decoding output is delayed by one block from the data block to which the reproduction signal is transferred.

As described above, according to the operation of the embodiment of the present invention, the Viterbi decoding can be collectively performed on a block-by-block basis, and the Viterbi decoding path can be determined in the reverse order of the transmission order of the reproduced signal to perform data decoding. Even if the indeterminate state of the Viterbi decoding path based on the likelihood determination result continues, Viterbi decoding outputs of all data blocks can be obtained and decoding errors can be eliminated. Further, unlike the prior art, a switching circuit for switching serial or parallel loads of shift register outputs of two systems is not required and the circuit configuration can be simplified.

FIG. 10 is another embodiment of the Viterbi decoding circuit shown in FIG. 1, and is a circuit diagram showing the recording / reading control means 11 and the plural series recording means 12 in a detailed configuration different from that of FIG. In FIG. 10, the same parts as those in FIG. 2 are designated by the same reference numerals, and new reference numerals 110 and 111 are switching circuits. Reference numeral 52 is a data block switching signal.

In FIG. 10, the likelihood determination result 50 is output to the switching circuit 110 from the likelihood determining means 41 shown in FIG. The switching circuit 110 switches so as to alternately transfer the likelihood determination result 50 to the shift register circuits 102 and 103 in data block units by the data block switching signal 52. The likelihood determination results recorded in the shift register circuits 102 and 103 are respectively input to the switching circuit 111, and the switching circuit 111 outputs the likelihood determination results to the data block switching signal 52, which is the opposite of the switching operation of the switching circuit 110. The data is alternately switched in block units and output to the decoding path determination means 13. That is, when the switching circuit 110 is switched to transfer the likelihood determination result 50 to the shift register circuit 102, the switching circuit 111 outputs the likelihood determination result from the shift register circuit 103 to the decoding path determination means 13 as 51, and vice versa. When the switching circuit 110 switches so as to transfer the likelihood determination result 50 to the shift register circuit 103, the switching circuit 111 causes the shift register circuit 1 to move.
The likelihood determination result from 02 is 51, and the decoding path determination means 13
Is output to. The configuration and operation of the decoding path determination means 13 have already been described, and will be omitted.

In the embodiment shown in FIG. 10, since two systems of shift register circuits are alternately switched between recording and reading in data block units, parallel data loading between the shift register circuits is not necessary, and the number of wirings is as shown in FIG. It can be reduced as compared with the embodiment.

FIG. 11 shows still another embodiment of the Viterbi decoding circuit shown in FIG. 1, which is a circuit showing the recording / reading control means 11 and the plural series recording means 12 in a detailed configuration different from those of FIGS. 2 and 10. It is a figure. 11, the same parts as those in FIG. 2 or FIG. 10 are indicated by the same reference numerals and are new reference numerals.
120 is an address generating circuit, 121 is an inverting circuit, 122 is an address switching circuit, 123 is a data switching circuit, and 124 is a memory circuit.

In FIG. 11, the likelihood determination result 50 is output to the data switching circuit 123 from the likelihood determining means 41 shown in FIG. The data switching circuit 123 records the likelihood determination result 50 by the clock input 47 in the memory circuit 124 in the first half of the clock, and at the same time, in the latter half of the clock, the likelihood determination result already recorded in the memory circuit 124 one data block before. It is output as the reading 51 to the decoding path determination means 13. The address generation circuit 120 counts the clock input 47 and sequentially generates addresses for recording the likelihood determination result in the memory circuit 124. The inverting circuit 123 inverts this address to sequentially generate the read address in the reverse order of the recording address. The address switching circuit 122 supplies the address generation circuit 120 to the memory circuit 124 in the first half of the clock by the clock input 47.
The read address from the inverting circuit 123 is input to the memory circuit 124 in the latter half of the clock at the same time as inputting the recording address from. The memory circuit 124 alternately records and reads the likelihood determination result by the address input and the data input / output at the clock cycle. The recording / reading area of the memory circuit 124 is switched by the data block switching signal 52 each time data block is transferred.

2 and 10 in the embodiment shown in FIG.
Since a memory is used instead of the two-system shift register circuit shown in FIG. 1, the circuit configuration can be further simplified.

FIG. 12 shows another embodiment of the Viterbi decoding circuit according to the present invention. The recording / reading control circuit shown in FIG.
14 and recording means 15 are added. In this embodiment, the read / write control circuit 11 has the same configuration and operation as the read / write control circuit 11 and the read / write control circuit 11 and the read / write control circuit 11 outputs the decoded data 48 output in the reverse order of the reproduction signal transfer order.
14 and the recording means 15 restore the reproduction signal in the transfer order and output the decoded data 53. As a result, decoded data can be obtained in the order of reproduction signal transfer. The decoded data obtained in this embodiment has a delay of two data blocks from the point of time when the reproduction signal is transferred. Further, in this embodiment, the recording / reading control circuit 14 and the recording means 15 may be integrated with the recording / reading control circuit 11 and the recording means 12, respectively.

[0034]

According to the present invention, even if the uncertain state of the decoding path is continuous according to the likelihood determination result, after the data blocks in which the decoding path is definitely determined are collectively recorded, the recording order is reversed. Since the likelihood determination result is read and the decoding path is determined, the error occurrence can be suppressed to a low level without causing a decoding error, and the circuit configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of a Viterbi decoding circuit according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a Viterbi decoding circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of Viterbi decoding.

FIG. 4 is a block diagram of a Viterbi decoding circuit according to a conventional technique.

FIG. 5 is a recording / reproducing block diagram.

FIG. 6 is a diagram showing an example of a class I partial response isolated reproduction waveform.

FIG. 7 is a diagram illustrating an example of Viterbi decoded prediction sample values.

FIG. 8 is a state transition diagram and a trellis diagram for Viterbi decoding.

FIG. 9 is a state transition diagram and a trellis diagram for Viterbi decoding.

FIG. 10 shows a second Viterbi decoding circuit according to the embodiment of the present invention.
3 is a detailed block diagram of FIG.

FIG. 11 is a third Viterbi decoding circuit according to the embodiment of the present invention.
3 is a detailed block diagram of FIG.

FIG. 12 is a block diagram of a Viterbi decoding circuit according to another embodiment of the present invention.

[Explanation of symbols]

 41 ... Likelihood determination means, 11,14 ... Recording read control means, 12,15 ... Recording means, 42,13 ... Decoding path determination means, 101 ... Switching control circuit, 102, 103 ... Shift register circuit, 104 ... Exclusive OR (EOR) circuit, 105 ... switching circuit, 106 ... latch circuit, 107 ... logic inverting circuit, 110, 111 ... switching circuit, 120 ... address generating circuit, 121 ... address inverting circuit, 122 ... address switching circuit, 123 ... data switching circuit, 124 ... Memory times. ,

Claims (5)

[Claims] 1. A Viterbi decoding device for decoding data by applying a Viterbi algorithm, wherein a transmission signal is divided into a plurality of blocks, and likelihood comparison and determination are performed collectively for each block to be divided. A Viterbi decoding device, wherein the Viterbi decoding path is judged by tracing back the likelihood comparison judgment result in the transmission order. 2. A Viterbi decoding device for applying a Viterbi algorithm to perform data decoding, and a likelihood comparison / determination means for performing a likelihood comparison between a plurality of predicted amplitude values for a transmission signal and outputting a likelihood determination result. Recording means for recording the likelihood determination result from the likelihood comparison / determination means in block units, and recording / reading control means for controlling the recording / reading so that the likelihood determination result of the recording means is read out in the reverse order of the recording order. And a decoding path determination means for determining the Viterbi decoding path in block units in the transmission order from the likelihood determination result read by the recording / reading control means from the recording means. 3. The Viterbi decoding apparatus according to claim 2, wherein recording / reading of the likelihood determination result of the recording means is alternately switched at a transmission clock cycle of a transmission signal. 4. A recording means for recording the likelihood determination result is constituted by a memory having a plurality of blocks of recording areas, and the recording areas of the memory are alternately switched at a transmission block cycle to perform recording and reading. The Viterbi decoding device according to claim 2. 5. A second recording means for recording a plurality of blocks of the decoded data from the decoding path judging means for judging the Viterbi decoding path by tracing the transmission order in block units, and decoding by the second recording means. 3. Viterbi according to claim 2, further comprising a second recording / reading control means for controlling the recording / reading so that the data is read out in the reverse order of the recording order, and for providing the decoded data to be read out in the same order as the transmission order. Decoding device.