JP3238053B2 - Data detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data detection circuit for Viterbi decoding of data recorded on an optical disk or the like, and more particularly to a data detection circuit capable of decoding data at a low data error rate.

[0002]

2. Description of the Related Art Conventionally, as a data detection circuit for a reproduction signal of an optical disk on which high-density recording has been performed, the reproduction signal is represented by PR (1, 1).
1) There is known a data detection circuit that equalizes characteristics and performs maximum likelihood decoding of the equalized reproduced signal by two-state Viterbi decoding (M. Tobita, “Viterbi De”).
protection of Partial Response
se on a Magneto Optical R
recording Channel "; SPIE Vo
l. 1663 Optical Data Storage
ge (1992) p166-p173).

Further, as a circuit for reproducing data recorded at a higher density, a reproduced signal is equalized to PR (1, 2, 1) characteristics, and data is decoded by four-state Viterbi decoding corresponding to the PR characteristics. A known data detection circuit is known (JP-A-6-243598).

FIG. 24 is a block diagram showing a configuration of a conventional data detection circuit. In FIG. 24, data recorded on a recording medium 1 is converted into an electric signal by an optical pickup 2. Then, the clock signal is input to the clock extraction unit 3 to which the PLL circuit is applied, and the channel clock C1 synchronized with the reproduction signal is output. The AD converter 4 quantizes the reproduction signal at the timing of the clock C1. The quantized data sequence is input to the equalizer 6 and equalized to a desired PR characteristic. The output of the equalizer 6 is input to a branch metric calculator 8, and a branch metric is calculated using an expected value corresponding to the PR characteristic. Then, the branch metric is input to the ACS circuit 11, and the surviving path is determined. The ACS circuit 11 outputs information indicating which state transition has occurred in the surviving path, and this output is input to the data decoding unit 12, where the data is decoded.

[0005]

However, in the above-mentioned conventional data detection circuit, when the SN ratio is reduced due to higher-density recording and intersymbol interference occurs, or the SN ratio is increased due to an increase in noise.
When the ratio decreases, there is a problem that the error rate of decoded data deteriorates.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a reproduced signal recorded at a higher density and having a reduced SN ratio due to intersymbol interference and a reproduced signal having a reduced SN ratio due to a lot of noise. To decode data at a good data error rate, and even at the same recording density and SN ratio as before, to decode data at a better error rate than the conventional error rate, and expand the margin. It is an object of the present invention to provide a data detection circuit that performs the following.

[0007]

According to a first aspect of the present invention, there is provided a data detection circuit for decoding a reproduced signal read from a recording medium by Viterbi decoding to detect data. Data stream generating means for quantizing and equalizing the reproduced signal at sampling points having different phases to generate a predetermined number of quantized data strings corresponding to two or more predetermined number of partial response characteristics; Branch data using the expected value corresponding to each partial response characteristic.
While calculating a click, comprising calculating means for calculating a sum of a predetermined number of branch metrics to generate a composite branch metric, based on the composite branch metric, and a data decoding means for Viterbi decoding the data It is characterized by becoming.

The data stream generating means includes a clock generating means for generating a first clock synchronized with the reproduced signal and a second clock having a predetermined number of frequencies of the first clock, And quantizing means for quantizing the data quantized at the timing of the clock, and classifying the data quantized by the quantizing means at a cycle of the first clock to classify the data into a predetermined number of quantized data strings. It is made.

In the data detection circuit having the above-described configuration, the quantized data sequence having a predetermined number of channel clock intervals having different sampling phases is separately equalized to different partial response characteristics. Then, a combined branch metric is calculated by adding a predetermined number of branch metrics corresponding to the different partial response characteristics, and Viterbi decoding of data is performed using the combined branch metric. The difference in certainty between a given branch and a given branch is larger than when used, the probability of selecting the wrong path as the maximum likelihood path is reduced, and the data error rate of the decoding result is reduced. be able to.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the data detection circuit according to the present invention will be described.

Here, in order to specifically explain, an optical disk is assumed as a recording medium, and a channel clock of 2 is used.
A case will be described in which oversampling is performed with a clock having a double frequency to obtain a quantized data sequence at a plurality of channel clock intervals having different sampling phases and Viterbi decoding is performed.

FIG. 2 is a diagram showing a response of a reproduced waveform when a mark of one channel bit (one bit on a recording medium is called one channel bit) is scanned by an optical spot.
Hereinafter, the reproduced waveform of one channel bit is simply referred to as an impulse response, and the impulse response quantized and discretized at a certain timing is referred to as a discretized impulse response.

In a so-called PRML detection method in which maximum likelihood decoding is performed by Viterbi decoding using characteristics of a partial response (hereinafter referred to as PR characteristics), reproduction is performed using a clock having a channel bit interval synchronized with a reproduction waveform (hereinafter referred to as a channel clock). The waveform is sampled and equalized to desired PR characteristics, and Viterbi decoding is performed. Therefore, in the reproduced signal, the value at the sampling point is important,
Values at other timings are meaningless. For example, PR
In the case where Viterbi decoding is performed using the (1, 2, 1) characteristic, as shown in the impulse response of FIG. 2, the reproduced signal is quantum-quantized at the timing indicated by a white arrow A (hereinafter, referred to as a phase x). After performing equalization processing on PR (1, 2, 1) characteristics, Viterbi decoding is performed. When Viterbi decoding is performed using the PR (1, 1) characteristic, the reproduction signal is quantized at the timing indicated by a black arrow B (hereinafter referred to as a phase y) as shown by the impulse response in FIG. After equalizing the PR (1, 1) characteristic, Viterbi decoding is performed.

As described above, the phase of the quantization timing is different depending on the PR characteristic to be used, because the discretized impulse response when quantized at that timing is different for each P.
This is because selecting the sampling phase so as to be closest to the R characteristic reduces the load on the equalization processing and reduces the data error rate.

The present invention takes advantage of the fact that the discretized impulse response changes when the sampling phase is changed. The branch metric is determined for the reproduced waveform in consideration of the discretized impulse responses at a plurality of sampling phases, and Viterbi decoding is performed. This provides a better decoding method than before.

FIG. 1 is a block diagram showing a data detection circuit according to the present invention. In FIG. 1, data recorded on a recording medium 1 is converted into an electric signal by an optical pickup 2. Then, the electric signal is input to a clock extracting unit 3 (clock generating means in the claims) to which a PLL circuit is applied, and a channel clock C1 synchronized with a reproduced signal is output.
(A first clock in the claims) and a clock C2 (a second clock in the claims) having twice the frequency of the channel clock synchronized with the reproduced signal. The AD converter 4 (quantizing means in the claims) uses the clock C
The reproduction signal is quantized at the timing of 2. On the other hand, the data sorter 5 (sorting means in the claims) alternately sorts the quantized data using the timing of the channel clocks C1 and C2 output from the clock extractor 3 and outputs the data as two data strings. The two data strings are input to the equalizer 6 and the equalizer 7, respectively, and are equalized to desired PR characteristics. The outputs of the equalizer 6 and the equalizer 7 are input to a branch metric calculator 8 and a branch metric calculator 9, and a branch metric is calculated using expected values corresponding to the respective PR characteristics. The signal is combined into one branch metric by the combiner 10 and input to the ACS circuit 11 to determine a surviving path. The ACS circuit 11 outputs information indicating which state transition has occurred in the surviving path, and this output is input to the data decoding unit 12, where the data is decoded. Here, the ACS circuit 11 and the data decoding unit 12
It is designed for the property with the largest number of states. The data sequence generating means in the claims is an AD converter 4, a clock extracting unit 3, a data classifier 5, an equalizer 6,
7 and the calculating means is composed of branch metric calculators 8 and 9 and a combiner 10.
The data decoding means includes an ACS circuit 11 and a data decoding unit 12.

Hereinafter, the details of the data detection circuit having the above configuration will be described. First, the principle of decoding of the data detection circuit will be described.

Now, for two quantized data strings whose sampling phases are shifted by 180 degrees, PR (1, 2, 1) and P
Consider a case where two types of PR characteristics of R (1,1) are applied. This is done by quantizing at a sampling timing of twice the frequency of the channel clock, dividing the data into two data strings by alternately allocating the data, and separately dividing the data into a desired PR.
This can be realized by performing equalization processing on characteristics. In FIG.
The data is sampled by the clock C2,
The data is alternately sorted by the equalizer 6 and the equalizer 7
To achieve the desired PR characteristics.

FIG. 3 shows a state transition diagram of the PR (1, 2, 1) characteristic, and FIG. 4 shows a state transition diagram of the PR (1, 1) characteristic. For the state transition diagram of PR (1, 1), FIG.
Draw like (a), but PR for clarity
It is expanded as the number of states of (1, 2, 1) and drawn as shown in FIG. As described above, it is easy to understand that the PR characteristics that are used simultaneously are expanded according to the PR characteristics having the largest number of states. In these state transition diagrams, the notation Sxx represents past record data. For example, S10 indicates that two bits past is "0" and one bit past is "1". Also, A attached to an arrow indicating a state transition
The letters "H" are added to make it easier to understand when describing the state transition.

Here, consider the expected value of the state transition (branch). The expected value is the value of the reproduced signal on the assumption that no noise exists and no equalization error occurs. In this example, PR (1, 2, 2,
1) Five of an expected characteristics (DX ₀ ~DX _4), PR
There are two types of three expected values (DY _{0 to} DY ₂ ) of the (1,1) characteristic, and each time 1-bit data is reproduced, a pair of these two types of expected values exists. These expected values are actually A
Determined by assuming the output of the D converter. For example, if the AD converter 4 has 8 bits, it is determined in the range of 0 to 255.

For these two pairs of expected values, the vertical axis represents the expected value of PR (1,1), and the horizontal axis represents PR (1,2,1).
FIG. 5 shows a two-dimensional plane using the expected value of. In FIG. 5, alphabetic characters in parentheses correspond to the alphabetical characters added to the state transitions in FIGS.

These expected values are more paired than when PR (1, 1) is considered alone (open circles on the vertical axis) and when PR (1, 2, 1) is considered alone (white circles on the horizontal axis). (Black circles) indicates that the distance from any expected value to any expected value is equal or larger. In particular, the expected values of the state transitions A and F, B and E, C and D, B and G, B and H, E and G, and E and H are PR (1,
1) Two PRs, while the same value was used alone
When the characteristics are used in combination, they have different values, and the expected values of the state transitions B and F and C and E are the same in the case of using only PR (1, 2, 1). When they are used together, they have different values, and it can be considered that the distance between the expected values is considerably widened.

Incidentally, the actually obtained quantized data is obtained by superimposing noise on the expected value. Here, assuming that the noise is white Gaussian distribution noise N (0, σ ² ), a probability density that expresses what value the obtained quantized data has with respect to a certain expected value is represented by a probability. The function can be represented by the following equation.

The probability density function using the PR (1, 2, 1) characteristic is

[0025]

(Equation 1)

The probability density function using the PR (1,1) characteristic is:

[0027]

(Equation 2)

In this method, quantized data of two phases is obtained as a pair. The noise superimposed on them is N
Assuming that (0, σ ² ), the probability density function of the pair of quantized data with respect to the expected value pair is expressed by the product of the probability density functions of equations (1) and (2) as shown in the following equation. be able to.

[0029]

(Equation 3)

This probability density function has a standard deviation σ in FIG.
Is represented by a dotted circle with a radius of. Considering a pair of expected values as in the present invention, the distance between each expected value is increased, and the probability density function is two-dimensional, but the standard deviation σ is the same. The difference in likelihood (branch metric) between a branch and an arbitrary branch increases, the probability of selecting the wrong path as the maximum likelihood path becomes smaller than before, and the data error of the decoding result decreases.

Next, a method for obtaining a branch metric of each branch will be described. Since the branch metric represents the relative value of the certainty of each branch, it is obtained by taking the logarithm of the probability density function and transforming it.

First, the branch metric when the PR (1, 2, 1) characteristic is used alone is as follows when the logarithm of the probability density function of the equation (1) is taken and transformed.

[0033]

(Equation 4)

When the PR (1,1) characteristic is used alone, the branch metric is as follows when transformed by taking the logarithm of the probability density function of equation (2).

[0035]

(Equation 5)

On the other hand, the branch metric in the present invention is obtained as follows by taking the logarithm of the probability density function of the equation (3) and transforming it.

[0037]

(Equation 6)

Equation (6) shows the PR (1, 1) characteristic, PR
It is equal to each branch metric in the (1, 2, 1) characteristic, that is, the sum of the expressions (4) and (5). Therefore, assuming that the superimposed noise is white Gaussian distributed noise, in this example, the branch metric of PR (1,1) and the branch metric of PR (1,2,1) are calculated as before, and these are calculated. It can be considered that the sum is simply a combined branch metric (hereinafter referred to as a combined branch metric). This will be described with reference to the block diagram of FIG. 1. The branch metric calculator 8 calculates a PR (1, 2, 1) characteristic branch metric, and the branch metric calculator 9 calculates a PR (1, 1) characteristic branch metric. Is calculated, and the branch metric synthesizer 10 adds each branch metric to calculate a combined branch metric. Of course, instead of calculating the branch metric of each PR characteristic and then adding each, the calculation of one part at a time does not depart from the gist of the present invention.

The details of the block diagram shown in FIG. 1 will be described below.

First, the operation of the clock extracting unit 3 will be described. The clock extracting unit 3 includes the clock C1 and the clock C
2 is generated. FIG. 6 shows the clock C1 and the clock C2.
FIG. 4 is a diagram showing the timing of FIG. As shown in this figure, the clock C2 is set to a frequency twice that of the clock C1. When the clock C2 rises when the clock C1 is at the high level, the data is quantized at the sampling phase x (PR (1, 2, 1) characteristic) in FIG. At the time when the clock C2 rises, the sampling phase y
(PR (1, 1) characteristic) data is quantized.

Next, the operation of the data classifier 5 will be described. FIG. 7 is a diagram showing an example of the configuration of the data sorter 5. Here, the selector 7-1 outputs the value of the input A from the output Y when the input S is at a high level, and outputs the value of the input B when the input S is at a low level. When data quantized by the AD converter 4 is input to the data classifier having this configuration, the data is alternately distributed by the selector 7-1, the inverter 7-2, and the register 7-3, and the data is divided into two.
Generate two data strings. These two data strings are input to the FIFO buffer 7-4, respectively, and are buffered so that the subsequent processing can be performed in the same phase. As described above, the quantized data is divided into data strings at channel clock intervals by the data discriminator 5, so that the processes after the data discriminator 5 are performed on the basis of the clock having the same cycle as the clock C1.

Next, the equalizers 6 and 7 will be described. FIG. 8 is a diagram showing a specific configuration example. The equalizers 6 and 7 convert the quantized data 5 s and 5 s ′ input from the data classifier 5 into a register 8-1 and a multiplier 8-
2. Equalization processing is performed by an FIR filter including an adder 8-3. Of course, the number of taps is not limited to the number shown in the drawing, and the configuration is not limited to the configuration shown in the drawing. The equalizer 6 equalizes the PR (1, 2, 1) characteristic. The equalizer 7 equalizes the PR (1, 1) characteristic, but these equalizers also have a side effect of increasing high-frequency noise and deteriorating the SN ratio. Even if there is a deviation, each multiplier 8-2 is adjusted so that the data error rate is minimized.

The output 6 s of the equalizer 6 is input to the branch metric calculator 8, and the output 7 s of the equalizer 7 is input to the branch metric calculator 9. Then, the output of the branch metric calculator 8 and the output of the branch metric calculator 9 are combined by the branch metric combiner 9. FIG. 9 is a diagram showing a configuration example of this part. In FIG. 9, the branch metric calculator 8 has PR (1, 2, 2,
1) Five arithmetic units 9-1 to 9-1 corresponding to the expected values of the characteristics
According to −5, the following five types of branch metrics are calculated and output (X is an input).

The arithmetic unit _{9-1: 2X · DX 0 -DX 0} 2 arithmetic unit _{9-2: 2X · DX 1 -DX 1} 2 arithmetic unit _{9-3: 2X · DX 2 -DX 2} 2 arithmetic unit 9-4 : 2X · DX ₃ -DX ₃ ² calculator _{9-5: 2X · DX 4 -DX 4} 2 Furthermore, the branch metric calculator 9 in FIG. 9, P
Three types of branch metrics are calculated and output according to the expected value of the R (1,1) characteristic (Y is input).

The calculator _{9-6: 2Y · DY 0 -DY 0} 2 calculator _{9-7: 2Y · DY 1 -DY 1} 2 calculator _{9-8: 2Y · DY 2 -DY 2} 2 These, branch metric computation The outputs of the unit 8 and the branch metric calculator 9 corresponding to the same branch are added by an adder 9-9 to synthesize a branch metric. In FIG. 9, the alphabetical characters assigned to the output branch metrics correspond to the alphabetical characters assigned to indicate the state transitions in the state transition diagrams (FIGS. 3 and 4).

The output of the adder 10 is input to the ACS circuit 11 as a combined branch metric, the path metric is calculated, and the surviving path is selected. The path selection signal output from the ACS circuit 11 is input to the data decoding unit 12, and the data is decoded by the data decoding unit.

Next, the ACS circuit 11 will be described. FIG. 10 is a diagram illustrating a configuration example of the ACS circuit 11. Here, when the input A> the input B, the comparator 10-2 performs “
1 ”is output from the output Y, and“ 0 ”when input A ≦ input B
Is output. The selector 10-3 outputs the value of the input A from the output Y when the input S is "1", and outputs the value of the input B when the input S is "0".

The ACS circuit adds the branch metrics A to H calculated in the previous stage and the path metrics of the past surviving paths held in the register 10-4 to the adder 10-.
1 is added, and the path metric of each branch is calculated. Next, each path metric is compared by the comparator 10-2, and the path metric of the surviving path is selected by the selector 10-3 according to the comparison result, and is stored in the register 10-4. It is used as the path metric of the surviving path in the calculation. The comparator 10-
2 are output as a path selection signal 10a, a path selection signal 10b, a path selection signal 10c, and a path selection signal 10d, respectively, and input to the data decoding unit 12.

Next, the details of the data decoding unit 12 will be described. FIG. 11 is a diagram showing an example of the configuration. Here, the selector 11-1 outputs the value of the input B from the output Y when the input S is "1", and outputs the value of the input B when the input S is "0".

[0050] The data decoding unit includes the path selection signals 10a and 10a.
A selector 11-1 for selecting data by using b, 10c and 10d as inputs and a register 11-2 are constituted by shift registers connected as shown in FIG. This shift register includes path selection signals 10a, 10b, 10
The shift direction is determined by c and 10d. Therefore, the decoding result is selected in the first stage of the shift register depending on the state transition of the surviving path, and the decoding result of the surviving path is copied in the subsequent stages. If the number of stages of the shift register is increased to some extent, the values of the last four registers become the same. That is, going back to the past, the four surviving paths converge to one path. Therefore, the output of any register at the last stage is output as decoded data.

With the above configuration, it is possible to perform the Viterbi decoding by combining the data quantized at different sampling points, which is a feature of the present invention, and to reduce the data error rate in data detection. For this reason, it is possible to reproduce data recorded at a higher density than before. Further, even if the recording density is the same as that of the related art, the error rate of data can be made smaller and the margin can be enlarged.

In the above embodiment, PR (1, 2, 2,
Although the example in which the 1) characteristic and the PR (1, 1) characteristic are used together has been described, the present invention is not limited to these PR characteristics. For example, the PR characteristics when sampling at the phase x can be considered as PR (1,2,1) characteristics, and the PR characteristics when sampling at the phase y can be considered as PR (1,2,2,1) characteristics. . Expected value of the PR (1, 2, 2, 1) characteristic is 7 Tsude (DZ ₀ ~DZ _6), the number of states is eight. Accordingly, the state transition diagram of the PR (1, 2, 2, 1) characteristic is as shown in FIG. FIG. 12 shows a state transition diagram when the state transition diagram of the PR (1, 2, 1, 1) characteristic is extended according to the number of states of the PR (1, 2, 2, 1) characteristic. Although the detailed configuration of the data detection circuit in this case is not shown, the above-mentioned PR (1, 2, 1) characteristic and PR
It can be easily configured based on the same concept as when the (1,1) characteristic is used together.

When recording on a recording medium, the recording data is usually encoded by some recording code and recorded. However, the data of the present invention is considered in consideration of the characteristic of the minimum inversion interval of the code. It is also possible to apply to a detection method. For example, there is a (1,7) RLL code as a recording code having a minimum inversion interval of two channel bits or more. FIG. 14 shows the conversion table. If the recording data is converted in accordance with this conversion table, and further subjected to a so-called NRZI conversion in which the data is inverted by "1" and recorded on the recording medium, the minimum inversion interval becomes 2 channel bits or more. Further, there is a (2, 7) RLL code as a recording code having a minimum inversion interval of 3 channel bits or more. FIG. 15 shows the conversion table. If the recording data is converted in accordance with this conversion table and further subjected to a so-called NRZI conversion in which the data is inverted by "1" and recorded on a recording medium,
The minimum inversion interval is three or more channel bits.

FIGS. 16 to 23 show state transition diagrams of each PR characteristic in consideration of these characteristics. FIG. 16 shows the PR
State transition of the PR (1, 2, 1) characteristic when the (1, 2, 1) characteristic and the PR (1, 1) characteristic are used together and the characteristic of the recording code that the minimum inversion interval is 2 channel bits or more is considered. FIG. 17 shows the PR (1, 2, 1) characteristic and PR (1, 2).
1) When the characteristic is used in combination and the characteristic of the recording code that the minimum inversion interval is 2 channel bits or more is considered, PR (1,
1) It is a state transition diagram of a characteristic.

FIG. 18 shows the PR (1, 2, 1) characteristic and PR.
PR when the (1,1) characteristic is used together and the recording code characteristic that the minimum inversion interval is 3 channel bits or more is considered.
FIG. 19 is a state transition diagram of the (1, 2, 1) characteristic.
FIG. 9 is a state transition diagram of the PR (1,1) characteristic when the (1,2,1) characteristic and the PR (1,1) characteristic are used together and the recording code characteristic that the minimum inversion interval is 3 channel bits or more is considered. is there.

FIG. 20 shows the PR (1, 2, 1) characteristic and PR
FIG. 21 is a state transition diagram of the PR (1, 2, 1) characteristic when the (1, 2, 2, 1) characteristic is used in combination and the recording code characteristic that the minimum inversion interval is 2 channel bits or more is considered. P
The R (1,2,1) characteristic and the PR (1,2,2,1) characteristic are used together, and the PR (1,2,2) characteristic when the recording code characteristic that the minimum inversion interval is equal to or more than two channel bits is considered. , 1)
It is a state transition diagram of a characteristic.

FIG. 22 shows the PR (1, 2, 1) characteristic and PR
FIG. 23 is a state transition diagram of the PR (1, 2, 1) characteristic when the (1, 2, 2, 1) characteristic is used together and the recording code characteristic that the minimum inversion interval is 3 channel bits or more is considered. P
The R (1,2,1) characteristic and the PR (1,2,2,1) characteristic are used together, and the PR (1,2,2) characteristic when the recording code characteristic that the minimum inversion interval is 3 channel bits or more is considered. , 1)
It is a state transition diagram of a characteristic.

Characteristics of these recording codes (FIGS. 16 to 23)
Although a specific configuration of the data detection circuit in the case where the present invention is applied to the present invention by using both the PR characteristics and the PR characteristics is not shown, the configuration can be easily configured from the above description and the state transition diagram. It is needless to say that also in this case, there is an effect of reducing the data error rate in data detection of the reproduction signal.

The minimum inversion interval is exemplified by two channel bits and three channel bits. However, the invention is not limited to this. Of course, the invention can be applied to a recording code having a minimum inversion interval of four or more channel bits. It is possible.

In the above-described embodiment, the case where oversampling is performed with a clock having a frequency twice as high as the channel clock has been described for the sake of specific description.
Even when oversampling is performed with a clock having a frequency n times the channel clock, it is only necessary to expand the channel to n dimensions.

The method for obtaining a quantized data sequence at a plurality of channel clock intervals is not limited to the above-described method of oversampling and distributing data. For example, a plurality of AD converters may be provided to The quantization may be performed at the timing of the shifted channel clock.

[0062]

According to the data detection circuit of the present invention, a plurality of branch metrics are respectively calculated from quantized data at sampling points having different phases, and these are added to generate one combined branch metric. Is used to perform Viterbi decoding, errors in decoded data can be reduced, and data recorded at a higher density than before can be reproduced. Further, even if the recording density is the same as that of the related art, the error rate of data can be made smaller and the margin can be enlarged.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of a data detection circuit of the present invention.

FIG. 2 is a waveform chart for explaining the concept of the present invention.

FIG. 3 is a state transition diagram of PR (1, 2, 1) characteristics.

FIG. 4 is a state transition diagram of a PR (1, 1) characteristic.

FIG. 5 is a diagram for explaining the concept of the present invention.

FIG. 6 is a waveform chart for explaining the operation of the clock extraction unit.

FIG. 7 is a block diagram illustrating a configuration of a data classifier.

FIG. 8 is a block diagram illustrating a configuration of an equalizer.

FIG. 9 is a block diagram showing a configuration of a branch metric calculator and a branch metric synthesizer.

FIG. 10 is a block diagram illustrating a configuration of an ACS circuit.

FIG. 11 is a block diagram illustrating a configuration of a data decoding unit.

FIG. 12 shows PR (1, 2, 1) characteristics and PR (1, 2, 2,
FIG. 9 is a state transition diagram of PR (1, 2, 1) characteristics when the (2, 1) characteristics are used together.

FIG. 13 shows PR (1, 2, 1) characteristics and PR (1, 2, 2).
PR (1,2,2,1) when the characteristics are used together
It is a state transition diagram of a characteristic.

FIG. 14 is a diagram showing a typical conversion table of a (1,7) RLL code.

FIG. 15 is a diagram showing a typical conversion table of (2, 7) RLL code.

FIG. 16 illustrates a PR (1, 2, 1, 1) when the PR (1, 2, 1) characteristic and the PR (1, 1) characteristic are used together and the recording code characteristic that the minimum inversion interval is 2 channel bits or more is considered. )
It is a state transition diagram of a characteristic.

FIG. 17 shows a PR (1, 1) characteristic when the PR (1, 2, 1) characteristic and the PR (1, 1) characteristic are used in combination and the recording code characteristic that the minimum inversion interval is 2 channel bits or more is considered. 3 is a state transition diagram of FIG.

FIG. 18 is a diagram showing a PR (1, 2, 1, 1) when the PR (1, 2, 1) characteristic and the PR (1, 1) characteristic are used together and the recording code characteristic that the minimum inversion interval is 3 channel bits or more is considered. )
It is a state transition diagram of a characteristic.

FIG. 19 shows a PR (1, 1) characteristic when the PR (1, 2, 1) characteristic and the PR (1, 1) characteristic are used in combination and the recording code characteristic that the minimum inversion interval is 3 channel bits or more is considered. 3 is a state transition diagram of FIG.

FIG. 20 shows PR (1, 2, 1) characteristics and PR (1, 2, 2).
2, 1) PR characteristic when the characteristic is used together and the characteristic of the recording code that the minimum inversion interval is 2 channel bits or more is considered.
It is a state transition diagram of a (1, 2, 1) characteristic.

FIG. 21 shows PR (1, 2, 1) characteristics and PR (1, 2, 2).
2, 1) PR characteristic when the characteristic is used together and the characteristic of the recording code that the minimum inversion interval is 2 channel bits or more is considered.
It is a state transition diagram of a (1, 2, 2, 1) characteristic.

FIG. 22 shows PR (1, 2, 1) characteristics and PR (1, 2, 2).
2, 1) PR when the characteristic is used together and the characteristic of the recording code that the minimum inversion interval is 3 channel bits or more is considered.
It is a state transition diagram of a (1, 2, 1) characteristic.

FIG. 23 shows PR (1, 2, 1) characteristics and PR (1, 2, 2).
2, 1) PR when the characteristic is used together and the characteristic of the recording code that the minimum inversion interval is 3 channel bits or more is considered.
It is a state transition diagram of a (1, 2, 2, 1) characteristic.

FIG. 24 is a block diagram showing a configuration of a conventional data detection circuit.

[Explanation of symbols]

 3 Clock Extraction Unit 5 Data Classifier 6,7 Equalizer 8,9 Branch Metric Calculator 10 Combiner C1, C2 Clock

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 13/00 G11B 20/18 534 G11B 20/18 570

Claims (2)

(57) [Claims] 1. A data detection circuit for decoding a reproduced signal read from a recording medium by Viterbi decoding and detecting data, wherein the reproduced signal is quantized and equalized at sampling points having different phases, and two or more are reproduced. Data string generating means for generating the predetermined number of quantized data strings corresponding to a predetermined number of partial response characteristics, and using the predetermined number of quantized data strings using expected values corresponding to the respective partial response characteristics. Branch met
And a calculating means for calculating the sum of the predetermined number of branch metrics to generate a combined branch metric, and a data decoding means for performing Viterbi decoding based on the combined branch metric. A data detection circuit. 2. The data detection circuit according to claim 1, wherein the data string generating unit is configured to output a first data stream synchronized with the reproduction signal.
Clock generating means for generating a second clock having a frequency that is a predetermined multiple of the frequency of the first clock, and a quantizing means for quantizing the reproduced signal at the timing of the second clock; A data detection circuit, comprising: classification means for dividing the data quantized by the quantization means at a cycle of a first clock and classifying the data into the predetermined number of quantized data strings.