JPH0837466A - Viterbi decoding circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation by feeding back a difference from bus metrics of each of survived buses for succeeding arithmetic operation so as to prevent an increase in the arithmetic operation without degrading the accuracy of the arithmetic operation thereby reducing number of stages of arithmetic operation in the feedback loop. CONSTITUTION:Data obtained by quantizing a reproduced signal from an optical disk and equalized by the PR system are applied to a difference branch metric(BM) arithmetic means 1 for each clock, in which the difference from the BMs in all branches is calculated and the result is outputted. A survived bus discrimination means 2 calculates an output of the means 1 and a difference between the BMs between survived buses of one preceding clock of a latch means 5 to discriminate the survived bus. A difference BM arithmetic means 3 uses the difference from the BMs of the survived bus from the means 1, 5 to calculate the BM of the bus transited from each survived bus. An output of the means 3 is selected depending on an output of the means 2 by a difference BM selection means 4. The means 5 latches the output of the means 4 as a difference from the BMs between the survived buses. A data decoding means 6 is used to decode the data by using the output of the means 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding circuit, and more particularly, it performs a maximum likelihood decoding of the signal recorded on an optical disk after the information is equalized by the partial response method.
The present invention relates to improvement of a Viterbi decoding circuit in RML detection.

[0002]

2. Description of the Related Art As a data detection method of a reproduction signal of an optical disc recorded at high density, the reproduction signal is equalized to PR (1,1) characteristics which is a kind of partial response method,
There is one that performs maximum likelihood decoding of this equalized signal using a Viterbi signal (M. Tobita; "Viterbi Detection of Partial Re
sponse on a Magneto Optical Recording Channel "; SPI
E Vol.1663 Optical Data Strage (1992) p166-p173).

Further, as a data detection method for high-density recording, a reproduction signal is equalized to a PR (1,2,1) characteristic which is a kind of partial response method, and the equalized signal is PR ( A maximum likelihood decoding method has been proposed using a 4-state Viterbi signal for 1, 2, 1) characteristics (Fujiwara, Yamaguchi et al .; "PRM in magneto-optical recording / reproducing system".
A Study of L Detection "; Proceedings of the 1993 Spring Conference of the Institute of Electronics, Information and Communication Engineers, C-474, Application No. 5-31699
No., application number Japanese Patent Application No. 5-266762, etc.).

The Viterbi decoding circuit for the PR (1,1) characteristic is described in (MJ Ferguson, "Optimal Reception for Binar
y Partial Response Channels "; The Bell System Techn
The method proposed in ical Journal, Vol.51, No.2, pp493-505, Feb, 1972.) is simple and effective for high speed operation.

[0005] When using this method to the Viterbi decoding circuit for PR (1, 1) characteristics, as follows, contains the difference delta _k with which range the addition result of the input data y _{k + 1} between the survivor path M is the type of combination of surviving paths
The type of edge is discriminated and the difference between the surviving paths is calculated.

When Δ _k + y _{k + 1} >+1; + merge, Δ _{k + 1} = y _{k + 1} −1 −1 ≦ Δ _k + y _{k + 1} ≦ + 1; no merge, Δ _{k + 1} = − When Δ _k −1> Δ _k + y _{k + 1} ; −merge, Δ _{k + 1} = y _{k + 1} +1 where + merge, no merge, −merge
Each e indicates a combination of survivor paths as shown in FIG. In the above arithmetic expression, since 0 of digital data to be recorded is set to −1 and 1 is set to +1, assuming that there is no noise, the input data y _{k + 1} is −.
There are three values of 2, 0, and +2, but this is for simplicity and if y _{k + 1} is the output of the AD converter, it is corrected accordingly.

Therefore, if the above conditions are judged,
Data can be decoded using the determination result.

Although this method is simple in operation and is effective for 2-state Viterbi decoding, for example, a 4-state Viterbi decoding circuit for PR (1,2,1) characteristics cannot use this method. So in this case, GDForney.JR; "The
Viterbi Argorithm ", Proc IEEE, 61, No.3, pp268-278, Ma
rch, 1972 and Trikeps; "Actual error correction technology" pp1
The general method as shown in 59-161 is used.

A Viterbi decoding circuit to which this method is applied, as shown in FIG. 9, is a branch metric calculating means 10 for calculating a branch metric from input data, a branch metric calculated by the branch metric calculating means 10 and a holding means 12. The addition / comparison and selection means 11 for performing addition, comparison, and selection with the path metrics of the past surviving paths held in the table, the holding means 12 for holding the path metrics of the past surviving paths, and the addition / comparison and selection means 11
Data decoding means 6 for decoding the data from the output of. Then, the addition / comparison / selection means 11 adds the branch metric calculated by the branch metric calculation means 10 and the path metric of the past surviving path held in the holding means 12, and the branch metric and holding means. The comparison means 14 for comparing the magnitude of the past surviving path held in 12 with the path metric, and the selection of selecting the more probable path metric as the path metric of the surviving path using the result of the comparing means 14. And means 15.

Next, the operation of this conventional example will be described.

The branch metric calculating means 10 calculates a branch metric from the input data, and the branch metric calculated by the branch metric calculating means 10 and the path metric of the past surviving path held in the holding means 12 are added together by the adding means 13 The branch metric and the path metric of the past surviving path held in the holding means 12 are compared by the comparing means 14 and compared. Using the result of the comparing means 14, the more probable path metric is the selecting means 15.
Selected as the path metric for the surviving path by
It is held by the holding means 12. The output of the comparison means 14 is input to the data decoding means 6 and is output as decoded data.

Next, the above-mentioned conventional Viterbi decoding circuit is
A case of application to a four-state Viterbi decoding circuit for PR (1,2,1) characteristics will be described with reference to FIG. The same components as those in FIG. 9 are designated by the same reference numerals and the description thereof will be omitted.

The addition / comparison / selection means 11 comprises a plurality of adders 1
6, a plurality of comparators 17, and a plurality of selectors 18. The holding means 12 is composed of a plurality of registers 19.

Next, the operation of this conventional example will be described.

The branch metric for each branch is calculated by the branch metric calculating means 1 from the data input every one clock, and the value of the calculated branch metric and the path metric of the surviving path calculated one clock before are added. Is added by the comparator 1
The sizes are compared by 7. According to the result of the comparison means 14, the output of the adder 16 having the larger likelihood is the selector 1
It is selected by 8 and used for the calculation in the next clock. On the other hand, the output of the comparator 17 is input to the data decoding means 6, and the data is decoded using this and output.

However, in the Viterbi decoding circuits shown in FIGS. 9 and 10, the path metrics of the surviving paths are added every time, and therefore the value increases each time data is input. Vessel 17, selector 1
8, the word length of the data handled by the arithmetic unit such as the register 19 is made sufficiently large, or the word length is limited by truncating the lower bits of the path metric of the surviving path at each operation, or as shown in FIG. As shown, processing such as inserting the path metric normalization calculating means 10 for normalizing the path metric of the surviving path into the feedback loop becomes necessary.

[0017]

The method of making the word length sufficiently large is effective when the block unit for decoding is small, but when the decoding unit is several hundred bytes in one sector like an optical disk. Requires a very long word length, and in particular, the time required for the arithmetic operation of the adder 16 and the comparator 17 becomes long. Therefore, in order to perform processing within one clock time, the clock cycle must be lengthened. It cannot be operated at high speed.

Further, in the method of truncating the lower bits of the path metric of the surviving path, the accuracy of the path metric is lost and the performance of the Viterbi decoding circuit deteriorates.

Further, the method of inserting an arithmetic unit for normalizing the path metric in the feedback loop is the most effective, but since the arithmetic processing which must be processed within one clock time increases, the clock cycle is lengthened. It must be operated at a high speed.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to prevent the value used for the calculation from always increasing without lowering the accuracy of the calculation and to reduce the number of calculation stages in the feedback loop. By doing so, it is an object of the present invention to provide a Viterbi decoding circuit that can operate at high speed.

[0021]

According to the present invention, the above object is to provide a difference branch metric calculation means for calculating a difference between branch metrics from input data, and a difference between the calculated branch metrics. Survivor path determination means for determining each survivor path by using the difference in path metric between each survivor path calculated from the input data up to the previous time, and the difference between each calculated branch metric and each survivor. The difference path metric calculating means for calculating the difference between the respective path metrics using the difference in the path metric between the paths, and the difference path metric calculating means based on the result of the surviving path determining means between the respective surviving paths. It is performed by using the difference path metric selection means for selecting the difference of the path metric and the input data up to the previous time. 3. The method further comprising: holding means for feeding back the difference in path metric between the respective surviving paths to the surviving path determining means and the differential path metric calculating means; and data decoding means for decoding data from the output of the surviving path determining means. This is achieved by the Viterbi decoding circuit described in.

The survivor path determination means determines the survivor path by comparing the difference between the output of the differential branch metric calculator means and the path metric between the survivor paths calculated and fed back from the previous input data. You should make a decision.

Further, the differential path metric calculating means adds or subtracts the difference between the output of the differential branch metric calculating means and the path metric between the surviving paths calculated and fed back from the input data up to the previous time. It is preferable to calculate the difference between each path metric.

Further, when the path metric difference between the surviving paths calculated and fed back from the input data up to the previous time from the output of the differential branch metric calculator is subtracted by the path metric calculator,
The differential branch metric calculation means has 1 as the original value.
And outputs the same value as the case of adding, and the difference path metric calculating means inverts the difference in the path metric between the surviving paths calculated and fed back from the input data up to the previous time, and then adds the values. Good.

[0025]

In the Viterbi decoding circuit according to claim 1,
Each survivor path is judged using the difference between each branch metric calculated outside the feedback loop and each survivor path calculated and fed back from the previous input data, and each branch calculated outside the feedback loop The difference between the metrics and the difference between each path metric calculated using the difference between each surviving path calculated and fed back from the previous input data is
It is selected and held according to the determination result of the surviving path.

Since the difference in path metric between these surviving paths does not increase each time data is input, the word length of the held data, that is, the data to be fed back can be suppressed to be short.

Therefore, since it is not necessary to provide an arithmetic unit for normalizing the path metric in the feedback loop, a Viterbi decoding circuit which operates at high speed can be constructed. Further, since the difference between the path metrics is calculated outside the feedback loop, it is possible to use a technique such as pipelining, which does not hinder the speedup.

In the Viterbi decoding circuit according to a second aspect of the present invention, each survivor path is determined by comparing the difference in each branch metric with the difference in path metric between the retained survivor paths. The survivor path can be determined by various calculations, the number of calculation stages in the feedback loop can be reduced, and this is also effective for high-speed operation.

In the Viterbi decoding circuit according to the third aspect of the present invention, the difference between the path metrics is calculated by adding or subtracting the difference between the branch metrics calculated outside the feedback loop, which is a simple calculation. Since the difference between the path metrics can be calculated, the number of calculation stages in the feedback loop can be reduced, which is also effective for high-speed operation.

In the Viterbi decoding circuit according to the fourth aspect, in calculating the difference between the path metrics, the difference in the path metric between the surviving paths fed back from the difference between the branch metrics calculated outside the feedback loop. When subtracting, the difference path metric calculation should subtract after subtracting the complement of "2" to subtract the path metric difference between the surviving paths that were fed back. Since a value equal to the value obtained by adding "1" to is output, the difference path metric calculation can be performed by simply inverting the difference between the surviving paths fed back and then adding the result. This is advantageous for high-speed operation because the number of calculation stages can be reduced.

[0031]

1 is a block diagram showing the arrangement of a Viterbi decoding circuit according to the present invention.
Will be described with reference to.

The Viterbi decoding circuit comprises a differential branch metric calculating means 1 for calculating the difference between the branch metrics from the input data, a difference between the branch metrics calculated by the differential branch metric calculating means 1 and the previous input data. The difference between the survivor path determination means 2 for determining each survivor path using the difference in the survivor paths calculated and fed back from the above, and the difference between each branch metric calculated by the differential branch metric calculator 1 and the previous time. Based on the results of the difference path metric calculation means 3 for calculating the difference between the respective path metrics by using the path metric difference between the respective surviving paths calculated from the input data up to Each output from the output of the differential path metric calculation means 3 Difference path metric selecting means 4 for selecting the difference in path metric between the remaining paths, survivor path determining means 2 for calculating the difference in path metric between the surviving paths calculated using the input data up to the previous time, and difference path metric calculation Holding means 5 for feeding back to the means 3
And a data decoding means 6 for decoding data from the output of the survivor path determination means 2.

Next, the operation of the above Viterbi decoding circuit will be described.

The differential branch metric calculation means 1 includes
For example, a reproduction signal from an optical disc is quantized by an A / D converter, and data equalized by the PR system by the equalization circuit is input as input data every clock.
The difference branch metric calculator 1 calculates the branch metric difference between all the branches from the above input data and outputs it. The survivor path determination unit 2 calculates the difference between the output of the differential branch metric operation unit 1 and the path metric of each survivor path stored in the storage unit 5 up to one clock before and determines the survivor path. The path of the path that transitions from each surviving path by using the difference in the output of the differential branch metric calculating means 1 by the differential path metric calculating means 3 and the path metric between the surviving paths held by the holding means 5 up to one clock before The metric is calculated. The output of the differential path metric calculating means 3 is selected by the differential path metric selecting means 4 corresponding to the output of the surviving path determining means 2. The holding means 5 holds the output of the differential path metric selecting means 4 as the path metric difference between the surviving paths,
This value is fed back and used for the calculation when the next data is input. The data decoding means 6 decodes the data using the output of the surviving path determination means 2.

The survival path determination means 2 determines the survival path by comparing the output of the holding means 5 with the output of the differential branch metric calculation means 1. The calculation of the differential path metric in the differential path metric calculating means 3 is performed by adding or subtracting the output of the differential branch metric calculating means 1 and the output of the holding means 5. These calculation methods will be described in detail later. As described above, the difference in the path metric between the surviving paths is always calculated, and this is fed back to perform the next calculation. Therefore, unlike the conventional example, the value does not accumulate and increase, and the word length is It can be kept small. Since the holding means 5 holds the difference in the path metric of each surviving path, it does not increase each time data is input. Therefore, the word length can be shortened without discarding the lower bits or providing the path metric normalization means, so that the operation can be performed at high speed and the circuit scale can be suppressed.

Further, since the survivor path determining means 2 and the differential path metric calculating means 3 operate in parallel and the path metric normalizing means is not necessary, the critical path in the feedback loop is the survivor path determining means 2 → difference. Since the path metric selecting means 4 → holding means 5 or the differential path metric calculating means 3 → differential path metric selecting means 4 → holding means 5 is used, the length can be shortened and the operation can be performed at high speed.

Since the differential branch metric calculation means 1 is formed outside the feedback loop and is feedforward processing, it can be pipelined and does not become an obstacle to high speed operation.

Next, an embodiment of the first Viterbi decoding circuit of the present invention for equalizing the reproduction signal of the data recorded on the optical disk into the PR (1,2,1) characteristic and performing maximum likelihood decoding This will be described with reference to FIG.

The differential branch metric calculator 1 is composed of a plurality of differential branch metric calculators 101 to 128. The survivor path determination means 2 is composed of a plurality of comparators 201 to 204. The differential path metric calculation means 3 is composed of a plurality of adders 301 to 320. The differential path metric selection means 4 is composed of a plurality of selectors 401 to 407. The holding unit 5 is composed of a plurality of registers 501 to 506.

The trellis diagram when the input data is considered to be equalized to the PR (1,2,1) characteristic is as shown in FIG. In FIG. 3, reference symbols b00 to b33 indicating the state transitions indicate branch metrics that are the likelihoods of the state transitions indicated by the arrows. For example, a path that was in state S00 at a time point k is a state at a time point k + 1. The branch metric when the transition to S01 is considered (hereinafter, described as state transition S00 _k → S01 _{k + 1} ) is described as b01, and the branch metric when state transition S11 _k → S10 _{k + 1} is described as b32. .

Each branch metric is obtained by the following calculation.

B00 = 2 · y _{k + 1} · d ₀ −d ₀ ² b02 = 2 · y _{k + 1} · d ₁ −d ₁ ² b21 = 2 · y _{k + 1} · d ₂ −d ₂ ² b23 = 2 · y _{k + 1} · d ₃ −d ₃ ² b10 = 2 · y _{k + 1} · d ₁ −d ₁ ² b 12 = 2 · y _{k + 1} · d ₂ −d ₂ ² b 31 = 2 · y _{k + 1} · d ₃ −d ₃ ² b 33 = 2 · y _{k + 1} · d ₄ −d ₄ ^{2 The} above y _{k + 1} is the decoding circuit input data at the time point k + 1, and d _{0 to} d ₄ correspond to it. It is the expected value of the input data when a state transition occurs.

The Viterbi decoding circuit shown in FIG. 2 is a decoding circuit for performing maximum likelihood decoding on a code whose state changes along the trellis diagram of FIG.

In the differential branch metric calculation means 1,
The branch metric differences between the two branches are calculated for all the combinations from the input data input every one clock. In the illustrated example, since there are 8 branches, 28 combinations exist, and the branch metric differences for all of them are calculated.

Difference branch metric calculators 101 to 12 which are constituent elements of the difference branch metric calculator 1
The reference numeral 8 is the same as that in FIG. 3, and for example, it is described as “b21−b00” in the differential branch metric calculator 105, but this is the branch metric in the case of the state transition S00 _k → S00 _{k + 1.} b00 and state transition S10 _k → S
This indicates that the difference from the branch metric b21 in the case of 01 _{k + 1} is calculated.

Comparators 201 to 1 of the survivor path judging means 2
204 compares the magnitudes of the two input values and outputs the comparison result. The comparators 201 to 204 have inputs A>
Output 0 outputs 0 when input B and 1 when input A ≦ input B.

The input A and the input B are added by the plurality of adders 301 to 320 of the differential path metric calculation means 3 and output as the output Y. A mark ◯ added to the inputs of the adders 301 to 320 means that all the bits of the corresponding inputs are inverted before the addition.

Selector 4 of the differential path metric selection means 4
Inputs A, B, C, and D are selected from 01 to 407 in correspondence with the inputs S1 and S2 as follows, and output from the output Y. Outputs A when S1 = 0 and S2 = 0 Outputs B when S1 = 0 and S2 = 1 Outputs C when S1 = 1 and S2 = 0 Outputs D when S1 = 1 and S2 = 1 The outputs of the selectors 401 to 407 are path metric differences for all combinations in each surviving path that has transited to each state by the previous data. In this example, the number of states is 4, so there are 4 surviving paths. Exists. Therefore, the path metric difference between surviving paths is 6
2 exist, and they are represented by Δ01, Δ23, Δ0 in FIG.
2, Δ21, Δ13, and Δ03.

These symbols represent the difference in the path metric between the surviving paths transiting to the following states.

Δ01 = Difference between path metric of surviving path transiting to state S01 and path metric of surviving path transiting to state S00 Δ23 = path metric of surviving path transiting to state S11 and state S10 Difference between the path metric of the surviving path transiting to state Δ02 = difference between the path metric of the surviving path transiting to state S10 and the path metric of the surviving path transiting to state S00 Δ21 = transition to state S01 Difference between the path metric of the surviving path that is present and the path metric of the surviving path that is transiting to state S10 Δ13 = The path metric of the surviving path that is transiting to state S11 and the path metric of the surviving path that is transiting to state S01 Difference Δ03 = path met of surviving path transiting to state S11 Between the clock and the path metric of the surviving path transiting to the state S00. The symbols Δ01, Δ23, Δ02, Δ21, Δ13, Δ03 are written inside the plurality of registers 501 to 506 of the holding means 5. , The path metric differences between the surviving paths described above are retained.

Hereinafter, when showing a difference between a branch metric and a path metric at a certain time point, a subscript indicating the time point is added to each symbol. For example, the branch metric b02 at the time point _k is b02 _k , and the path metric difference Δ01 between the surviving paths at the time point k + 1 is Δ.
Write as 01 _{k + 1} .

Below, Δ01, Δ23, Δ02, Δ2
The process of holding 1, Δ13, and Δ03 will be described by taking the process of holding Δ01 _{k + 1} as an example.

The differential branch metric calculator 101 calculates b00 _{k + 1} and b1 from the input data at the time point _{k + 1.}
The difference of 0 _{k + 1} is calculated. The comparator 201 compares the output of the differential branch metric calculator 101 and Δ01 _k held in the register 501 in magnitude. This is the state transition S00 _k → S00 _{k + 1} and the state transition S01 _k → S00.
It is equivalent to comparing which path of _{k + 1} has a larger path metric, that is, more likely.

Since Δ01 _k is the difference in the path metric between the surviving paths transiting to the state S00 and the state S01, the metric of the surviving path transiting to the state S00 is considered as the base point, and b00 _{k + 1} is obtained. Δ01 _k + b10
It is obtained by comparing with _{k + 1} . This is b00 _{k + 1} −b
Comparing 10 _{k + 1} with Δ01 _k . Therefore, the state transition S00 _k → S00 _{k + 1} and the state transition S01 _k → S0 are calculated by comparing the outputs of the differential branch metric calculator 101 and the register 501 by the comparator 201.
It is possible to obtain the determination result of which of 0 _{k + 1} is the surviving path.

The differential branch metric calculator 103 calculates b21 _{k + 1} and b3 from the input data at the time point _{k + 1.}
A difference of 1 _{k + 1} is calculated. The comparator 203 compares the output of the differential branch metric calculator 103 with the Δ23 _k held in the register 502. This is equivalent to comparing which path of the state transition S10 _k → S11 _{k + 1} and the state transition S11 _k → S11 _{k + 1} has a larger path metric, and therefore the output of the comparator 203 is the state transition S
It is the determination result of which of 10 _k → S11 _{k + 1} and state transition S11 _k → S11 _{k + 1} is the surviving path.

Similarly, the output of the comparator 202 is the state transition S
The result of the determination is which _one of 00 _k → S10 _{k + 1} and state transition S01 _k → S10 _{k + 1} is the surviving path, and the output of the comparator 204 is state transition S10 _k → S11 _{k + 1} and state transition S11 _k → This is the determination result as to which of S11 _{k + 1} is the surviving path.

The differential branch metric calculator 105 calculates b21 _{k + 1} and b0 from the input data at the time point _{k + 1.}
The difference of 0 _{k + 1} is calculated. The adder 301 adds the output of the differential branch metric calculator 105 and the output of the register 503. If the surviving path is in state transition S00
Assuming that _k → S00 _{k + 1} and state transition S10 _k → S01 _{k + 1} , if S00 _k is considered as a base point, state transition S0
The path metric of 0 _k → S00 _{k + 1} is b00 _{k + 1} ,
The path metric of the state transition S10 _k → S01 _{k + 1} is Δ02.
_{Since k} + b21 _{k + 1} , Δ01 _k is the difference between the path transiting to S00 _{k + 1} and the path transiting to S01 _{k + 1} , Δ01 _k = (Δ02 _k + b21 _{k + 1} ) −b00 _{k + 1} = Δ02 _k + (b21 _{k + 1} −b00 _{k + 1} ). Therefore, the output of the adder 301 is such that the surviving path has state transition S00 _k → S00 _{k + 1} and state transition S10 _k →
It shows Δ01 _{k + 1} when S01 _{k + 1} . Similarly, the output of the adder 302 is such that the surviving path has state transition S00 _k → S00 _{k + 1} and state transition S11 _k → S0.
Shows a Δ01 k + ₁ when a was 1 k _{+ 1,} the output of the adder 304, the survivor path state transition S01 _k
→ S00 _{k + 1} and shows a Δ01 _{k + 1} when a was in a state transition S11 _k → S01 _{k + 1.} The output of the adder 303 is Δ when the surviving path is the state transition S01 _k → S00 _{k + 1} and the state transition S10 _k → S01 _{k + 1.}
Although 01 _{k + 1} is shown, in this case, Δ01 _{k + 1} = b21 _{k + 1} − (b10 _{k + 1} + Δ21 _k ) = (b21 _{k + 1} −b10 _{k + 1} ) −Δ21 _k . Therefore, it is necessary to subtract Δ21 _k . For that purpose, the two's complement of Δ21 _k may be taken and added.
To do that, invert all bits of Δ21 _k and add 1
Must be added. However, inserting a circuit for adding 1 in the feedback loop causes a decrease in operating speed. Therefore, here, only the process of adding 1 is separated and put out of the feedback loop, and 1 is added by the branch metric calculator 107. This causes the adder 3 in the feedback loop.
Since only the inversion for the subtraction process needs to be performed at the input stage 03, the number of operation stages can be suppressed and the operation can be performed at high speed.

Branch metric calculators 111 and 11
In order to obtain a similar operation, 5 is added to 5 119 123 and 127, and adders 307 and 310 are added.
The inversion processing of the input stages 313, 316, and 319 is similarly performed.

The adder 301, 302, 303, 3 according to the results of the comparator 201 and the comparator 203 by the selector 401.
One of the outputs of 04 is selected and output, and this output is held in the register 501 as Δ01 _{k + 1} . For example, when the output of the comparator 201 is 1 and the output of the comparator 203 is 0, the surviving path has a state transition S01 _k → S.
Since 00 _{k + 1} and the state transition S10 _k → S01 _{k + 1} are shown, the output of the adder 303 is the selector 401.
And is held in the register 501 as Δ01 _{k + 1} . This operation is calculated simultaneously for all combinations of paths that transit from the surviving path, regardless of the value of the judgment result of the surviving path judging means 2, so there is no delay in the operation.

Although the process of calculating and holding Δ01 _{k + 1} has been described above, Δ01 _k , Δ23 _k , Δ02 _k and Δ2
1 _k, Δ13 _k, Δ03 _k and _{b00 k + 1 ~b33 k + 1} Δ01 k + 1 _{using, Δ23 k + 1, Δ02 k} + 1, Δ21 k + 1, Δ1
The process of calculating and holding 3 _{k + 1} and Δ03 _{k + 1} is the same as described above, and a description thereof will be omitted.

As described above, the registers 501 to 506 hold the path metric differences of the surviving paths. In this example, there are four surviving paths, but the path metric difference between these surviving paths is always small at a practical level and does not increase each time data is input, so the word length is It can be short. Therefore, since the arithmetic processing of the adder, the comparator, etc. can be performed in a short time, high speed operation becomes possible.

The determination of the surviving path is obtained by comparing the difference between the branch metrics and the difference between the path metrics between the surviving paths, and the path metric between the surviving paths is obtained by comparing the difference between the branch metrics and the surviving path. Since it can be obtained by adding the path metric difference between the two, the processing can be performed simply and in a short time, and the critical path in the feedback loop can be "comparator → selector → register" or "adder → selector → register". Since the processing time can be suppressed to be shorter than that of the “adder → comparator → selector → path metric normalization circuit → register” of the conventional device, high-speed operation is possible. Further, even when the subtraction processing is necessary in the differential path metric calculation means 3, since 1 is added in advance in the differential branch metric calculation means 1, the subtraction processing can be performed by inverting and adding the inputs. The calculation processing time in the feedback loop can be shortened, and high-speed operation is possible.

The data decoding is performed by the data decoding means 6 using the result of the survivor path determination means 2. As shown in FIG. 4, the data decoding means 6 is composed of a plurality of selectors 7 and a plurality of registers 8, and the selectors 7 and 8 constitute a shift register. The direction to be shifted is determined by the output of the survivor path determining means 2 in FIG. When the input S is 0, the input A is selected by the selector 7, and when the input S is 1, the input B is selected and the output Y is output.
Therefore, at the first stage of the shift register, the decoding result is selected depending on the state transition of the surviving path,
After the next stage, the decoding result of the surviving path is copied.
If the number of stages of this shift register is increased to some extent, the values of the four registers at the final stage will be the same.

In other words, as far back as the past, the four surviving paths are converged into one path. Therefore, in the final stage of the shift register, the decoding result of the surviving path remains as the same value in the four registers. Further, even if one of the final stage registers has a different value from the other registers, the majority value is selected by the majority logic circuit 9. The data decoded by the shift register composed of the selector 7 and the register 8 and the majority logic circuit 9 is selected from the four surviving paths finally left after the final data of the decoding block is input. It is equivalent to the data when the most probable one is selected and decrypted at a practical level.

The second embodiment of the Viterbi decoding circuit of the present invention will be described below. It should be noted that for the optical disc, for example, 1-7 RLL / NRZI code or 2-7 RLL / NRZ
A reproduction signal of data recorded by encoding using a code having a run length limitation such as an I code having a minimum inversion interval of 2 channel bits or more is equalized to a PR (1,2,1) characteristic, and this is maximized. The case of likelihood decoding will be described.

FIG. 5 shows a trellis diagram when the input data is considered to be equalized to the PR (1,2,1) characteristic and the run length limitation that the minimum inversion interval is 2 channel bits or more is taken into consideration. become. In FIG. 5, reference numerals b00 to b33 of arrows indicating state transitions are the same as those in FIG.

The configuration of the Viterbi decoding circuit of this embodiment is shown in FIG.
The same components as those shown in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

In the differential branch metric calculation means 1,
The branch metric differences between the two branches are calculated for all the combinations from the input data input every one clock. In the illustrated example, since there are 6 branches, there are 15 combinations, and the branch metric differences for all of them are calculated.

Inputs A are selected when the input S is 0, input B is selected when the input S is 1, and selected from the output Y by the selectors 407 to 410 which are the components of the differential path metric selection means 4. Is output.

Below, Δ01, Δ23, Δ02, Δ2
The process of holding 1, Δ13, and Δ03 will be described by taking the process of holding Δ01 _{k + 1} as an example.

The differential branch metric calculator 101 calculates b00 _{k + 1} and b1 from the input data at the time point _{k + 1.}
The difference of 0 _{k + 1} is calculated. The comparator 201 compares the output of the differential branch metric calculator 101 and Δ01 _k held in the register 501 in magnitude. This is the state transition S00 _k → S00 _{k + 1} and the state transition S01 _k → S00.
It is equivalent to comparing which path of _{k + 1} has a larger path metric, that is, more likely.

That is, Δ01 _k is the state S00 and the state S0.
Since it is the difference in the path metric between the surviving paths transiting to 1, the metric of the surviving paths transiting to the state S00 is considered as the base point, and b00 _{k + 1} and Δ01 _k +
It is obtained by comparing with b10 _{k + 1} . This is b00
Comparing _{k + 1} −b10 _{k + 1} with Δ01 _k . Therefore, the differential branch metric calculator 101 and the register 5
State transition S00 _k → S00 _{k + 1} and state transition S01 by the operation of comparing the output of 01 with the comparator 201.
The determination result of which of _k → S00 _{k + 1} is the surviving path is obtained. Therefore, the output of the comparator 204 is the state transition S10 _k → S11 _{k + 1} and the state transition S11 _k → S11 _{k + 1.}
Which is the surviving pass.

Further, the state transition S10 _k → S01 _{k + 1} and the state transition S01 _k → S10 _{k + 1} do not exist because there is a run length limitation that the minimum inversion interval is 2 channel bits or more, and the state transition S11 _{k is} always present. → S01 _{k + 1} , state transition S00
_{Since k} → S10 _{k + 1} is the surviving path, there is no need to judge.

The differential branch metric calculator 106 calculates b31 _{k + 1} and b0 from the input data at the time point _{k + 1.}
The difference of 0 _{k + 1} is calculated. The adder 302 adds the output of the differential branch metric calculator 106 and the output of the register 506. If the surviving path is in state transition S00
_{If k} → S00 _{k + 1} , the state transition is always S10 _k → S
Since 11 _{k + 1} is a surviving path, if S00 _k is considered as a base point, the path metric of the state transition S00 _k → S00 _{k + 1} is b00 _{k + 1} , and the path metric of the state transition S10 _k → S11 _{k + 1} . Is Δ03 _k + b31 _{k + 1} and Δ01 _{k + 1}
Is the difference between the path transiting to S00 _{k + 1} and the path transiting to S01 _{k + 1} , so Δ01 _{k + 1} = (Δ03 _k + b31 _{k + 1} ) −b00 _{k + 1} = Δ03 _k + (b31 _{k +1 -b00 k +} 1) Thus, the output of the adder 302, Δ01 _{k + 1} when the survivor path is that a state transition S00 _k → S00 _{k + 1}
Is shown. Similarly, the output of the adder 304 shows Δ01 _{k + 1} when the surviving path is the state transition S01 _k → S00 _{k + 1} .

The selector 407 selects one of the outputs of the adders 302 and 304 according to the result of the comparator 201,
This is output, and this output is set as Δ01 _{k + 1} in the register 501.
Is held. For example, when the output of the comparator 201 is 1, it indicates that the surviving path is the state transition S01 _k → S00 _{k + 1.} Therefore, the output of the adder 304 is selected by the selector 401, and Δ01 It is held in the register 501 as _{k + 1} . This operation is calculated simultaneously for all combinations of paths that transit from the surviving path, regardless of the value of the judgment result of the surviving path judging means 2, so there is no delay in the operation.

Although the process of calculating and holding Δ01 _{k + 1} has been described above, Δ01 _k , Δ23 _k , Δ02 _k and Δ2
1 _k, Δ13 _k, Δ03 _k and _{b00 k + 1 ~b33 k + 1} Δ01 k + 1 _{using, Δ23 k + 1, Δ02 k} + 1, Δ21 k + 1, Δ1
The process of calculating and holding 3 _{k + 1} and Δ03 _{k + 1} is the same as described above, and a description thereof will be omitted. However, for Δ21 _{k + 1} , state transition S00 _k → S10 _{k + 1} and state transition S1
There is no need to select 1 _k → S01 _{k + 1} as the surviving path, and the output of the adder 312 is unconditionally Δ21 _{k + 1.}
Is held in the register 504. As for Δ03 _{k + 1} , one of the adders 317 to 320 is selected and stored in the register 506 as Δ03 _{k + 1} as in the first embodiment.

As described above, the registers 501 to 506 hold the difference between the path metrics of the surviving paths. In this example, there are four surviving paths, but the path metric difference between these surviving paths is always small at a practical level and does not increase each time data is input, so the word length is It can be short. Therefore, since the arithmetic processing of the adder, the comparator, etc. can be performed in a short time, high speed operation becomes possible.

The determination of the surviving path is obtained by comparing the difference between the branch metrics and the difference between the path metrics between the surviving paths, and the path metric between the surviving paths is obtained by comparing the difference between the branch metrics and the surviving path. Since it can be obtained by adding the path metric difference between the two, the processing can be performed simply and in a short time, and the critical path in the feedback loop can be "comparator → selector → register" or "adder → selector → register". Since the processing time can be suppressed to be shorter than that of the “adder → comparator → selector → path metric normalization circuit → register” of the conventional device, high-speed operation is possible. Further, even when the subtraction processing is necessary in the differential path metric calculation means 3, since 1 is added in advance in the differential branch metric calculation means 1, the subtraction processing can be performed by inverting and adding the inputs. The calculation processing time in the feedback loop can be shortened, and high-speed operation is possible.

Data decoding is performed by the data decoding means 6 using the result of the survivor path determination means 2. This data decoding means 6 has a plurality of selectors 7 as shown in FIG.
And a plurality of registers 8 and a selector 7
And the register 8 constitute a shift register, and the shift direction of this shift register is determined by the output of the survivor path determining means 2 of FIG. When the input S is 0, the input A is selected by the selector 7, and when the input S is 1, the input B is selected and the output Y is output. Therefore, the decoding result is selected in the first stage of the shift register depending on the state transition of the surviving path, and the decoding result of the surviving path is copied in the subsequent stages. If the number of stages of this shift register is increased to some extent,
The values of the four registers at the final stage are the same.

In other words, as far back as the past, the four surviving paths are converged into one path. Therefore, in the final stage of the shift register, the decoding result of the surviving path remains as the same value in the four registers. Further, even if one of the final stage registers has a different value from the other registers, the majority value is selected by the majority logic circuit 9. The data decoded by the shift register composed of the selector 7 and the register 8 and the majority logic circuit 9 is selected from the four surviving paths finally left after the final data of the decoding block is input. The data is practically equivalent to the data when the most probable one is selected and decrypted.

A reproduced signal of data encoded and recorded by using a code having a run length limit of which the minimum inversion interval is 2 channel bits or more is equalized to a PR (1,2,1) characteristic and this is subjected to maximum likelihood decoding. In that case, a lower data error rate can be obtained by decoding with the Viterbi decoding circuit shown in FIG. 6 than with the Viterbi decoding circuit shown in FIG.

Although the holding means 5 is arranged immediately after the differential path metric selection means 4 in FIGS. 1, 2 and 6, this holding means may be arranged anywhere in the feedback loop. For example, it may be arranged immediately after the differential path metric calculation means 3. In this case, the output of the survivor path determination means 2 must also be delayed by one clock to match the phase, so that a register is also arranged immediately after the survivor path determination means 2. Further, the configuration of the decoding means 6 is as shown in
The output is not limited to FIG. 7 and any one of the four registers may be output without using the majority logic circuit 9. Also, after the final data of the decoding unit block is input, the one with the highest likelihood is selected from the four surviving paths that finally remained, and the data is decoded according to the transition state of that path. You may.

[0083]

According to the Viterbi decoding circuit of the first aspect, since the difference in the path metric of each surviving path is fed back and used for the next calculation, the value does not increase each time the calculation is performed, and the calculation data The word length of is suppressed to be short, and it is possible to operate at high speed without degrading the performance as in the case where the lower bit of the data to be fed back is truncated. Further, it is possible to operate at a high speed by reducing the number of calculation stages in the feedback loop without requiring a calculation means for normalizing the calculation result.

According to the Viterbi decoding circuit of the second aspect, the determination of each surviving path is made by comparing the difference of each branch metric with the difference of the path metric between each surviving path calculated and fed back from the previous input data. Since it is performed by doing so, it is possible to determine the surviving path by a simple calculation, reduce the number of calculation stages in the feedback loop, and operate at high speed.

According to the Viterbi decoding circuit of the third aspect, the calculation of the difference of each path metric calculates the difference of each branch metric and the path metric between each surviving path calculated and fed back by the input data up to the previous time. Since the difference is added or subtracted, the difference between the path metrics can be calculated by a simple calculation, the number of calculation stages in the feedback loop can be reduced, and the operation can be performed at high speed.

According to the Viterbi decoding circuit of the fourth aspect, when the difference in the path metric between the surviving paths fed back is subtracted from the calculation result of the difference in the branch metric, the difference in the branch metric is calculated. Since the value is the same as the value obtained by adding 1 to the original value, the process of taking the 2's complement in the feedback loop is simplified, and the number of operation stages can be reduced to operate at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a Viterbi decoding circuit of the present invention.

FIG. 2 is a block diagram showing a configuration of a first embodiment of a Viterbi decoding circuit of the present invention.

FIG. 3 is a trellis diagram showing a state transition of a PR (1,2,1) characteristic.

4 is a block diagram showing a configuration of a data decoding means of the Viterbi decoding circuit of FIG.

FIG. 5 is a trellis diagram showing state transitions when a minimum inversion interval is recorded using a code having two or more channel bits and is equalized to a PR (1,2,1) characteristic during reproduction. .

FIG. 6 is a block diagram showing a configuration of a second embodiment of a Viterbi decoding circuit of the present invention.

7 is a block diagram showing a configuration of data decoding means of the Viterbi decoding circuit of FIG.

FIG. 8 is an explanatory diagram of a Viterbi decoding method for PR (1,1) characteristics.

FIG. 9 is a block diagram showing a configuration of a conventional Viterbi decoding circuit.

FIG. 10 shows the Viterbi decoding circuit of FIG.
It is a block diagram which shows the structure at the time of applying to a (1, 2, 1) characteristic.

FIG. 11 is a block diagram showing another configuration of a conventional Viterbi decoding circuit.

[Explanation of symbols]

 1 differential branch metric calculation means 2 survivor path determination means 3 differential path metric calculation means 4 differential path metric selection means 5 holding means 6 data decoding means

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Claims (4)

[Claims] 1. A Viterbi decoding circuit for performing maximum likelihood decoding of data equalized by a partial response method or data coded by a convolutional code, and a differential branch metric for calculating a difference between branch metrics from input data. Computing means, and survivor path determining means for determining each surviving path using the difference between the computed branch metrics and the path metric difference between each surviving path computed and fed back from the input data up to the previous time, A difference path metric calculation means for calculating a difference between the path metrics using the calculated difference between the branch metrics and the path metric difference between the surviving paths, and based on a result of the survivor path determining means From the output of the differential path metric calculation means, the path metric of each surviving path Difference path metric selection means for selecting the difference, holding means for feeding back the difference in path metric between the surviving paths calculated using the input data up to the previous time to the surviving path determination means and the difference path metric calculating means, and the surviving A Viterbi decoding circuit including a data decoding unit that decodes data from the output of the path determination unit. 2. The survivor path determining means compares the output of the differential branch metric calculating means with the path metric between the survivor paths calculated from the input data up to the previous time and fed back to determine the survivor path. The Viterbi decoding circuit according to claim 1, wherein the determination is performed. 3. The differential path metric calculating means adds or subtracts the difference between the output of the differential branch metric calculating means and the path metric between the surviving paths calculated and fed back from the input data up to the previous time. A method for calculating a difference between path metrics.
The Viterbi decoding circuit described in 1. 4. The differential branch metric when the path metric calculation means subtracts the difference in path metric between the surviving paths calculated and fed back from the input data up to the previous time from the output of the differential branch metric calculation means. The calculation means outputs a value equal to the value obtained by adding 1 to the original value, and the difference path metric calculation means calculates the difference in path metric between the surviving paths calculated from the input data up to the previous time and fed back. The Viterbi decoding circuit according to claim 1, wherein the Viterbi decoding circuit performs the inversion and the addition.