JP3258174B2 - Viterbi decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding circuit, and more particularly, to a PIT for equalizing information recorded on an optical disc to a partial response system and then decoding the signal with maximum likelihood.
The present invention relates to an improvement of a Viterbi decoding circuit in RML detection.

[0002]

2. Description of the Related Art As a data detection method for a reproduction signal of an optical disk on which high-density recording has been performed, the reproduction signal is equalized to a PR (1, 1) characteristic which is a kind of a partial response system.
Some of the equalized signals are subjected to maximum likelihood decoding using Viterbi signals (M. Tobita; "ViterbiDetection of Partial Reproduction").
sponse on a Magneto Optical Recording Channel "; SPI
E Vol.1663 Optical Data Storage (1992) p166-p173).

Further, as a data detection method for high-density recording, a reproduced signal is equalized to a PR (1, 2, 1) characteristic which is a kind of a partial response method, and the equalized signal is converted to a PR (1, 2). A scheme of maximum likelihood decoding using four-state Viterbi signals for the (1, 2, 1) characteristic has been proposed (Fujiwara, Yamaguchi et al .; "PRM in magneto-optical recording and reproducing system"
Examination of L Detection "; Proceedings of IEICE Spring Conference 1993, C-474, Application No. 5-31699
No., Japanese Patent Application No. 5-266762, etc.).

A Viterbi decoding circuit for the PR (1,1) characteristic is described in (MJ Ferguson, "Optimal Reception for Binar
y Partial Response Channels "; The Bell System Techn
ical Journal, Vol. 51, No. 2, pp 493-505, Feb, 1972) is simple and effective even in the case of high-speed operation.

[0005] When using this method to the Viterbi decoding circuit for PR (1, 1) characteristics, as follows, contains the difference delta _k with which range the addition result of the input data y _{k + 1} between the survivor path M that is the type of combination of surviving paths
The type of erg is determined, and the difference between surviving paths is calculated.

When Δ _k + y _{k + 1} >+1; + merge, Δ _{k + 1} = y _{k + 1} −1 −1 ≦ Δ _k + y _{k + 1} ≦ + 1; no merge, Δ _{k + 1} = − When Δ _k −1> Δ _k + y _{k + 1} ; −merge, Δ _{k + 1} = y _{k + 1} +1 where, + merge, no merge, −merg
e indicates a combination of surviving paths as shown in FIG. In the above equation, the digital data to be recorded is set to −1 for 0 and 1 for +1. Therefore, assuming that there is no noise, the input data y _{k + 1} becomes −
There are three values of 2, 0 and +2, but this is for the sake of simplicity, and if y _{k +1} is the output of the AD converter, it is modified accordingly.

Accordingly, if the above conditions are determined,
The data can be decoded using the determination result.

This method has a simple operation and is effective for two-state Viterbi decoding. However, for example, a four-state Viterbi decoding circuit for PR (1, 2, 1, 1) characteristics cannot use this method. Therefore, in this case, GDForney.JR; "The
Viterbi Argorithm ", Proc IEEE, 61, No.3, pp268-278, Ma
rch, 1972 and Trikeps; "Combat error correction technology" pp1
The general method as shown in 59-161 is used.

As shown in FIG. 9, a Viterbi decoding circuit to which this method is applied includes a branch metric calculating means 10 for calculating a branch metric from input data, a branch metric calculated by the branch metric calculating means 10 and a holding means 12. Addition, comparison and selection means 11 for adding, comparing, and selecting the path metrics of the past surviving paths, storage means 12, for holding the path metrics of the past surviving paths, and addition and comparison means 11
And a data decoding means 6 for decoding data from the output of. The addition / comparison / selection unit 11 includes an addition unit 13 for adding the branch metric calculated by the branch metric calculation unit 10 and the path metric of the past surviving path held in the holding unit 12, a branch metric and a holding unit Comparing means 14 for comparing the magnitude of the past surviving path with the path metric stored in the past 12; and selecting the more probable path metric as the path metric of the surviving path using the result of the comparing means 14. And means 15.

Next, the operation of the conventional example will be described.

A branch metric is calculated from the input data by the branch metric calculation means, and the branch metric calculated by the branch metric calculation means is added to the path metric of the past surviving path held in the holding means. The magnitude of the branch metric is compared with the path metric of the past surviving path held in the holding unit 12 by the comparing unit 14. Using the result of the comparing means 14, a path metric which is more likely to be obtained is selected by the selecting means 15.
Is selected as the path metric of the surviving path by
It is held by the holding means 12. The output of the comparison means 14 is input to the data decoding means 6 and output as decoded data.

Next, the conventional Viterbi decoding circuit described above is
A case where the present invention is applied to a 4-state Viterbi decoding circuit for PR (1, 2, 1) characteristics will be described with reference to FIG. Note that the same components as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.

The addition / comparison / selection means 11 includes a plurality of adders 1
6, a plurality of comparators 17, and a plurality of selectors 18. The holding unit 12 includes a plurality of registers 19.

Next, the operation of the conventional example will be described.

The branch metric calculation means 1 calculates the branch metric for each branch from the data input every clock, and calculates the value of the calculated branch metric and the path metric of the surviving path calculated one clock before the adder 16. Is added by the comparator 1
7, the sizes are compared. According to the result of the comparison means 14, the output of the adder 16 having the larger likelihood is selected by the selector 1
8 and used for the operation at the next clock. On the other hand, the output of the comparator 17 is input to the data decoding means 6, and the data is decoded using the data and output.

However, in the above-described Viterbi decoding circuit shown in FIGS. 9 and 10, the path metric of the surviving path is added each time, and the value increases each time data is input. Unit 17, selector 1
8, the word length of the data handled by the arithmetic unit such as the register 19 is made sufficiently large, or the word length is limited by truncating the lower-order bit of the path metric of the surviving path at each operation. As shown, it is necessary to insert a path metric normalization calculating means 10 for normalizing the path metric of the surviving path into a feedback loop.

[0017]

The above-mentioned method of making the word length sufficiently large is effective when the decoding block unit is small, but when the decoding unit is several hundred bytes in one sector like an optical disk. Requires a very long word length, and in particular, the time required for the operations of the adder 16 and the comparator 17 becomes long. Therefore, in order to process within one clock time, the clock cycle must be lengthened. Cannot operate at high speed.

In the method of truncating the lower bits of the path metric of the surviving path, the precision of the path metric is lost, and the performance of the Viterbi decoding circuit is reduced.

Further, the most effective method is to insert an arithmetic unit for normalizing the path metric in the feedback loop. However, since the number of arithmetic processes that must be processed within one clock time increases, the clock cycle is increased. And cannot operate at high speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to suppress a constantly increasing value used in an operation without reducing the accuracy of the operation and to reduce the number of operation stages in a feedback loop. Accordingly, an object of the present invention is to provide a Viterbi decoding circuit capable of high-speed operation.

[0021]

According to the present invention, the above-mentioned object is to provide a differential branch metric calculating means for calculating a difference between each branch metric from input data; Surviving path determining means for determining each surviving path by using a path metric difference between surviving paths calculated and fed back from input data up to the previous time; a difference between the calculated branch metrics and the surviving paths A difference path metric calculation means for calculating a difference between each path metric using a path metric difference between paths; and a difference path metric calculation means based on a result of the surviving path determination means. A differential path metric selection means for selecting a path metric difference and an operation using input data up to the previous 2. The storage device according to claim 1, further comprising: a holding unit that feeds back the difference of the path metric between the surviving paths to the surviving path determining unit and the differential path metric calculating unit; and a data decoding unit that decodes data from an output of the surviving path determining unit. Is achieved by the Viterbi decoding circuit described in (1).

The surviving path determining means compares the difference between the output of the differential branch metric calculating means and the path metric between the surviving paths calculated from the input data up to the previous time and fed back to determine the surviving path. It is good to make a judgment.

Further, the difference path metric calculation means adds or subtracts a difference between an output of the difference branch metric calculation means and a path metric between surviving paths calculated and fed back from input data up to the previous time. It is preferable to calculate the difference between each path metric.

When the path metric calculation means subtracts the path metric difference between the surviving paths calculated from the output of the differential branch metric calculation means from the input data up to the previous time and fed back from the output of the difference branch metric calculation means,
The difference branch metric calculation means calculates the original value as 1
Is output, and the difference path metric calculation means calculates and feedbacks the path metric difference between the surviving paths calculated from the input data up to the previous time and adds the inverted values. Is also good.

[0025]

In the Viterbi decoding circuit according to the first aspect,
Each surviving path is determined using the difference between each branch metric calculated outside the feedback loop and the difference between each surviving path calculated based on the previous input data and fed back, and each branch calculated outside the feedback loop. The difference between the metrics and the difference between each path metric calculated using the difference between each surviving path calculated and fed back from the previous input data,
It is selected and held according to the surviving path determination result.

Since the path metric difference between the surviving paths does not increase each time data is input, the word length of the held data, that is, the data to be fed back can be reduced.

Therefore, there is no need to provide an arithmetic unit for normalizing the path metric in the feedback loop, and a high-speed Viterbi decoding circuit can be constructed. Further, since the difference between each path metric is calculated outside the feedback loop, a technique such as pipelining can be used, which does not hinder speeding up.

In the Viterbi decoding circuit according to the second aspect, each surviving path is determined by comparing the difference between each branch metric and the stored path metric difference between each surviving path. The surviving path can be determined by simple calculation, the number of calculation stages in the feedback loop can be reduced, and this is also effective for high-speed operation.

In the Viterbi decoding circuit according to the third aspect, the calculation of the difference between each path metric is performed by adding or subtracting the difference between each branch metric calculated outside the feedback loop. Since the difference between each path metric can be calculated, the number of calculation stages in the feedback loop can be reduced, which is effective for high-speed operation.

In the Viterbi decoding circuit according to the fourth aspect, in calculating the difference between the path metrics, the difference between the path metrics between the surviving paths fed back from the difference between the branch metrics calculated outside the feedback loop. Is subtracted, the difference path metric operation should normally be added after taking the complement of "2" in order to subtract the path metric difference between the surviving paths fed back, but the original value in the branch metric operation In the differential path metric calculation, it is sufficient to simply invert the difference between the surviving paths that have been fed back, and then add the result. Can be reduced in the number of operation stages, which is advantageous for high-speed operation.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a Viterbi decoding circuit according to the present invention is shown in FIG.
This will be described with reference to FIG.

The Viterbi decoding circuit calculates difference branch metric calculation means 1 for calculating a difference between each branch metric from input data, and calculates a difference between each branch metric calculated by the difference branch metric calculation means 1 and the previous input data. Surviving path determining means 2 for judging each surviving path using the difference in path metric between surviving paths calculated and fed back, and the difference between each branch metric calculated by differential branch metric calculating means 1 and the Based on the result of the surviving path determining means 2 and the difference path metric calculating means 3 for calculating the difference between the path metrics using the path metric difference between the surviving paths calculated and fed back from the input data up to Each output from the output of the differential path metric calculation means 3 Difference path metric selection means 4 for selecting a path metric difference between the remaining paths; surviving path determination means 2 for calculating a path metric difference between each surviving path calculated using input data up to the previous time; Holding means 5 for feeding back to means 3
And data decoding means 6 for decoding data from the output of the surviving path determination means 2.

Next, the operation of the above-mentioned Viterbi decoding circuit will be described.

The difference branch metric calculation means 1 includes:
For example, a reproduction signal from an optical disk is quantized by an A / D converter, and data equalized in a PR system by an equalization circuit is input as input data every clock.
The difference branch metric calculation means 1 calculates the branch metric difference between all the branches from the input data and outputs the result. The surviving path judgment means 2 calculates the difference between the output of the differential branch metric calculation means 1 and the path metric between the surviving paths held by the holding means 5 up to one clock before and determines the surviving path. The path of the path transiting from each surviving path using the output of the differential branch metric calculating means 1 by the differential path metric calculating means 3 and the path metric difference between each surviving path up to one clock before held in the holding means 5 A metric is calculated. The output of the difference path metric calculation means 3 is selected by the difference path metric selection means 4 in accordance with the output of the surviving path determination means 2. The holding unit 5 holds the output of the difference path metric selection unit 4 as the difference of the path metric between each surviving path,
This value is fed back and used for calculation when the next data is input. Data decoding is performed by the data decoding unit 6 using the output of the surviving path determination unit 2.

The surviving path judgment by the surviving path judging means 2 is performed by comparing the output of the holding means 5 with the output of the differential branch metric calculating means 1. The calculation of the difference path metric in the difference path metric calculation means 3 is performed by adding or subtracting the output of the difference branch metric calculation means 1 and the output of the holding means 5. These calculation methods will be described later in detail. As described above, the path metric difference between the surviving paths is always calculated, and this is fed back to perform the next calculation. Therefore, unlike the conventional example, the values do not accumulate and increase, and the word length is reduced. It can be kept small. Since the difference of the path metric of each surviving path is held by the holding unit 5, it does not increase each time data is input. Therefore, the word length can be kept short without truncating lower bits or providing a path metric normalizing means, so that high-speed operation can be achieved and the circuit scale can be reduced.

Since the surviving path determining means 2 and the differential path metric calculating means 3 operate in parallel, and no path metric normalizing means is required, the critical path in the feedback loop is determined by the surviving path determining means 2 → difference. Since path metric selecting means 4 → holding means 5 or differential path metric calculating means 3 → differential path metric selecting means 4 → holding means 5, the length can be shortened and the operation can be performed at high speed.

The difference branch metric calculation means 1 is formed outside the feedback loop and is feed-forward processing, so that it can be pipelined and does not hinder high-speed operation.

Next, an embodiment of the first Viterbi decoding circuit of the present invention for equalizing a reproduced signal of data recorded on an optical disk to PR (1, 2, 1) characteristics and decoding the equalized signal with maximum likelihood. This will be described with reference to FIG.

The difference branch metric calculation means 1 comprises a plurality of difference branch metric calculation units 101 to 128. The surviving path determination unit 2 includes a plurality of comparators 201 to 204. The difference path metric calculation means 3 is composed of a plurality of adders 301 to 320. The difference path metric selection means 4 is composed of a plurality of selectors 401 to 407. The holding unit 5 includes a plurality of registers 501 to 506.

FIG. 3 shows a trellis diagram when it is considered that the input data is equalized to the PR (1, 2, 1) characteristic. In FIG. 3, symbols b00 to b33 of arrows indicating state transitions indicate branch metrics which are certainty of the state transitions indicated by arrows. For example, at the time point k, the path that was in the state S00 changes to the state at the time point k + 1. When it is considered that the state transition has been made to S01 (hereinafter, described as state transition S00 _k → S01 _{k + 1} ), the branch metric is b01, and when the state transition is S11 _k → S10 _{k + 1} , the branch metric is described as b32. .

Each branch metric is obtained by the following operation.

[0042] _{b00 = 2 · y k + 1} · d 0 -d 0 2 b02 = 2 · y k + 1 · d 1 -d 1 2 b21 = 2 · y k + 1 · d 2 -d 2 2 b23 = _{2 · y k + 1 · d} 3 -d 3 2 b10 = 2 · y k + 1 · d 1 -d 1 2 b12 = 2 · y k + 1 · d 2 -d 2 2 b31 = 2 · y k + ₁ · d ₃ −d ₃ ² b33 = 2 · y _{k + 1} · d ₄ −d ₄ ^{2 The} above y _{k + 1} is the decoding circuit input data at the time of k + 1, and d _{0 to} d ₄ are the corresponding data. This is the expected value of the input data when a state transition occurs.

The Viterbi decoding circuit shown in FIG. 2 is a decoding circuit for maximum likelihood decoding of a code whose state changes along the trellis diagram of FIG.

In the difference branch metric calculation means 1,
The branch metric differences between the two branches are calculated for all the combinations from the input data input every clock. In the illustrated example, since there are eight branches, there are 28 combinations, and the difference between the branch metrics for all of them is calculated.

Difference branch metric calculators 101 to 12 which are components of difference branch metric calculator 1
The reference numeral 8 is the same as that in FIG. 3. For example, “b21−b00” is written in the difference branch metric calculator 105, but this is the branch metric for the state transition S00 _k → S00 _{k + 1.} b00 and state transition S10 _k → S
This means that the difference from the branch metric b21 in the case of 01 _{k + 1} is calculated.

The comparators 201 to 201 of the surviving path determination means 2
Reference numeral 204 compares the magnitudes of the two input values and outputs the result of the comparison. The comparators 201 to 204 receive the input A>
Output 0 is output from input Y when input B, and 1 when input A ≦ input B.

The inputs A and B are added by a plurality of adders 301 to 320 of the difference path metric calculation means 3 and output as an output Y. The addition of a circle to the inputs of the adders 301 to 320 means that all the bits of the corresponding inputs are inverted and then added.

Selector 4 of differential path metric selection means 4
Inputs A, B, C, and D are selected and output from the output Y in accordance with 01 to 407 corresponding to the inputs S1 and S2 as follows. When S1 = 0, S2 = 0, output A. When S1 = 0, S2 = 1, output B. When S1 = 1, S2 = 0, output C. When S1 = 1, S2 = 1, output D. The outputs of the selectors 401 to 407 are the path metric differences for all the combinations in each surviving path that has transited to each state according to the previous data. In this example, the number of states is four, so there are four surviving paths. Exists. Accordingly, the path metric difference between surviving paths is 6
In FIG. 2, Δ01, Δ23, Δ0
2, Δ21, Δ13, and Δ03.

These symbols represent the difference in the path metric between the surviving paths that have transitioned to the following states.

Δ01 = the difference between the path metric of the surviving path that has transitioned to state S01 and the path metric of the surviving path that has transitioned to state S00 Δ23 = the path metric of the surviving path that has transitioned to state S11 and state S10 Δ02 = the difference between the path metric of the surviving path that has transitioned to state S10 and the path metric of the surviving path that has transitioned to state S00 Δ21 = transition to state S01 Difference between the path metric of the surviving path that is in progress and the path metric of the surviving path that is transitioning to state S10 Δ13 = the path metric of the surviving path that is transitioning to state S11 and the path metric of the surviving path that is transitioning to state S01 Δ03 = Pathmethod of surviving path transiting to state S11 Difference between the path metric and the path metric of the surviving path that has transitioned to the state S00. The symbols Δ01, Δ23, Δ02, Δ21, Δ13, and Δ03 are written inside the plurality of registers 501 to 506 of the holding unit 5. , The path metric difference between the surviving paths described above is maintained.

Hereinafter, when a difference between a branch metric and a path metric at a certain time is indicated, a suffix indicating the time is added to each symbol. For example, the branch metric b02 at time _k is b02 _k , and the path metric difference Δ01 between surviving paths at time k + 1 is Δ01
Described as 01 _{k + 1} .

Hereinafter, Δ01, Δ23, Δ02, Δ2
The process in which 1, Δ13, and Δ03 are held will be described using the process in which Δ01 _{k + 1} is held as an example.

The difference branch metric calculator 101 calculates b00 _{k + 1} and b1 from the input data at the time _{k + 1.}
A difference of 0 _{k + 1} is calculated. The comparator 201 compares the output of the difference branch metric calculator 101 with Δ01 _k held in the register 501 in magnitude. This corresponds to state transition S00 _k → S00 _{k + 1} and state transition S01 _k → S00
_This is equivalent to comparing which of the _{k + 1} paths has a larger path metric, that is, is more likely.

Since Δ01 _k is the difference of the path metric between the surviving path transitioning to the state S00 and the state S01, the metric of the surviving path transitioning to the state S00 is considered as a base point, and b00 _{k + 1} and Δ01 _k + b10
It is obtained by comparing with _{k + 1} . This is b00 _{k + 1} -b
10 _{k + 1} is compared with Δ01 _k . Accordingly, the state transition S00 _k → S00 _{k + 1} and the state transition S01 _k → S0 are performed by the operation of comparing the output of the difference branch metric calculator 101 and the output of the register 501 by the comparator 201.
A determination result is obtained as to which of 0 _{k + 1} is the surviving path.

The difference branch metric calculator 103 calculates b21 _{k + 1} and b3 from the input data at the time _{k + 1.}
A difference of 1 _{k + 1} is calculated. The comparator 203 compares the output of the difference branch metric calculator 103 with Δ23 _k held in the register 502. This is equivalent to comparing which of the state transitions S10 _k → S11 _{k + 1} and the state transition S11 _k → S11 _{k + 1} has a larger path metric, and the output of the comparator 203 is the state transition S
The determination result is which of 10 _k → S11 _{k + 1} and state transition S11 _k → S11 _{k + 1} is the surviving path.

Similarly, the output of the comparator 202 is the state transition S
It is a determination result as to which of 00 _k → S10 _{k + 1} and state transition S01 _k → S10 _{k + 1} is the surviving path, and the output of the comparator 204 is state transition S10 _k → S11 _{k + 1} and state transition S11 _k → This is the result of determining which of S11 _{k + 1} is the surviving path.

The difference branch metric calculator 105 calculates b21 _{k + 1} and b0 from the input data at the time _{k + 1.}
A difference of 0 _{k + 1} is calculated. The output of the difference branch metric calculator 105 and the output of the register 503 are added by the adder 301. The surviving path temporarily changes state S00.
_k → S00 _{k + 1} and when to have been state transition S10 _k → S01 _{k + 1,} considering that starting from the S00 _k, the state transition S0
The path metric of 0 _k → S00 _{k + 1} is b00 _{k + 1} ,
The path metric of the state transition S10 _k → S01 _{k + 1} is Δ02
_k + b21 _{k + 1} , and Δ01 _k is the difference between the path transitioning to S00 _{k + 1} and the path transitioning to S01 _{k + 1.} Therefore, Δ01 _k = (Δ02 _k + b21 _{k + 1} ) −b00 _{k + 1} = Δ02 _k + (b21 _{k + 1} −b00 _{k + 1} ). Therefore, the output of the adder 301 indicates that the surviving path has the state transition S00 _k → S00 _{k + 1} and the state transition S10 _k →
It shows Δ01 _{k + 1} assuming that it was S01 _{k + 1} . Similarly, the output of the adder 302 indicates that the surviving path has the state transition S00 _k → S00 _{k + 1} and the state transition S11 _k → S0
Shows a Δ01 k + ₁ when a was 1 k _{+ 1,} the output of the adder 304, the survivor path state transition S01 _k
Δ01 _{k + 1} when → S00 _{k + 1} and state transition S11 _k → S01 _{k + 1} . The output of the adder 303 is Δ の when the surviving path is state transition S01 _k → S00 _{k + 1} and state transition S10 _k → S01 _{k + 1.}
01 _{k + 1} but is of the show, in this _{case, Δ01 k + 1 = b21 k} + 1 - (b10 k + 1 + Δ21 k) = (b21 k + 1 -b10 k + 1) is -Deruta21 _k Therefore, it is necessary to subtract Δ21 _k . To do so, it is sufficient to take the two's complement of Δ21 _k and add it.
In this process, all bits of Δ21 _k are inverted, and 1
Must be added. However, inserting a circuit for adding 1 into the feedback loop causes a reduction in operation speed. Therefore, here, only the process of adding 1 is separated out of the feedback loop, and 1 is added by the branch metric calculator 107. Thereby, the adder 3 is provided in the feedback loop.
Since only the inversion for the subtraction process needs to be performed in the input stage 03, the number of operation stages can be reduced, and the operation can be performed at high speed.

Branch metric calculators 111 and 11
For 5, 119, 123, and 127, 1 is added to obtain the same operation, and adders 307 and 310,
The inversion processing of the input stages 313, 316, and 319 is performed in the same manner.

The adders 301, 302, 303, and 3 are selected by the selector 401 in accordance with the results of the comparators 201 and 203.
One of the outputs 04 is selected and output, and this output is held in the register 501 as Δ01 _{k + 1} . For example, when the output of the comparator 201 is 1 and the output of the comparator 203 is 0, the surviving path is a state transition S01 _k → S
00 _{k + 1} and the state transition S10 _k → S01 _{k + 1} , the output of the adder 303 is
And held in the register 501 as Δ01 _{k + 1} . This operation is performed simultaneously for all combinations of paths transiting from the surviving path regardless of the value of the judgment result of the surviving path judging means 2, so that there is no delay in the operation.

The process of calculating and holding Δ01 _{k + 1} has been described above. However, Δ01 _k , Δ23 _k , Δ02 _k , Δ2 _k
1 _k, Δ13 _k, Δ03 _k and _{b00 k + 1 ~b33 k + 1} Δ01 k + 1 _{using, Δ23 k + 1, Δ02 k} + 1, Δ21 k + 1, Δ1
The process of calculating and holding 3 _{k + 1} and Δ03 _{k + 1} is the same as described above, and a description thereof will be omitted.

As described above, the registers 501 to 506 hold the difference between the path metrics of the surviving paths. In this example, there are four surviving paths, but the path metric difference between these surviving paths is always small at a practical level and does not increase each time data is input. It may be short. Therefore, the arithmetic processing of the adder, the comparator, and the like can be performed in a short time, so that high-speed operation can be performed.

The surviving path is determined by comparing the difference between each branch metric and the path metric between each surviving path. The path metric between the surviving paths is determined by the difference between the branch metric and the surviving path. The process can be performed simply and in a short time because the difference is obtained by adding the path metric difference between the two. The critical path in the feedback loop is either “comparator → selector → register” or “adder → selector → register”. And the processing time can be reduced as compared with the conventional apparatus "adder → comparator → selector → path metric normalization circuit → register", so that high-speed operation is possible. Further, even when the subtraction processing is necessary in the difference path metric calculation means 3, since the difference branch metric calculation means 1 adds 1 in advance, the subtraction processing can be performed if the input is inverted and added. In addition, the arithmetic processing time in the feedback loop can be reduced, and high-speed operation can be performed.

The data decoding is performed by the data decoding means 6 using the result of the surviving path judgment means 2. As shown in FIG. 4, the data decoding means 6 comprises a plurality of selectors 7 and a plurality of registers 8, and the selector 7 and the registers 8 constitute a shift register. The shift direction is determined by the output of the survivor path determination means 2 in FIG. When the input S is 0, the input A is selected by the selector 7, and when the input S is 1, the input B is selected and output from the output Y.
Therefore, in the first stage of the shift register, the decoding result is selected according to the state transition of the surviving path,
From the next stage, the decoding result of the surviving path is copied.
If the number of stages of the shift register is increased to some extent, the values of the last four registers become the same.

That is, going back to the past, the four surviving paths are converged into one path. Therefore, the decoding result of the surviving path remains as the same value in the four registers at the last stage of the shift register. Even if one of the last registers has a different value from the other registers, the majority logic circuit 9 selects the larger value. The data decoded by the shift register constituted by the selector 7 and the register 8 and the majority logic circuit 9 is selected from the four surviving paths finally left after the input of the final data of the decoded block. This is equivalent to data obtained when the most probable data is selected and decoded at a practical level.

Hereinafter, a second embodiment of the Viterbi decoding circuit according to the present invention will be described. In addition, for example, 1-7 RLL / NRZI code or 2-7 RLL / NRZ
A reproduced signal of data encoded and recorded by using a code having a run length limitation of a minimum inversion interval of two channel bits or more, such as an I code, is equalized to PR (1, 2, 1) characteristics, and this is re-equalized. The case of likelihood decoding will be described.

FIG. 5 shows a trellis diagram when the input data is considered to be equalized to the PR (1,2,1) characteristic and the run length limitation that the minimum inversion interval is equal to or more than two channel bits is considered. become. In FIG. 5, reference numerals b00 to b33 of arrows indicating state transitions are the same as those in FIG.

The configuration of the Viterbi decoding circuit of this embodiment is shown in FIG.
The same components as those in FIG. 2 are denoted by the same reference numerals and description thereof is omitted.

In the difference branch metric calculation means 1,
The branch metric differences between the two branches are calculated for all the combinations from the input data input every clock. In the illustrated example, since there are six branches, there are 15 combinations, and the difference between the branch metrics for all of them is calculated.

When the input S is 0, the input A is selected, when the input S is 1, the input B is selected, and the output Y is selected by the selectors 407 to 410 which are components of the differential path metric selection means 4. Is output.

Hereinafter, Δ01, Δ23, Δ02, Δ2
The process in which 1, Δ13, and Δ03 are held will be described using the process in which Δ01 _{k + 1} is held as an example.

The difference branch metric calculator 101 calculates b00 _{k + 1} and b1 from the input data at the time _{k + 1.}
A difference of 0 _{k + 1} is calculated. The comparator 201 compares the output of the difference branch metric calculator 101 with Δ01 _k held in the register 501 in magnitude. This corresponds to state transition S00 _k → S00 _{k + 1} and state transition S01 _k → S00
_This is equivalent to comparing which of the _{k + 1} paths has a larger path metric, that is, is more likely.

That is, Δ01 _k is the state S00 and the state S0
Since the difference is the path metric between the surviving paths that have transitioned to 1, the metric of the surviving path that has transitioned to state S00 is considered as a base point, and b00 _{k + 1} and Δ01 _k +
It is obtained by comparing with b10 _{k + 1} . This is b00
_{k + 1−} b10 _{k + 1} is compared with Δ01 _k . Therefore, the differential branch metric calculator 101 and the register 5
The state transition S00 _k → S00 _{k + 1} and the state transition S01 are performed by the operation of comparing the output of S01 with the comparator 201.
A determination result is obtained as to which of _k → S00 _{k + 1} is the surviving path. Therefore, the output of the comparator 204 is a state transition S10 _k → S11 _{k + 1} and a state transition S11 _k → S11 _{k + 1}
Are the surviving paths.

The state transitions S10 _k → S01 _{k + 1} and the state transitions S01 _k → S10 _{k + 1} do not exist because the minimum inversion interval has a run-length limit of two channel bits or more, and the state transitions S11 _k always exist. → S01 _{k + 1} , state transition S00
_{Since k} → S10 _{k + 1} is a surviving path, there is no need to make a determination.

The difference branch metric calculator 106 calculates b31 _{k + 1} and b0 from the input data at the time _{k + 1.}
A difference of 0 _{k + 1} is calculated. The output of the difference branch metric calculator 106 and the output of the register 506 are added by the adder 302. The surviving path temporarily changes state S00.
_{If k} → S00 _{k + 1} , the state transition S10 _k → S
Since 11 _{k + 1} is the survivor path, considering that starting from the S00 _k, the state transition S00 _k → S00 _{k + 1} path metrics b00 _{k + 1,} and the state transition S10 _k → S11 _{k + 1} path metrics Becomes Δ03 _k + b31 _{k + 1} and Δ01 _{k + 1}
Is the difference between the path transitioning to S00 _{k + 1} and the path transitioning to S01 _{k + 1} , so that Δ01 _{k + 1} = (Δ03 _k + b31 _{k + 1} ) −b00 _{k + 1} = Δ03 _k + (b31 _{k +1 -b00 k +} 1) Thus, the output of the adder 302, Δ01 _{k + 1} when the survivor path is that a state transition S00 _k → S00 _{k + 1}
Is shown. Similarly, the output of the adder 304 indicates Δ01 _{k + 1} when the surviving path is state transition S01 _k → S00 _{k + 1} .

The selector 407 selects one of the outputs of the adders 302 and 304 according to the result of the comparator 201,
Is output, and this output is stored in the register 501 as Δ01 _{k + 1} .
Is held. For example, if the output of the comparator 201 is 1, it indicates that the surviving path has undergone the state transition S01 _k → S00 _{k + 1.} Therefore, the output of the adder 304 is selected by the selector 401, and Δ01 It is held in the register 501 as _{k + 1} . This operation is performed simultaneously for all combinations of paths transiting from the surviving path regardless of the value of the judgment result of the surviving path judging means 2, so that there is no delay in the operation.

The process of calculating and holding Δ01 _{k + 1} has been described above. However, Δ01 _k , Δ23 _k , Δ02 _k , and Δ2
1 _k, Δ13 _k, Δ03 _k and _{b00 k + 1 ~b33 k + 1} Δ01 k + 1 _{using, Δ23 k + 1, Δ02 k} + 1, Δ21 k + 1, Δ1
The process of calculating and holding 3 _{k + 1} and Δ03 _{k + 1} is the same as described above, and a description thereof will be omitted. However, for Δ21 _{k + 1} , state transition S00 _k → S10 _{k + 1} and state transition S1
Since 1 _k → S01 _{k + 1} is always a surviving path, there is no need to select it, and the output of the adder 312 is unconditionally set to Δ21 _{k + 1}
Is held in the register 504. As for Δ03 _{k + 1} , one is selected from the adders 317 to 320 as in the first embodiment, and held in the register 506 as Δ03 _{k + 1} .

As described above, the registers 501 to 506 hold the difference between the path metrics of the surviving paths. In this example, there are four surviving paths, but the path metric difference between these surviving paths is always small at a practical level and does not increase each time data is input. It may be short. Therefore, the arithmetic processing of the adder, the comparator, and the like can be performed in a short time, so that high-speed operation can be performed.

The surviving path is determined by comparing the difference between each branch metric and the path metric between each surviving path. The path metric between the surviving paths is determined by the difference between the branch metric and the surviving path. The process can be performed simply and in a short time because the difference is obtained by adding the path metric difference between the two. The critical path in the feedback loop is either “comparator → selector → register” or “adder → selector → register”. And the processing time can be reduced as compared with the conventional apparatus "adder → comparator → selector → path metric normalization circuit → register", so that high-speed operation is possible. Further, even when the subtraction processing is necessary in the difference path metric calculation means 3, since the difference branch metric calculation means 1 adds 1 in advance, the subtraction processing can be performed if the input is inverted and added. In addition, the arithmetic processing time in the feedback loop can be reduced, and high-speed operation can be performed.

The data is decoded by the data decoding means 6 using the result of the surviving path judgment means 2. The data decoding means 6 includes a plurality of selectors 7 as shown in FIG.
And a plurality of registers 8.
And a register 8 constitute a shift register. The direction of the shift register is determined by the output of the surviving path determination means 2 in FIG. When the input S is 0, the input A is selected by the selector 7, and when the input S is 1, the input B is selected and output from the output Y. Therefore, the decoding result is selected in the first stage of the shift register depending on the state transition of the surviving path, and the decoding result of the surviving path is copied in the subsequent stages. If the number of stages of this shift register is increased to some extent,
The values of the last four registers are the same.

That is, going back to the past, the four surviving paths are converged into one path. Therefore, the decoding result of the surviving path remains as the same value in the four registers at the last stage of the shift register. Even if one of the last registers has a different value from the other registers, the majority logic circuit 9 selects the larger value. The data decoded by the shift register constituted by the selector 7 and the register 8 and the majority logic circuit 9 is selected from the four surviving paths finally left after the input of the final data of the decoded block. It is equivalent to data at the practical level when the most probable data is selected and decoded.

A reproduced signal of data which has been encoded and recorded using a code having a run length limitation of a minimum inversion interval of two channel bits or more is equalized to PR (1, 2, 1) characteristics, and this is subjected to maximum likelihood decoding. In this case, a lower data error rate can be obtained by decoding with the Viterbi decoding circuit shown in FIG. 6 than with the Viterbi decoding circuit shown in FIG.

Although the holding means 5 is arranged immediately after the difference path metric selecting means 4 in FIGS. 1, 2 and 6, this holding means may be arranged anywhere in the feedback loop. For example, it may be arranged immediately after the difference path metric calculation means 3. In this case, the output of the surviving path determining means 2 must be delayed by one clock to match the phase. Therefore, a register is arranged immediately after the surviving path determining means 2. The configuration of the decoding means 6 is the same as that shown in FIG.
Also, the present invention is not limited to FIG. 7, and any one of the four registers may be output without using the majority logic circuit 9. Also, after the final data of the decoding unit block is input, the one with the highest likelihood is selected from the four remaining surviving paths, and the data is decoded according to the transition state of the path. You may.

[0083]

According to the Viterbi decoding circuit of the present invention, the difference between the path metrics of each surviving path is fed back and used for the next calculation, so that the value does not increase each time the calculation is performed, and the calculation data does not increase. Can be operated at high speed without deteriorating the performance as in the case where the lower bits of the data to be fed back are truncated. In addition, no operation means for normalizing the operation result is required, the number of operation stages in the feedback loop is reduced, and the operation can be performed at high speed.

According to the Viterbi decoding circuit of the second aspect, each surviving path is determined by comparing the difference between each branch metric and the path metric difference between each surviving path calculated from the input data up to the previous time and fed back. Therefore, the surviving path can be determined by a simple operation, and the number of operation stages in the feedback loop can be reduced, and the operation can be performed at high speed.

According to the Viterbi decoding circuit of the third aspect, the difference between the path metrics is calculated based on the difference between each branch metric and each surviving path calculated and fed back from the difference between each branch metric and the previous input data. Since the calculation is performed by adding or subtracting the difference, the difference between each path metric can be calculated by a simple calculation, and the number of calculation stages in the feedback loop can be reduced to operate at high speed.

According to the Viterbi decoding circuit of the present invention, when the difference of the branch metric is calculated by subtracting the difference of the path metric between the surviving paths fed back from the calculation result of the difference of the branch metric, the calculation of the difference of the branch metric is performed. Since the value is equal to the value obtained by adding 1 to the original value, the process of taking the two's complement in the feedback loop is simplified, the number of operation stages is reduced, and high-speed operation can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a Viterbi decoding circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a first embodiment of a Viterbi decoding circuit according to the present invention.

FIG. 3 is a trellis diagram showing a state of state transition of PR (1, 2, 1) characteristics.

FIG. 4 is a block diagram illustrating a configuration of a data decoding unit of the Viterbi decoding circuit in FIG. 2;

FIG. 5 is a trellis diagram showing a state transition when the minimum inversion interval is recorded using a code of two or more channel bits and is equalized to PR (1, 2, 1) characteristics during reproduction. .

FIG. 6 is a block diagram showing a configuration of a second embodiment of the Viterbi decoding circuit according to the present invention.

FIG. 7 is a block diagram illustrating a configuration of a data decoding unit of the Viterbi decoding circuit in FIG. 6;

FIG. 8 is an explanatory diagram of a Viterbi decoding method for PR (1, 1) characteristics.

FIG. 9 is a block diagram illustrating a configuration of a conventional Viterbi decoding circuit.

FIG. 10 is a diagram showing an example in which the Viterbi decoding circuit shown in FIG.
It is a block diagram which shows the structure at the time of applying to a (1,2,1) characteristic.

FIG. 11 is a block diagram showing another configuration of a conventional Viterbi decoding circuit.

[Explanation of symbols]

 1 difference branch metric calculation means 2 surviving path determination means 3 difference path metric calculation means 4 difference path metric selection means 5 holding means 6 data decoding means

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI G11B 20/18 570 G11B 20/18 570F

Claims (4)

(57) [Claims] 1. A Viterbi decoding circuit for maximum likelihood decoding of data equalized by a partial response system or data encoded by a convolutional code, wherein the difference branch metric calculates a difference between each branch metric from input data. Calculating means, and surviving path determining means for determining each surviving path using the difference between the calculated branch metrics and the path metric difference between the surviving paths calculated and fed back from the previous input data and A difference path metric calculation unit for calculating a difference between each path metric using the calculated difference between each branch metric and a difference between each of the surviving paths, and a surviving path determining unit. From the output of the differential path metric calculation means, the path metric Difference path metric selecting means for selecting a difference, holding means for feeding back a difference in path metric between each surviving path calculated using input data up to the previous time to surviving path determining means and difference path metric calculating means, A Viterbi decoding circuit comprising: data decoding means for decoding data from the output of the path determination means. 2. The surviving path determining means compares the difference between the output of the differential branch metric calculating means and the path metric between the surviving paths calculated and fed back from input data up to the previous time to determine the surviving path. The Viterbi decoding circuit according to claim 1, wherein the determination is performed. 3. The difference path metric calculation means adds or subtracts a difference between an output of the difference branch metric calculation means and a path metric between surviving paths calculated and fed back from input data up to the previous time. 2. The method according to claim 1, wherein a difference between each path metric is calculated.
2. A Viterbi decoding circuit according to claim 1. 4. When the path metric calculation means subtracts a path metric difference between surviving paths calculated and fed back from input data up to the previous time from an output of the difference branch metric calculation means, the difference branch metric calculation means. The calculating means outputs a value equal to the value obtained by adding 1 to the original value, and the difference path metric calculating means calculates the difference between the path metrics between the surviving paths calculated from the input data up to the previous time and fed back. 2. The Viterbi decoding circuit according to claim 1, wherein the addition is performed after inversion.