JPH0964756A - Viterbi decoding circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of a decoding memory by optimizing how to select a survival path. SOLUTION: A branch metric arithmetic section 1 calculates a branch metric of each branch. An adder section 2 uses a branch metric to be calculated to obtain a path metric of each survival path. When competitive inputs A, B are equal to each other, a path metric value of a path transiting to a state S00 via a state S00 and a path metric value of a path transiting to a state S11 via the state S11 are given to a comparator section 3 and a selection section 4 selecting the input A. When the path metric values of competitive paths are identical to each other, a path transiting to a state S00 via the state S00 or a path transiting to a state S11 via the state S11 is used for a survival path. As a result, a converging time of a transition pattern taking much time for convergence of the path is minimized to reduce the capacity of the decoding memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding circuit used in a data detection circuit for reproducing information recorded on an optical disc or the like.

[0002]

2. Description of the Related Art In recent years, as a method for detecting data recorded on an optical disk device, a PRML detection method combining a partial response method and Viterbi decoding has been attracting attention.

When high density recording is performed on an optical disk,
The quality of the reproduced signal is deteriorated and the error rate is deteriorated. As signal processing for improving the deterioration of the quality of the reproduced signal and the deterioration of the error rate, the reproduced signal has a PR (1,2,1) characteristic (when an isolated 1 bit is reproduced, the amplitude ratio at each sampling point is Is equal to “2”, is “1” on both sides, and is equal to “0” in other cases), and the PR (1,2,
1) A data detection method has been proposed in which a signal equalized in characteristics is subjected to maximum likelihood decoding by Viterbi decoding. Further, the data is converted so that the minimum inversion interval becomes 2 channel bits or more and recorded on the optical disc, and the reproduction signal from this optical disc is equalized to the PR (1,2,1) characteristic, and the minimum inversion interval is 2 channels. The property of being more than a bit and PR (1,
2, 1) By the Viterbi decoding circuit using the characteristics, the P
A data detection method has also been proposed which performs maximum likelihood decoding of a signal equalized to the R (1,2,1) characteristic.

The concept of the Viterbi decoding will be described below. FIG. 5 is a trellis diagram of Viterbi decoding using the characteristic that the minimum inversion interval is 2 channel bits or more and the PR (1,2,1) characteristic. In FIG. 5, S00, S10, S01 and S11 represent transition states in the PR (1,2,1) characteristic, for example, state S10.
Indicates that the recording data two bits before is “0” and the recording data one bit before is “1”. That is,
Assuming that the current state is S00 and the next recording data is "0", the state transits to state S00 at the next time. On the other hand, if the next recording data is "1", the state transits to the state S10 at the next time point. Here, in FIG. 5, the states S10 to S
The transition to 01 and the transition from state S01 to state S10 are not described. This is because the conversion of the minimum inversion interval is 2 channel bits or more, so that the recorded data is ... 0
This is because there is no data sequence such as 10 ... Or ... 101 ... And such a state transition is not considered.

In FIG. 5, recorded data when the state transition occurs is described on the left side of the slash "/", and PR when the state transition occurs on the right side of the slash "/".
The expected value of the reproduced signal after (1, 2, 1) equalization is described. Here, the expected value has four values of d0, d1, d3 and d4. The expected value does not include d2 because the minimum inversion interval is 2 channel bits or more.

The data obtained from the optical disk or the like can be considered to be the expected value in which noise, equalization error and the like are superimposed. Therefore, in Viterbi decoding, the probability of a path on the trellis diagram is calculated based on the difference between the input data and this expected value. Then, which path is most probable is determined, and the print data (that is, the value on the left side of the slash /) corresponding to the most probable path is output as the decoded data corresponding to the input data.

Originally, the input data of the Viterbi decoding circuit is A
Since it is output data from the D converter or the like, the input data and the expected value are values represented by several bits. However, in the following description, for simplicity, it is expressed in decimal as follows. d0 = 0 d1 = 1 d3 = 3 d4 = 4

The Viterbi decoding operation will be described below by taking an example. In the above Viterbi decoding, the probability (branch metric) for each state transition is calculated by the following formula. − (Y−d) ² where y: input data of the Viterbi decoding circuit d: expected value for each state transition Further, the probability (path metric) of each path is a value obtained by adding each branch metric, and these It can be said that the larger the value, the more certain.

For example, FIG. 6 shows input data ...
The state transition when 0.1 0.8 2.6 ... Is input to the Viterbi decoding circuit is expressed by a trellis diagram. Hereinafter, the path A shown by the thick solid line and the path B shown by the thick broken line in FIG. 6 will be described. In FIG. 6, the branch metric of branch A0 has input data of "0.
"And the expected value" 1 because 0 "-. (0.1-0) ² = -0.1 ² = -0.01 Similarly, branch metric of a branch A1 is input The data is "0.8" and the expected value is "1"
Therefore, it is “−0.04”. Also, branch A2
The branch metric is “−0.16” because the input data is “2.6” and the expected value is “3”.
Therefore, the path metric of the path A is "-0.21" by adding the branch metrics of the branches A0, A1 and A2.

On the other hand, the branch metric of the branch B0 is -0.81 because the input data is 0.1 and the expected value is 1. The branch metric of branch B1 is 0.8 for input data and 3 for expected value.
Therefore, it is -4.84. The branch metric of the branch B2 is -1.96 because the input data is 2.6 and the expected value is 4. Therefore, the path metric of the path B is "-7.61" by adding the branch metrics of the branches B0, B1 and B2.

The two paths, path A and path B, are
The state S11 intersects at time t3. Therefore, the path metrics of the two paths are compared at the time of this crossing, and the path of the more probable path (that is, the path with the larger path metric value) is left as the surviving path. That is, in the example shown in FIG. 6, since the path metric (-0.21) of the path A is larger than the path metric (-7.61) of the path B, the path A remains as a surviving path. Of. In this case, it is assumed that the path A or the path B remains in both the state S00 at the time point t1 and the state S11 at the time point t2.

In the above example, only two paths, path A and path B, have been described, but in reality,
It seems likely that the path metrics of two paths will be compared in each state at each time point (the path metric is large).
The work to leave the other pass is performed. That is, in the case of the above example, the state S00 at the time t1 is changed to the state S0.
The path metrics of the path transiting to state S00 via 0 and the path transiting to state S00 via state S01 are compared, and the path having the larger path metric value is left as a surviving path. In the state S11 at the time point t2,
A path that transits to state S11 via state S11 and state S10
The path having the larger path metric value among the paths transiting to the state S11 via the path is left as the surviving path. In this way, four passes will always remain as surviving passes.

Thus, the above time points are changed from time point t0 to time point t3.
The surviving bus at time 0 converges to one as time goes toward, and the recorded data (the value written on the left side of the slash /) corresponding to the path converged to this one is output as decoded data. . At that time, a memory for decoding (hereinafter sometimes simply referred to as a memory) for storing path transition information or a candidate for decoded data is necessary in order to realize an operation that goes back in the past. here,
In the present embodiment, the number of past bits of the transition information of the recorded data or the candidate for the decoded data to be stored is represented by the number of bits and called the memory depth.

[0014]

However, the reproduction signal from the recording medium on which the converted data is recorded such that the minimum inversion interval is 2 channel bits or more is PR (1,2,1). The Viterbi decoding circuit that performs maximum likelihood decoding of a signal equalized in characteristics has the following problems. That is, as described above, it is necessary to store path transition information or decoded data candidates in the above memory in order to realize the operation that is going on in the past. In that case, the depth of the memory includes, for example, in FIG. 6, a path that transits to state S00 via state S00 at state t00 at time t1 and a path that transits to state S00 at state t01. Which path is to be a surviving path when the path metric values of
When the path metric value of the path transiting to the state S11 via 1 and the path transiting to the state S11 via the state S10 are equal, a difference occurs depending on which path is the surviving path. .

Therefore, if the method of selecting the surviving path is not appropriate, there is a problem that the depth of the memory becomes unnecessarily large. On the other hand, when the depth of the memory is insufficient, there is a problem that decoded data is output and a decoding error occurs before the surviving paths converge to one.

Therefore, an object of the present invention is to PR the reproduced signal from the recording medium on which the data converted such that the minimum inversion interval becomes 2 channel bits or more is recorded.
An object of the present invention is to provide a Viterbi decoding circuit capable of reducing the depth of a decoding memory by optimizing the method of selecting a survivor path when performing maximum likelihood decoding of a signal equalized to a (1,2,1) characteristic. Another object of the present invention is to provide a Viterbi decoding circuit that does not have a decoding error due to a lack of depth of memory for decoding.

[0017]

In order to achieve the above object, the invention according to claim 1 is a recording medium in which data converted such that the minimum inversion interval is 2 channel bits or more is recorded. Is a Viterbi decoding circuit for performing maximum likelihood decoding on a reproduction signal obtained by equalizing the reproduction signal of FIG. 1 to a PR (1,2,1) characteristic, and a path metric value and a state of a path that transits to state S00 via state S00. If the value of the path metric of the path transiting to state S00 via S01 is equal, the path transiting to state S00 via state S00 is selected as the surviving path while the path transiting to state S11 is selected. State S
When the value of the path metric of the path transiting to 11 and the value of the path metric of the path transiting to state S11 via state S10 are equal, the path transiting to state S11 via state S11 is survived. It is characterized by selecting as a path.

According to the above configuration, when the path metric values of the two paths transiting to the state S00 or the path metric values of the two paths transiting to the state S11 are equal, the surviving path is optimally selected. The path will converge faster. Thus, even if the depth of the decoding memory is small, the decoding can be performed correctly.

Further, in the invention according to claim 2, the reproduction signal from the recording medium on which the data converted such that the minimum inversion interval becomes 2 channel bits or more is recorded is PR.
A Viterbi decoding circuit that performs maximum likelihood decoding of a reproduction signal equalized to a (1, 2, 1) characteristic, in which a branch metric calculator calculates a branch metric based on input data, and an adder calculates the branch metric. The branch metric is added to the path metric of the surviving path to obtain the path metric of the surviving path at the next point in time, and the selector selects the path metric of the path transiting from the state S00 to the state S00 and the state S01. If the value of the path metric of the path transiting to state S00 is equal, the path transiting to state S00 via state S00 is selected as the surviving path while the path S11 transits to state S11 via state S11.
When the value of the path metric of the path transiting to the state is equal to the value of the path metric of the path transiting to the state S11 via the state S10, the path transiting to the state S11 via the state S11 is selected as the surviving path. It is characterized by that.

In the above configuration, the adder adds the path metric of the surviving path and the branch metric calculated by the branch metric calculator to obtain the path metric of the surviving path at the next time point. Then, when the values of the path metrics of the two paths transiting to the state S00 are equal, the selecting section selects the path transiting to the state S00 via the state S00 as the surviving path. Similarly, when the path metric values of the two paths transiting to the state S11 are equal, the state S
The path that transits to the state S11 via 11 is selected as the surviving path. In this way, as a result of selecting the surviving path optimally, the convergence of the path is accelerated, and the decoding is correctly performed even if the depth of the decoding memory is small.

According to a third aspect of the present invention, in the Viterbi decoding circuit according to the second aspect of the present invention, the transition information of the surviving path is generated when the surviving path is selected by the selecting section, and the generation is performed. It is characterized by having 10 or more transition information storage means for storing each of the transition information at each of the above-mentioned time points.

In the above structure, every time a surviving path is obtained by the selecting section, transition information of the surviving path at that time is generated. Then, each of the generated transition information at each time is sequentially stored in the transition information storage means. At this time, the survivor path is optimally selected and the path convergence is accelerated as in the invention according to claim 2. Therefore, the number of transition information storage means required in the transition pattern in which the path convergence takes the longest time is 10 or more. Therefore, even if the transition pattern takes the longest to converge a path, all the transition information generated until the path converges is held in the transition information storage means and correctly decoded.

In the invention according to claim 4, the selection unit in the Viterbi decoding circuit according to the invention according to claim 3 is set to the state S00.
If the value of the path metric of the path transiting to the state S00 via the state and the value of the path metric of the path transiting to the state S00 via the state S01 are equal, the state transits to the state S00 via the state S01. A Viterbi decoding circuit adapted to select a path as a surviving path is characterized by having twelve or more transition information storage means.

According to the above configuration, the number of transition information storage means required in the transition pattern in which the path convergence takes the longest time is 12 or more. Therefore, the number of the transition information storage means is more than the number required for the transition pattern that takes the longest time to converge the path, and all the transition information generated until the path converges is stored in the transition information storage means. And it is decrypted correctly.

According to the invention of claim 5, the selection unit in the Viterbi decoding circuit of the invention of claim 3 is set to the state S11.
If the value of the path metric of the path transiting to the state S11 via the state and the value of the path metric of the path transiting to the state S11 via the state S10 are equal, the state transits to the state S11 via the state S10. A Viterbi decoding circuit adapted to select a path as a surviving path is characterized by having twelve or more transition information storage means.

According to the above configuration, the number of transition information storage means required for the transition pattern in which the path convergence takes the longest time is 12 or more. Therefore, the number of the transition information storage means is more than the number required for the transition pattern that takes the longest time to converge the path, and all the transition information generated until the path converges is stored in the transition information storage means. And it is decrypted correctly.

Further, in the invention according to claim 6, the reproduction signal from the recording medium on which the data converted such that the minimum inversion interval becomes 2 channel bits or more is recorded is PR.
A Viterbi decoding circuit that performs maximum likelihood decoding of a reproduction signal equalized to (1,2,1) characteristics, including a branch metric calculation unit that calculates a branch metric of each branch based on input data, and a path metric of a surviving path. And a branch metric calculated by the branch metric calculation unit to obtain a path metric at the next time point of the surviving path, and a state S00 via a state S00.
The first input value is the path metric obtained by the adding unit of the path that transits to S1, and the second input value is the path metric obtained by the adding unit of the path that transits to state S00 via state S01. If the two input values are different, the larger one of the input values is output, and if the two input values are the same, the first selection unit that selects and outputs the first input value, and the state S11 The path metric obtained by the adder of the path transiting to the state S11 via S1 is used as the first input value, while the path determined by the adder of the path transiting to the state S11 via the state S10 The metric is used as the second input value, and when the two input values are different, the larger one is output, while when the two input values are the same, the first input value is selected and output. Selector and the first and second , The path metric of the path that transits to the state S10 via the state S00 and the path metric of the path that transits to the state S01 via the state S11 obtained by the adder. It is characterized by comprising a holding unit for holding the path metric as a path metric of a surviving path at the next point in time, and a data decoding unit for generating decoded data based on the selection result in the first and second selecting units. There is.

In the above configuration, the adder adds the path metric of the surviving path and the branch metric calculated by the branch metric calculator to obtain the path metric of the surviving path at the next time point. Then, while the path metric of the path transiting to the state S00 via the state S00 is input to the first selection unit as the first input value, the path metric of the path transiting to the state S00 via the state S01 is The second input value is input to the first selection unit. Similarly, the path metric of the path transiting to the state S11 via the state S11 is input to the second selecting unit as the first input value, while the path metric of the path transiting to the state S11 via the state S10. Is input to the second selection unit as the second input value.

Here, the first and second selectors output the larger input value when the two input values are different, while the first input value is output when the two input values are equal. To output. Therefore, in the first selecting unit, when both input values are equal, the path transiting to the state S00 via the state S00 is selected as the surviving path. Similarly, in the second selecting unit, when both input values are equal, the path transiting to the state S11 via the state S11 is selected as the surviving path.

Then, the path metric output from the above two selectors and the state S10 via the state S00 are set.
The path metric of the path that transits to the state and the path metric of the path that transits to the state S01 via the state S11 are stored in the storage unit as the path metric of the surviving path at the next time point. After that, the data decoding unit generates decoded data based on the selection results of the first and second selection units.

As described above, as a result of the first and second selecting sections selecting the surviving path optimally, the path converges quickly and the decoding is correctly performed even if the decoding memory has a small depth.

According to a seventh aspect of the present invention, in the Viterbi decoding circuit according to the sixth aspect of the invention, the data decoding unit transitions the surviving path when the surviving path is selected by the selecting unit. Transition information generating means for generating information based on the selection result by the first and second selecting units, and 10 or more transition information storing each of the transition information at each time point generated by the transition information generating means. It is characterized by including storage means and decoded data output means for outputting the decoded data based on the transition information stored at the end when the transition information is stored in all the transition information storage means.

In the above structure, the first and second selectors cause the path to transit to state S00 via state S00 or transit to state S11 via state S11 when both input values are equal. The path is selected as the surviving path. As a result, the surviving path is optimally selected so that the convergence of the path can be accelerated, and the number of transition information storage means required in the transition pattern in which the path convergence takes the longest time is 10 or more. Therefore, the number of the above-mentioned transition information storage means becomes more than the number required for the transition pattern that takes the longest time to converge the path, and the decoded data is correctly output without being output before the path converges.

In the invention according to claim 8, the contents of the first input value and the contents of the second input value in the first selecting unit of the Viterbi decoding circuit of the invention according to claim 7 are reversed. In the Viterbi decoding circuit, the data decoding section is characterized by having 12 or more transition information storage means.

In the above-mentioned configuration, when the both input values are equal, the first selecting unit selects the path that transits to the state S00 via the state S01 as the surviving path. As a result, the number of transition information storage means required in the transition pattern that takes the longest to converge the path is 12 or more. Therefore, the number of the above-mentioned transition information storage means becomes more than the number required for the transition pattern that takes the longest time to converge the path, and the decoded data is correctly output without being output before the path converges.

According to a ninth aspect of the invention, the contents of the first input value and the contents of the second input value in the second selecting section of the Viterbi decoding circuit of the invention according to the seventh aspect are reversed. In the Viterbi decoding circuit, the data decoding section is characterized by having 12 or more transition information storage means.

In the above structure, when the two input values are equal, the second selecting unit selects the path that transits to the state S11 via the state S10 as the surviving path. As a result, the number of transition information storage means required in the transition pattern that takes the longest to converge the path is 12 or more. Therefore, the number of the above-mentioned transition information storage means becomes more than the number required for the transition pattern that takes the longest time to converge the path, and the decoded data is correctly output without being output before the path converges.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram of the Viterbi decoding circuit according to the present embodiment. In this Viterbi decoding circuit, a reproduced signal from a recording medium on which data converted such that the minimum inversion interval is 2 channel bits or more is recorded is equalized to PR (1,2,1) characteristics. It is a decoding circuit for performing maximum likelihood decoding on a signal, and is roughly configured by a branch metric calculation unit 1, an addition unit 2, a comparison unit 3, a selection unit 4, a holding unit 5, and a data decoding unit 6.

The branch metric calculator 1 calculates a branch metric based on input input data (for example, reproduced data of digital data recorded on an optical disk). Here, assuming that the input data is y, the branch metric calculator 1 calculates a branch metric using expected values 0, 1, 3, 4 at each state transition as follows, and outputs A to F. Are output to six different adders 2. Transition from state S00 to state S00:-(y-0) ^2- > output A Transition from state S01 to state S00:-(y-1) ^2- > output B Transition from state S00 to state S10:-(y -1) ² → output C transition from state S11 to state S01:-(y-3) ² → output D transition from state S10 to state S11:-(y-3) ² → output E state S11 to state S11 Transition to :-( y-4) ² → Output F

The adder 2 adds the branch metric value from the branch metric calculator 1 and the path metric value of the surviving path held in the holding unit 5 at the previous time. Then, each of the adders 2 to which each of the outputs A, B, E and F is input sends the obtained result to the comparator 3. On the other hand, each adder 2 to which each of the outputs C and D is input sends the obtained result to the two holding units 5b and 5c of the four holding units 5 and holds them.

The comparison section 3 compares the input A and the input B (both are path metric values obtained by the addition section 2) and outputs an output Y representing the comparison result. The output Y at that time is as follows. When input A ≧ input B output Y = 0 When input A <input B output Y = 1 The output Y thus output is sent to the data decoding unit 6. Then, as will be described later in detail, the data decoding unit 6 generates and outputs the decoded data based on the comparison result (output Y) by the comparison unit 3.

The selecting unit 4 receives the same inputs A and B as those of the comparing unit 3 and inputs the output Y from the comparing unit 3 to the input S.
As the output Y, either the input A or the input B is selected according to the value of the input S and is output as the output Y. The output Y at that time is as follows. When input S = 0, output Y = input A, when input S = 1, output Y = input B That is, the selection unit 4 has the larger input value of the input A and the input B (that is, the larger path metric value). When the input A and the input B are the same, the input A is selected and output. In this way, the value selected by the selection unit 4 is sent to and held by the other two holding units 5a and 5d different from the two holding units 5b and 5c.

The Viterbi decoding circuit having the above structure operates as follows. That is, the branch metric calculator 1
Calculates the branch metric of each branch as described above. Then, the addition unit 2a outputs the output A (state S00 from the branch metric calculation unit 1 to the path metric value of the surviving path that has transited to the state S00 at the previous time (that is, the path metric value stored in the holding unit 5a). To the state S00) is added, and the path metric value of the path transiting to the state S00 via the state S00 at the next time point is calculated. Similarly, the addition unit 2
b calculates the path metric value of the path transiting to the state S00 via the state S01, the adder 2c calculates the path metric value of the path transiting to the state S10 via the state S00, and the adder 2d calculates The addition unit 2e calculates the path metric value of the path transiting to the state S01 via the state S11, the addition unit 2e calculates the path metric value of the path transiting to the state S11 via the state S10, and the addition unit 2f calculates the state S11. Via state S1
Calculate the path metric value of the path that transits to 1.

Then, the path metric value of the path transiting to the state S10 via the state S00 calculated by the adder 2c is stored as it is in the holding unit 5b as the path metric value of the surviving path. Similarly, the path metric value of the path transiting to the state S01 via the state S11 calculated by the adding unit 2d is stored in the holding unit 5c as the path metric value of the surviving path.

On the other hand, the state S0 calculated by the adder 2a
The path metric value of the path transiting to the state S00 via 0 is input as the input A to the comparison unit 3a and the selection unit 4a. The path metric value of the path transiting to the state S00 via the state S01 calculated by the adder 2b is input as the input B. Here, as described above, when the comparison unit 3 and the selection unit 4 cooperate with each other to select and output the larger input value of the input A and the input B, and the input A and the input B are equal. , The input A is selected and output. Therefore, the comparing unit 3a and the selecting unit 4a have a larger one of the path metric value of the path transiting to the state S00 via the state S00 and the path metric value of the path transiting to the state S00 via the state S01. Select one of the path metric values and output. On the other hand, when the path metric values of both paths are equal, the path metric value of the path transiting to the state S00 via the state S00 is selected and output.

In this way, the more probable path is selected by the selecting section 4a. At that time, if the path metric values of the path transiting to the state S00 via the state S00 and the path transiting to the state S00 via the state S01 are equal, the status S00 is transited via the state S00.
The path that transits to is selected.

On the other hand, the path metric value of the path transiting to the state S11 via the state S10 calculated by the adder 2e is input as the input B to the comparator 3b and the selector 4b. The path metric value of the path transiting to the state S11 via the state S11 calculated by the adder 2f is input as the input A. Therefore, the comparing unit 3b and the selecting unit 4b cooperate to obtain the path metric value of the path transiting to the state S11 via the state S10 and the path metric value of the path transiting to the state S11 via the state S11. home,
Select and output the larger path metric value. On the other hand, when the path metric values of both paths are equal,
The path metric value of the path transiting to the state S11 via the state S11 is selected and output.

In this way, the more likely path is selected by the selecting section 4b. At that time, if the path metric values of the path transiting to the state S11 via the state S11 and the path transiting to the state S11 via the state S10 are equal, the status S11 is transited via the state S11.
The path that transits to is selected.

The operation of the Viterbi decoding circuit having the above configuration will be described below in more detail with reference to specific examples. FIG. 3 is a trellis diagram showing the state of decoding when no noise is superimposed on the input data input to the Viterbi decoding circuit. The pattern shown in FIG. 3 is a transition pattern that requires the most time to converge the surviving paths. In FIG. 3, the input data, the path metric value of the path transiting to the state S00 via the state S00, and the path metric value of the path transiting to the state S00 via the state S01 are shown below the trellis diagram. , The path metric value of the path transiting to the state S11 via the state S10, and the path metric value of the path transiting to the state S11 via the state S11 are also shown.

Further, in the pattern shown in FIG. 3, time t0
In the above, it is assumed that the number of paths that transit to the state S11 converge to one and that there is only one surviving path. However, due to the calculation of the path metric, there are four surviving paths at time t0. The path metrics of the surviving paths are all "0" and are equal.

As described above, the branch metric calculator 1 calculates the branch metric value for each branch based on the input data at each time point in FIG. 3, and the adder 2 calculates the path metric for each survivor path. Calculate the value. Then, the comparison unit 3 and the selection unit 4 cooperate with each other,
The path metric values of two paths competing as a result of the transition to state S00 and state S11 are compared, and the path having the larger path metric value is selected as the surviving path. At this time, when the path metric values of the two competing paths are equal, the status S00 is passed through the status S00.
State S11 via the path transiting to 00 or state S11
The path that transits to is selected as the surviving path.

By the way, in FIG. 3, assuming that the path a indicated by the thick solid line is a true path, the paths indicated by other thin solid lines with a cross added are compared in path metric value with the true path a. Loses and disappears. However, the thick-broken path b is a wrong path and remains as a surviving path. Therefore, at time t10, the path metric value of the path transiting to the state S00 via the state S00 and the path metric value of the path transiting to the state S00 via the state S01 are both equal to "-26". In this case, which of the paths is the surviving path becomes a problem.

Here, in the Viterbi decoding circuit according to the present embodiment, as described above, as shown in FIG. 3A, the path transiting from the state S00 to the state S00 is regarded as the surviving path. Therefore, the erroneous path b indicated by the thick broken line disappears at time t10. As a result, time t
The path exiting from each state at 0 is 1 of the true path a at time t10.
Only the book becomes available, and the state transition is finalized and the decoded data is finalized. On the other hand, as shown in FIG. 3B, if the path that transits to the state S00 via the state S01 is the surviving path, the erroneous path b survives until the time t12. As a result, the state transition is not fixed until time t12.

That is, in the Viterbi decoding circuit according to the present embodiment, if the memory for storing the transition information of the path (or the candidate of the decoded data) at the time of decoding has a depth of at least 10 bits, accurate decoded data can be obtained. Can be output. However, in the case of FIG. 3B, the depth of memory required for decoding is at least 12 bits in order to output accurate decoded data.

FIG. 4 shows another transition pattern that requires the longest time to converge the surviving path, input data, the path metric value of the path transiting to the state S00 via the state S00, and the state S00 via the state S01. The path metric value of the path transiting to S, the path metric value of the path transiting to state S11 via state S10, and the path metric value of the path transiting to state S11 via state S11 are shown.

In the case of FIG. 4 as well, when the Viterbi decoding circuit according to the present embodiment is used, as shown in FIG. 4A, the path that transits to the state S11 via the state S11 is the surviving path. Therefore, the erroneous path d indicated by the thick broken line disappears at time t10. As a result, the state transition is fixed at time t10 and the decoded data is fixed. On the other hand, as shown in FIG. 4B, if the path that transits to the state S11 via the state S10 is the surviving path, the erroneous path d survives until the time t12. As a result, time t12
The state transition is not fixed until.

That is, in the Viterbi decoding circuit according to the present embodiment, the depth of the decoding memory can be at least 10 bits even in the case of FIG. 4, and it can be made smaller than in other cases.

As described above, in the Viterbi decoding circuit according to the present embodiment, the branch metric of each branch calculated by the branch metric calculator 1 is used to add the path metric of each surviving path at the next time point by each adder 2. Find the value. Then, in cooperation with each other, the larger input value of the input A and the input B is selected and output, while the input A
And the input B are equal, the input A is selected and output as the input A in the two comparing units 3 and the selecting unit 4 via the state S00 obtained by the adding unit 2 Path metric value of path transiting to S00 and status S11
While inputting the path metric value of the path transiting to the state S11 via S1, the path metric value of the path transiting to the state S00 via the status S01 and the state S are input as input B.
The path metric value of the path transiting to the state S11 via 10 is input. Therefore, when the path metric value of the path transiting to the state S00 via the state S00 is equal to the path metric value of the path transiting to the state S00 via the state S01, the status S00 is transmitted via the state S00. The path that transits to can be the surviving path. If the path metric value of the path transiting to the state S11 via the state S11 and the path metric value of the path transiting to the state S11 via the state S10 are equal, the status S11 is transmitted via the state S11. The path that transits to can be the surviving path.

That is, according to the Viterbi decoding circuit of the present embodiment, when no noise is superimposed on the input data, the time required for path convergence in the transition pattern which takes the longest time for path convergence is calculated from time t0. It can be suppressed by time t10. Therefore, the depth of the decoding memory can be 10 bits.

In the actual case, since noise is superimposed on the reproduced signal, the decoding memory requires a depth of 10 bits or more. Even in that case, the depth of the decoding memory can be made smaller than that in the other selection method according to the selection method of the survivor path of the Viterbi decoding circuit according to the present embodiment.

Next, the data decoding unit 6 will be described in more detail. FIG. 2 is a detailed block diagram of the data decoding unit 6 in FIG. The data decoding unit 6 is composed of a plurality of selectors 7 and a plurality of registers 8,
Each selector 7 and the register 8 form a shift register. Then, in this shift register, the shift direction is determined as follows based on the value of the output Y of the comparison unit 3 in FIG. That is, the data decoding unit 6
When the output Y of the comparison unit 3 input to the input terminal G or the input terminal H is “0” (that is, when the input S of the selector 7 is “0”), the selector 7 outputs the input A. Select and output Y
Is sent to the register 8. On the other hand, the output Y of the comparison unit 3
Is "1" (that is, the input S of the selector 7 is "1"), the selector 7 selects the input B and sends it to the register 8 as the output Y.

As a result, in FIG. 2, the state transition of the surviving path is shown in the first stage of the shift register which is composed of the two selectors 7 and the four registers 8 closest to the comparator 3. The corresponding decoding result is stored.
Then, the decoding result of the surviving path is copied to the second and subsequent stages of the shift register. That is, 4
The operation of storing the decoded data candidates corresponding to the surviving path of the book in the register 8 and rewriting the decoded data candidate of the disappeared path to the decoding result of the surviving path each time the surviving path is determined. This is done sequentially at each stage of the register. By doing so, when the surviving path has converged to one, the values stored in the four registers 8 forming the stages of the shift register corresponding to that time are all the same. Therefore, the data decoding unit 6 may output the decoding result of the surviving path stored in one of the four registers 8 storing the same value in that case as the decoded data O.

Here, the above means that each stage in the shift register corresponds to the depth of the decoding memory. By the way, as mentioned above,
In the Viterbi decoding circuit having the configuration of FIG. 1, even if the input data has a transition pattern that takes the longest time to converge the path as shown in FIG. 3 or 4, the depth of the decoding memory is 10 bits or more. If so, accurate decoded data can be output. Therefore, in the Viterbi decoding circuit of the present embodiment, the number of stages of the shift register that constitutes the data decoding unit 6 is set to 10 or more (that is, one stage formed by two selectors 7 and four registers 8). 10 minutes or more shift registers are provided). By doing so, even if the input data has a transition pattern that takes the longest time to converge the surviving path, the decoding result is written in all stages of the shift register before the surviving path converges, and the decoded data O is output. It is possible to prevent the occurrence of a decoding error due to the error.

In the Viterbi decoding circuit according to the above embodiment, the output Y of the adder 2a is compared with the comparator 3a and the selector 4a.
While the input A to the
And input B to the selection unit 4a. However, if the correspondence between the output and the input is reversed, the path metric value of the path transiting to the state S00 via the state S00 calculated by the adder 2a and the state S01 calculated by the adder 2b are passed. Then, when the path metric value of the path transiting to the state S00 is equal, the Viterbi decoding circuit can be configured so that the path transiting to the state S00 via the state S01 is the surviving path. In that case, even if the input data has a transition pattern that requires the most time for the survival path to converge, as shown in FIGS. 3 and 4, if the decoding memory depth is 12 bits or more, it is accurate. It is possible to output various decoded data. Therefore, in this case, by setting the number of stages of the shift register configuring the data decoding unit 6 to 12 or more, it is possible to prevent the occurrence of a decoding error due to outputting the decoded data O before the surviving path converges. is there.

Similarly, in the Viterbi decoding circuit according to the above embodiment, the output Y of the adder 2f is used as the input A of the comparator 3b and the selector 4b, while the output Y of the adder 2e is used as the comparator 3b. The input B to the selection unit 4b is used. However,
By reversing the correspondence between the output and the input, when the path metric value of the path transiting to the state S11 via the state S11 is equal to the path metric value of the path transiting to the state S11 via the state S10. To state S via state S10
The Viterbi decoding circuit can be configured so that the path that transits to 11 becomes the surviving path. In that case, even if the input data has a transition pattern that requires the most time for the survival path to converge, if the depth of the decoding memory is 12 bits or more, accurate decoded data can be output. Therefore, also in this case, by setting the number of stages of the shift register configuring the data decoding unit 6 to 12 or more, the decoded data O can be obtained before the surviving path converges.
It is possible to prevent the occurrence of a decoding error due to the output of.

In the above embodiment, the branch metric calculator 1 calculates the branch metric according to the following equation:-(y-d) ² where y: input data d: expected value selector 4 The larger path metric value is selected as more likely. However, the present invention is not limited to this, and the branch metric calculator 1 calculates the branch metric by (y−d) ² and the selector 4 selects the smaller path metric value as more probable. It doesn't matter. Further, the branch metric calculation unit 1 may calculate the branch metric by using an equation such as 2y · d−d ² obtained by modifying the above equations.

[0067]

As is apparent from the above, the Viterbi decoding circuit according to the first aspect of the present invention can be used in the state S when the path metric values of two paths transiting to the state S00 are equal.
A path that transits to state S00 via 00 is selected as a surviving path, while two paths transiting to state S11 have the same path metric value, a path transiting to state S11 via state S11. Is selected as the surviving path, the reproduction signal from the recording medium on which the converted data is recorded so that the minimum inversion interval is 2 channel bits or more is equalized to the PR (1,2,1) characteristic. When maximum likelihood decoding is performed on the reproduced signal, the surviving path can be selected so that the path converges quickly.

Therefore, according to the present invention, the depth of the decoding memory can be reduced by optimizing the survival path selection method.

Also, in the Viterbi decoding circuit according to the second aspect of the present invention, the selecting unit makes a transition to the state S00 based on the path metric at the next time point of the surviving path obtained by the branch metric calculating unit and the adding unit. If the path metric values of the two paths are equal, the status is S00.
The path that transits to state S00 via S is selected as the surviving path, while if the path metric values of the two paths transiting to state S11 are equal, the path transiting to state S11 via state S11 is selected. Since it is selected as the surviving path, the reproduction signal from the recording medium on which the converted data is recorded so that the minimum inversion interval is 2 channel bits or more is equalized to the PR (1,2,1) characteristic. When performing maximum likelihood decoding on the reproduced signal, the surviving path can be selected so that the path converges quickly.

Therefore, according to the present invention, the depth of the decoding memory can be reduced by optimizing the survival path selection method.

Further, in the invention according to claim 3, the transition information of the surviving path is generated at the time point when the surviving path is selected by the selecting unit, and the transition information at each time point is generated. 1 for storing transition information storage means
Since it has 0 or more, even in the case of a transition pattern in which the path takes the longest to converge, all the transition information generated at each time until the path converges can be held in the transition information storage means. Therefore, according to the present invention, the decoding memory can be optimized by eliminating the decoding error.

Further, in the invention according to claim 4, when the path metric values of the two paths transiting to the state S00 are equal, the path transiting to the state S00 via the state S01 is selected as the surviving path. In the Viterbi decoding circuit configured as above, since the transition information storage means is 12 or more,
Even in the case of a transition pattern in which the path takes the longest to converge, all the transition information generated at each time until the path converges can be held in the transition information storage means. Therefore, according to the present invention, the decoding memory can be optimized by eliminating the decoding error.

Further, in the invention according to claim 5, when the path metric values of the two paths transiting to the state S11 are equal, the path transiting to the state S11 via the state S10 is selected as the surviving path. In the Viterbi decoding circuit configured as above, since the transition information storage means is 12 or more,
Even in the case of a transition pattern in which the path takes the longest to converge, all the transition information generated at each time until the path converges can be held in the transition information storage means. Therefore, according to the present invention, the decoding memory can be optimized by eliminating the decoding error.

Further, the Viterbi decoding circuit of the invention according to claim 6 outputs the larger input value when the two input values are different from each other, and outputs the first input value when the two input values are equal.
It has first and second selectors for selecting and outputting input values,
As the first input value and the second input value in the first selecting unit, the path metric of the path transiting to the state S00 via the state S00 obtained by the adding unit and the state S00 transiting to the state S00 via the state S01. The path metric of the path to be input is input, and as the first input value and the second input value in the second selecting unit, the state S11 is obtained via the state S11 obtained by the adding unit.
Since the path metric of the path that transits to 11 and the path metric of the path that transits to state S11 via state S10 are input, data that has been converted such that the minimum inversion interval is 2 channel bits or more is recorded. The path metric of the path transiting to the state S00 via the state S00 and the state S01 when the maximum likelihood decoding of the reproduced signal obtained by equalizing the reproduced signal from the recording medium to the PR (1,2,1) characteristic is performed. Via state S
If the path metric of the path transiting to 00 is equal, the path transiting to state S00 via state S00 is selected as the surviving path, while the path transiting to state S11 via state S11. Path metric and status S10
If the values of the path metrics of the paths transiting to the state S11 via the state S11 are equal, the state S11 is passed via the state S11.
The path that transits to can be selected as the surviving path.

Therefore, according to the present invention, the method of selecting the surviving path can be optimized to speed up the convergence of the path, and the data decoding section can decode the decoded data based on the selection result in the first and second selecting sections. The memory depth required for generation can be reduced.

Further, the data decoding unit in the Viterbi decoding circuit of the invention according to claim 7 generates the transition information of the surviving path at the time when the surviving path is selected by the transition information generating means, and makes the transition at each time point. When the transition information is stored in all the transition information storage means, the decoded data output means lastly stores the decoded information based on the transition information stored therein. Therefore, even if the transition pattern takes the longest time to converge the path, after storing all the transition information generated at each time until the path converges in the above transition information storage means, The decoded data can be output. Therefore, according to the present invention, it is possible to prevent the decoded data from being output before the path converges and eliminate the decoding error.

Further, the invention according to claim 8 is such that the path metric of the path transiting to the state S00 via the state S00 and the path metric of the path transiting to the state S00 via the state S01 are equal to each other. In the Viterbi decoding circuit that selects the path that transits to the state S00 via the state S01 as the surviving path, the transition information storage means of the data decoding unit is set to 12 or more. Even in the case of a transition pattern that takes a time, the decoded data can be output after storing all the transition information generated at each time point until the path converges in the respective transition information storage means. Therefore, according to the present invention, it is possible to prevent the decoded data from being output before the path converges and eliminate the decoding error.

The invention according to claim 9 is such that when the value of the path metric of the path transiting to the state S11 via the state S11 is equal to the value of the path metric of the path transiting to the state S11 via the state S10. In the Viterbi decoding circuit that selects the path that transits to the state S11 via the state S10 as the surviving path, the transition information storage means of the data decoding unit is set to 12 or more, so that it takes the longest time to converge the path. Even in the case of the transition pattern, the above-mentioned decoded data can be output after all the transition information generated at each time until the path converges is stored in each transition information storage means. Therefore, according to the present invention, it is possible to prevent the decoded data from being output before the path converges and eliminate the decoding error.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a Viterbi decoding circuit of the present invention.

FIG. 2 is a detailed block diagram of a data decoding unit in FIG.

FIG. 3 is a trellis diagram showing a transition pattern that requires the most time to converge a surviving path.

FIG. 4 is a trellis diagram showing a transition pattern that takes the longest time to converge a survivor path different from that in FIG.

FIG. 5 is an explanatory diagram of a trellis diagram of Viterbi decoding using the characteristic that the minimum inversion interval is 2 channel bits or more and the PR (1,2,1) characteristic.

FIG. 6 is an explanatory diagram of a method for determining a survivor path in Viterbi decoding.

[Explanation of symbols]

1 ... Branch metric calculation unit, 2 ... Addition unit, 3
… Comparison section, 4… Selection section, 5…
Holding unit, 6 ... data decoding unit,
7 ... Selector, 8 ... Register.

Claims (9)

[Claims] 1. A reproduction signal obtained by equalizing a reproduction signal from a recording medium on which data converted such that the minimum inversion interval is 2 channel bits or more is recorded, into a PR (1,2,1) characteristic. Is a Viterbi decoding circuit for maximum likelihood decoding, in which the path metric value of the path transiting to state S00 via state S00 and the path metric value of the path transiting to state S00 via state S01 are equal. In this case, the path that transits to state S00 via state S00 is selected as the surviving path, while the path metric value of the path transiting to state S11 via state S11 and the state via state S10. A Viterbi decoding circuit, characterized in that, when the value of the path metric of a path transiting to S11 is equal, a path transiting to state S11 via said state S11 is selected as a surviving path. 2. A reproduction signal obtained by equalizing a reproduction signal from a recording medium on which data converted such that the minimum inversion interval is 2 channel bits or more is recorded, into a PR (1,2,1) characteristic. Is a Viterbi decoding circuit for maximum likelihood decoding, in which a branch metric calculator calculates a branch metric based on input data, and an adder adds the calculated branch metric to a path metric of a surviving path to calculate The path metric of the surviving path at the next point in time is obtained, and the path metric of the path transiting to the state S00 via the state S00 and the state S00 via the state S01 by the selection unit.
If the path metric of the path transiting to the state is equal to the path metric of the path transiting to the state S00, the path transiting to the state S00 via the state S00 is selected as the surviving path, while the path transiting to the state S11 via the state S11 is selected. When the path metric and the value of the path metric of the path transiting to the state S11 via the state S10 are equal, the path transiting to the state S11 via the state S11 is selected as the surviving path. Viterbi decoding circuit. 3. The Viterbi decoding circuit according to claim 2, wherein when the surviving path is selected by the selecting unit, transition information of the surviving path is generated, and the transition at each of the generated time points is generated. A Viterbi decoding circuit having 10 or more transition information storage units for storing respective pieces of information. 4. The path metric of the path which transits to the state S00 via the state S00 and the path metric of the path which transits to the state S00 via the state S00 in the selection unit in the Viterbi decoding circuit according to claim 3. And the values are equal,
A Viterbi decoding circuit configured to select a path that transits to state S00 via state S01 as a surviving path, characterized by comprising 12 or more of the transition information storage means. 5. The path metric of the path which transits to the state S11 via the state S11 and the path metric of the path which transits to the state S11 via the state S10 in the selection unit in the Viterbi decoding circuit according to claim 3. And the values are equal,
A Viterbi decoding circuit adapted to select a path that transits to the state S11 via the state S10 as a surviving path, characterized in that it has 12 or more transition information storage means. 6. A reproduction signal obtained by equalizing a reproduction signal from a recording medium on which data converted such that the minimum inversion interval becomes 2 channel bits or more is recorded, into a PR (1,2,1) characteristic. Is a Viterbi decoding circuit for performing maximum likelihood decoding of a branch metric calculation unit that calculates a branch metric of each branch based on input data, a path metric of a surviving path, and a branch metric calculated by the branch metric calculation unit. An addition unit for adding the path metric at the next time of the surviving path and a path metric obtained by the addition unit for the path transiting to the state S00 via the state S00 are used as the first input value, With the path metric obtained by the adder of the path transiting to the state S00 via the state S01 as the second input value, both input values are When the input values are different, the larger one of the input values is output, and when the both input values are the same, the first selection unit which selects and outputs the first input value, and the state S11 via the state S11. The first input value is the path metric obtained by the addition unit of the path that transits to S1, and the second input value is the path metric obtained by the addition unit of the path that transits to state S11 via state S10. When the two input values are different from each other, the larger one of the input values is output, and when the two input values are the same, the second selection unit which selects and outputs the first input value, The path metric output from the first and second selection units and the path metric of the path transiting to the state S10 via the state S00 obtained by the addition unit and the state S01 transiting to the state S01 via the state S11. Path metric for path A holding unit that holds the path metric as a path metric of the surviving path at the next point in time, and a data decoding unit that generates decoded data based on the selection results of the first and second selecting units are provided. Viterbi decoding circuit. 7. The Viterbi decoding circuit according to claim 6, wherein the data decoding unit selects first and second transition information of the surviving path when the surviving path is selected by the selecting unit. Transition information generating means that is generated based on the selection result by the section, 10 or more transition information storing means that stores each of the transition information at each time point generated by the transition information generating means, and all the transitions A Viterbi decoding circuit comprising: decoded data output means for outputting decoded data based on the transition information stored at the end when the transition information is stored in the information storage means. 8. The Viterbi decoding circuit according to claim 7, wherein the contents of the first input value and the contents of the second input value in the first selection unit of the Viterbi decoding circuit are reversed. Is a Viterbi decoding circuit having 12 or more of the transition information storage means. 9. The Viterbi decoding circuit according to claim 7, wherein the contents of the first input value and the contents of the second input value in the second selecting unit of the Viterbi decoding circuit are reversed. Is a Viterbi decoding circuit having 12 or more of the transition information storage means.