JPH06282601A - Logical simulator - Google Patents

Abstract

PURPOSE:To quickly execute a processing for setting data at the pertinent position of a basic logical element handled by the respective processors inside a parallel logical simulator based on the data corresponding to logic circuit components prepared in the pre-processing of an instruction level simulator. CONSTITUTION:When the data prepared in the pre-processing of the instruction level simulator 1 are transferred to the parallel logical simulator 2, a data transfer means 31 refers to information in a first storage means 32, divides the data and transfers them to the processors (4-1) to (4-n). The data setting means 42 of the respective processors discriminates which received data are to be set at which position of which basic logical element relating to the execution of simulation by referring to the information of a second storage means 41 for the received data and sets the data at the pertinent position of the pertinent basic logical element in a simulation execution part 43.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation device, and more particularly to an instruction level simulator which is a software simulator for performing pre-processing and post-processing of simulation, a plurality of processing processors for performing main processing of simulation, and control of these processing processors. The present invention relates to an improvement of a logic simulation device composed of a parallel logic simulator that is a hardware simulator including a control processor that controls data transfer between instruction level simulators.

[0002]

2. Description of the Related Art Generally, processing by a machine language instruction program for simulating one function of a logic circuit is classified as follows.

Processing by an instruction that moves a function that sets a value immediately before test execution in a simulation model Processing by an instruction that moves a function that performs test execution Processing by an instruction that moves a function for determining a simulation result

The above process is called a pre-process for simulation, the process is called a main process, and the process is called a post-process.

In this process of, since the movement of the actual device is simulated, it is necessary to calculate the change in the value at the gate level. However, the pre-processing and post-processing of the simulation are operated by machine language instructions. It suffices to be able to calculate at the level of possible logic circuit constituent elements, and if the calculation is done at the gate level, the amount of calculation becomes enormous.

Therefore, 1) A software simulator (instruction level simulator) described at the assembler level, which has as a calculation unit a logical circuit component operable by a machine language instruction, such as a register or a memory constituting a logic circuit to be simulated. 2) All output signal values are given by using a basic logic element such as a flip-flop, an AND gate, and an OR gate (this basic logic element serves as an element forming the above-mentioned logic circuit constituent element) as a calculation unit, and each machine Using two kinds of simulators, a hardware simulator capable of performing a device-level logic simulation, which calculates a value that changes by the execution of a word instruction,
By using a hardware simulator for this main processing, the hardware simulator is applied to different basic logic elements so that the basic logic elements whose operations are independent of each other in synchronization in the simulation model can be processed in parallel. By implementing with a parallel logic simulator composed of multiple processing processors that execute simulations and control processors that control these,
A logic simulation device that realizes high-speed simulation has been proposed.

By the way, in the logic simulation apparatus of this type, at the end of the processing of (1), the instruction level simulator holds the value in the unit of the logic circuit component processable by the machine language instruction, whereas the parallel logic simulator. Each processing processor therein needs to hold its value at the basic logic element level in order to perform the simulation at the basic logic element level. Further, although the value obtained at the basic logic element level is obtained by the simulation of each processing processor, it is necessary to hold the simulation result in units of logic circuit components at the start of processing in the instruction level simulator.

Therefore, in the conventional logic simulation apparatus, the control processor in the parallel logic simulator divides the data in units of logic circuit elements sent from the instruction level simulator into individual processing processors and divides them. Which basic logic element in the simulation model the data should be set to is determined, and after conversion (division) of the data if necessary, which basic logic element should be set Is added to the processing processor. In addition, the data corresponding to the basic logic element sent from each processor is edited and arranged in units of logic circuit components that can be handled by the instruction level simulator, and these are combined to form one logic circuit component unit. Data is generated and transferred to the instruction level simulator.

[0009]

However, in this way, the control processor in the parallel logic simulator divides the data in units of logic circuit elements sent from the instruction level simulator into individual processors,
Further, it is determined which basic logic element in the simulation model each divided data should be set to, and if necessary, data conversion (division) is performed before setting to which basic logic element. In the configuration in which information on whether or not it should be added is transferred to the processor, since the processing proceeds sequentially,
The amount of data that can be processed within a fixed time is limited, the data setting to the basic logic element handled by the processor is delayed, and high-speed simulation becomes difficult.

Further, the control processor edits the data corresponding to the basic logic elements sent from the individual processing processors in the data of the logic circuit component unit which can be handled by the instruction level simulator, and edits them to combine them into one. In the configuration in which data for each logic circuit component unit is generated and transferred to the instruction level simulator, it takes time until the data for each logic circuit component unit is generated based on the simulation result, and the post-processing of the simulation is promptly performed. The simulation time is long as a whole.

The present invention solves such a conventional problem, and an object of the present invention is to solve each of the problems of the parallel logic simulator when the data for each logic circuit component is created in the preprocessing of the instruction level simulator. The purpose is to promptly set the corresponding data to the basic logic element handled by the processor.

Another object of the present invention is to be able to promptly create data for each logic circuit component handled by the instruction level simulator from the simulation result at the end of the simulation of each processing processor.

[0013]

In order to achieve the above object, a logic simulation apparatus of the present invention has an instruction level simulator for performing pre-processing and post-processing of simulation, a plurality of processing processors for performing main processing of simulation, and the plurality of processing processors. In a logic simulation device configured with a parallel logic simulator including a control of a processing processor and a control processor for controlling data transfer between the instruction level simulators, a machine language instruction handled by the instruction level simulator in the control processor Based on the correspondence information stored in the first storage means, which stores correspondence information indicating which range of the data corresponding to the logic circuit constituent element that can be processed by , The logic circuit sent from the instruction level simulator The data corresponding to the component is divided and transferred to the processing processor, and the data sent from the processing processor is edited into the data corresponding to the logic circuit component handled by the instruction level simulator, and the data is converted to the instruction level simulator. Data transfer means for transferring, and storing in each of the processing processors corresponding information indicating which bit of the data sent from the control processor should be set in which position of which basic logic element. Based on the second storage means and the correspondence information stored in the second storage means, the data sent from the control processor is set to the corresponding position of the basic logic element when the self-processing processor performs the logic simulation. Along with the obtained data, a simulation is executed by a self-processor to obtain the data. It was by editing the data of the basic logic elements and a data setting means for sending to the control processor.

[0014]

In the logic simulation apparatus of the present invention, when performing simulation for one function of the simulation model, the instruction level simulator first performs preprocessing, and the machine language instruction prepared by this preprocessing can be used for processing. Data in units of logic circuit components can be transferred to the control processor of the parallel logic simulator, and the data transfer means in the control processor can be processed by machine language instructions stored in the first storage means and handled by the instruction level simulator. Based on correspondence information indicating which range of data corresponding to different logic circuit components corresponds to which processing processor, the transferred data is divided and transferred to the processing processors, and data setting means in each processing processor But,
Based on the correspondence information stored in the second storage means, which bit of the data sent from the control processor should be set in which position of which basic logic element, the transferred data is automatically stored. It is set to the corresponding position of the basic logic element in the logic simulation by the processor.

Further, the data setting means in each processing processor sets the data obtained by performing the simulation in each processing processor based on the set data.
The processor is edited based on the correspondence information stored in the second storage means and sent to the control processor, and the data transfer means in the control processor is based on the correspondence information stored in the first storage means. The data sent from the computer is edited and transferred to the instruction level simulator, and the instruction level simulator performs post-processing of the simulation based on the transferred data.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, a logic simulation apparatus according to an embodiment of the present invention comprises an instruction level simulator 1
And a parallel logic simulator 2.

The instruction level simulator 1 is a software simulator for executing pre-processing and post-processing of a simulation, and a logical circuit component operable by a machine language instruction such as a register and a memory constituting a logical circuit to be simulated is used as a calculation unit. Perform a simulation.

The parallel logic simulator 2 is a hardware simulator for executing the main processing of the simulation, and includes physical level basic logic elements such as flip-flops, AND gates, OR gates and registers, which constitute the above-mentioned logic circuit constituent elements. Simulation is performed as a unit of calculation.

The parallel logic simulator 2 includes a control processor 3 and a plurality of processing processors 4-1 to 4-n,
It has a configuration capable of exchanging data between processors.

The control processor 3 controls data transfer between the instruction level simulator 1 and the parallel logic simulator 2 and controls the start and end of simulation of each of the processing processors 4-1 to 4-n.

The control processor 3 handles the data handled by the instruction level simulator 1 and the processing processors 4-1 to 4-.
First storage means 3 for storing correspondence information of data handled by n
2 and the correspondence information stored in the first storage means 32, the data sent from the instruction level simulator 1 is divided and transferred to each of the processing processors 4-1 to 4-n, and vice versa. The data transfer means 31 is provided to combine the data sent from the processing processors 4-1 to 4-n and transfer the data to the instruction level simulator 1.

The processing processors 4-1 to 4-n are processors for simulating in parallel the portions of the simulation model whose operations are independent of each other in synchronization. Each of the processing processors 4-1 to 4-n is a processor. , The control processor 3 as illustrated in the processor 4-1.
Second storage means 41 for storing correspondence information indicating which bit of the data sent from is set in which position of which basic logic element, and this second storage means 41.
The data sent from the control processor 3 is set to the corresponding position of the basic logic element when the logic simulation is performed by the self-processor based on the correspondence information stored in the. The data setting means 42 for editing the data of the basic logic element obtained by the simulation by the processing processor and sending it to the control processor 3 and the simulation execution part 43 for executing the simulation by the data set by the data setting means 42. Contains.

The operation of the present embodiment thus constructed will be described below.

When the logic simulation is performed on the simulation model, the pre-processing of the simulation, the main processing of the simulation, and the post-processing of the simulation are performed for each function to be verified of the logic circuit. The pre-processing and post-processing of the simulation are performed by the instruction level simulator 1, and the main processing of the simulation is performed by the parallel logic simulator 2.

In the instruction level simulator 1, in the pre-processing of the simulation, the instruction level simulator 1 executes the instruction to operate the function of setting the value immediately before the test execution in the simulation model. The data created by this pre-processing is data corresponding to the logic circuit components that can be processed by the machine language instruction. Now, assume that the name of a certain logic circuit component is AAA, and the data related to it (for example, 1 word, 16-bit 00
1101101000001) is created by preprocessing, the instruction level simulator 1 transfers the data set to the parallel logic simulator 2 in the format of AAA = 001101110100001, for example.

The transferred data is the data transfer means 31 in the control processor 3 of the parallel logic simulator 2.
Will be received at. When the data transfer unit 31 receives the data from the instruction level simulator 1, the data transfer unit 31 searches the first storage unit 32 for the element name AAA added to the data, and the element name A
Corresponding information about AA data is acquired. Now, for example, it is assumed that the following correspondence information is acquired.

AAA (0: 1, 0:16) = (REG,
0,0-3, PROC1) (REG, 0, 4-7, PROC2) (REG, 0, 8-15, PROC1) This correspondence information is for the logic circuit component of the element name AAA,
It is an element related to a register having a 1-word structure starting from the 0th word, and 1 word is composed of 16 bits starting from the 0th bit. 0th to 3rd bits of the 0th word of the logic circuit constituent element of this element name AAA. And 8 to 15 bits correspond to the processor named PROC1,
It is shown that 4 to 7 bits correspond to a processor named PROC2. For convenience of explanation, it is assumed that the name of the processing processor 4-1 is PROC1 and the name of the processing processor 4-2 is PROC2.

The data transfer means 31 receives the element name A
When the above-mentioned information is acquired as the correspondence information regarding the AA data, the data is 0011 according to the correspondence information.
And 0110 and 10010001, divided into the first and third
The second divided data is edited according to a predetermined format, and is transferred to the processor 4-1 in the format of AAA = 001110010001, and the second divided data is processed in the format of AAA = 0110, for example. Transfer to 2.

The transferred data are received by the data setting means 42 of the processing processors 4-1 and 4-2 at the transfer destination.

When the data setting means 42 in the processor 4-1 receives the data from the control processor 3, the data setting means 42 searches the second storage means 41 by the element name AAA added to the data, and makes a correspondence regarding the data of the element name AAA. Get information. Now, for example, it is assumed that the following correspondence information is acquired.

AAA (0: 3) = (REG1,0: 1,0: 3) AAA (3: 1) = (REG2,0: 1,0: 1) AAA (4: 8) = (REG2,0) : 1,1: 8) This correspondence information indicates that 3-bit data starting from the 0th bit of the element name AAA starts from the 0th bit of the basic logic element named REG1 of 1-word configuration starting from the 0th word. Being set to a bit, the 1-bit data starting from the 3rd bit of the element name AAA is set to the 1-bit starting from the 0th bit of the basic logic element named REG2 having the 1-word configuration starting from the 0th word. That is, it is indicated that 8-bit data starting from the 4th bit of the element name AAA is set to 8 bits starting from the 1st bit of the basic logic element REG2.

The data setting means 42 receives the received element name A
When the above information is acquired as the correspondence information regarding the AA data, the element name AAA received according to the information.
Data (001110010001) is divided into 001, 1 and 10010001, and each divided data is divided into corresponding basic logic elements RE in the simulation execution unit 43.
Set it to the corresponding position of G1 and REG2. This allows the simulation executing unit 43 to perform a simulation.

On the other hand, the data setting means in the processor 4-2 also receives the received data by referring to the corresponding information in the second storage means at the same time as the data setting means 42 of the processor 4-1. Each bit of is set to the corresponding position of the internal simulation execution unit.

After that, each processor 4-1 to 4-n
The simulation is performed by the simulation execution unit 43 inside.

Now, assuming that the simulation is completed in the simulation executing section 43 of the processor 4-1 the data setting means 42 is operated in the simulation executing section 43.
From the simulation result corresponding to the basic logic element, the data of the basic logic element is edited into the data to be sent to the control processor 3 by referring to the correspondence information of the second storage means 41, and the data is transferred to the data transfer means 31 of the control processor 3. Forward.

That is, the data of the element name AAA (00111
Each bit of 0001001) is the element name R as described above.
Assuming that the value of the basic logic element REG1 has changed to 000 and the value of the basic logic element REG2 has changed to 011111111 as a result of setting the corresponding bit of the basic logic elements of EG1 and REG2 to the simulation execution section 43, The data setting means 42 uses the correspondence information AAA (0: 3) = (REG1,0: 1,0: 3) AAA (3: 1) = (REG2) in the second storage means 41 corresponding to the element name AAA. 0: 1, 0: 1) Based on AAA (4: 8) = (REG2,0: 1,1: 8), each bit of the basic logic elements REG1 and REG2 is sent from the control processor 3. The element name AAA is edited and transferred to the data transfer means 31 in the format AAA = 000011111111, for example.

In parallel with the operation of the processor 4-1 as described above, also in the other processors 4-2 to 4-n, the data corresponding to the basic logic element obtained as a result of the simulation is set in the internal data setting means. Is edited and transferred to the control processor 3.

Now, when the simulation in each of the processors 4-1 to 4-n is completed and all the resulting data is transferred to the data transfer means 31, the data transfer means 3
The reference numeral 1 refers to the correspondence information stored in the first storage means 32 to edit the data sent from each of the processing processors 4-1 to 4-n into the data handled by the instruction level simulator 1, and this editing Command level simulator 1
Transfer to.

For example, as described above, the simulation is completed based on the divided data obtained by dividing the data of the element name AAA (0011011101001000) and transferred to the processing processors 4-1 and 4-2.
1, the data AAA = 000011111111 is transferred, and from the processor 4-2,
For example, when the data AAA = 1110 is transferred, the data transfer means 3
1 is correspondence information corresponding to the element name AAA, AAA (0: 1, 0:16) = (REG, 0, 0-3,
PROC1) Based on (REG, 0,4 to 7, PROC2) (REG, 0,8 to 15, PROC1), the data of AAA = 0000111011111111111 is edited and transferred to the instruction level simulator 1.

The instruction level simulator 1 executes post-processing of the simulation by executing an instruction for operating the function of judging the result of the simulator based on the transferred data.

[0042]

As described above, in the logic simulation apparatus of the present invention, when the data in the unit of logic circuit created in the preprocessing of the instruction level simulator is transferred to the control processor of the parallel logic simulator,
The data transfer means in the control processor divides the transferred data on the basis of the correspondence information stored in the first storage means and transfers the divided data to the processing processors. Based on the correspondence information stored in the second storage means, the transferred data is set at the corresponding position of the basic logic element in the logic simulation by the self-processing processor, so that the logic circuit configuration created in the pre-processing is set. There is an effect that a data set to a corresponding position of a basic logic element handled by each processor can be promptly executed based on element-corresponding data.

Further, the data setting means in each processor sets the data obtained by performing the simulation in each processor based on the set data by the second data processor.
Edited based on the correspondence information stored in the storage means and sent to the control processor, and the data transfer means in the control processor sends the data from each processing processor based on the correspondence information stored in the first storage means. Since the received data is edited and transferred to the instruction level simulator, there is an effect that at the end of the simulation of each processing processor, the data for each logic circuit component handled by the instruction level simulator can be quickly created from the simulation result. .

Therefore, there is an effect that the efficiency of logic verification is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a logic simulation apparatus of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Instruction level simulator 2 ... Parallel logic simulator 3 ... Control processor 31 ... Data transfer means 32 ... First storage means 4-1 to 4-n ... Processing processor 41 ... Second storage means 42 ... Data setting means 43 ... Simulation execution unit

Claims (2)

[Claims] 1. An instruction level simulator that performs pre-processing and post-processing of simulation, a plurality of processing processors that perform main processing of simulation, and a control processor that controls the plurality of processing processors and controls data transfer between the instruction level simulators. In a logic simulation device configured with a parallel logic simulator including, in the control processor, which range of data corresponding to a logic circuit component which can be processed by a machine language instruction and which is handled by the instruction level simulator corresponds to which processing processor. First storage means for storing correspondence information indicating whether or not to perform processing, and dividing the logic circuit component correspondence data sent from the instruction level simulator based on the correspondence information stored in the first storage means. And a data transfer means for transferring to the processor. Second storage means for storing in each of the processing processors correspondence information indicating which bit of the data sent from the control processor should be set at which position of which basic logic element; Data setting means for setting the data sent from the control processor to the corresponding position of the basic logic element when performing logic simulation of the data sent from the control processor based on the correspondence information stored in the second storage means. A logic simulation device characterized by. 2. An instruction level simulator that performs pre-processing and post-processing of simulation, a plurality of processing processors that perform main processing of simulation, and a control processor that controls the plurality of processing processors and controls data transfer between the instruction level simulators. In a logic simulation device configured with a parallel logic simulator including, in the control processor, which range of data corresponding to a logic circuit component which can be processed by a machine language instruction and which is handled by the instruction level simulator corresponds to which processing processor. First storage means for storing correspondence information indicating whether or not to perform processing, and dividing the logic circuit component correspondence data sent from the instruction level simulator based on the correspondence information stored in the first storage means. And transfer it to the processing processor, and Data transfer means for editing the data sent from the processor into data corresponding to the logic circuit components handled by the instruction level simulator and transferring the data to the instruction level simulator, wherein each of the processing processors has the control processor The correspondence information stored in the second storage means for storing correspondence information indicating which bit of the data sent from the device should be set at which position of which basic logic element; and the correspondence information stored in the second storage means. Based on the set data, the data sent from the control processor is set to the corresponding position of the basic logic element when the self-processing processor performs logic simulation, and the self-processing processor executes the simulation based on the set data. A data setting procedure for editing the data of the basic logic element and sending it to the control processor. Logic simulation apparatus comprising: a and.