JPH06275644A - Thin film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a TFT of positive stagger structure wherein the OFF- current between a source and a drain is restrained, and the manufacturing method wherein the TFT is formed without inreasing the number of masks. CONSTITUTION:Insulating films 106 are formed on side surfaces of both steps of a source wiring 102 and/or a drain electrode 104, and contact layers 105 are formed on the upper surfaces of both electrodes 103 and 104. As a result, the source electrode 103 and/or the drain electrode 104 do not come into contact with a semiconductor layer 107 which is formed so as to cover the electrodes. The insulating films 106 are formed by oxidizing both of the electrodes 103 and 104, in the state that masks formed on the contact layers 105 are left in order to form the source electrode 103 and the drain electrode 104, so that the insulating films 106 are not formed on the surfaces of the contact layers 105. Hence the contact layers 105 is in contact with the semiconductor layer 107. Superflous masks for forming the insulating films 106 are unnecessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter abbreviated as TFT) used as a switching element in an active matrix substrate for a liquid crystal display device, for example.

[0002]

2. Description of the Related Art In recent years, application of liquid crystal display devices to word processors, laptop personal computers, pocket televisions, etc. has been rapidly expanding. In particular, among the liquid crystal display devices, an active matrix liquid crystal display device in which a TFT is provided as a switching element in each pixel has advantages such as high display contrast and no restriction on display capacity. It is being appreciated.

FIG. 9 shows a picture element portion of an active matrix substrate which constitutes this active matrix type liquid crystal display device. FIG. 9A shows the plan configuration, and FIG.
Shows a cross section taken along line AA ′ in (a).

A plurality of gate wirings 902a, 902a, ... And source wirings 907a, 907 are formed on an insulating substrate 901.
are formed vertically and horizontally, and each gate wiring 902a is formed.
A gate electrode 902b is branched from the gate wiring 902a in the direction orthogonal to the gate wiring 902a in the vicinity of the intersection with the source wiring 907a. Further, a TFT 920 is formed above the gate electrode 902b so as to intersect with the gate electrode 902b. At the formation position of the TFT 920, the source electrode 907 is connected to the source wiring 907a.
b branches in a direction orthogonal to the source wiring 907a and constitutes a part of the TFT 920.

Two adjacent source wirings 907a and 907 are provided.
Two gate wirings 902a and 902 adjacent to each other
In each of the regions surrounded by a, the TFT 9 in this region is
20. The pixel electrode 9 is formed by substantially filling the area excluding the formation portion.
09 are formed.

TF is provided on the side of the pixel electrode 909 of the TFT 920.
One end of the drain electrode 908 overlaps with T920. The protruding portion of the picture element electrode 909 is superposed on the end of the drain electrode 908 opposite to the one where the TFT 920 is superposed, and the picture element electrode 909 is interposed via the drain electrode 908.
And the TFT 920 are electrically connected.

FIG. 9B shows a sectional structure of the TFT 920. A gate electrode 902b is formed on the base substrate 901. A gate insulating film 903 is formed on the entire surface of the base substrate 901 so as to cover the gate electrode 902b. A portion of the gate insulating film 903, which covers the gate electrode 902b, projects upward.

A semiconductor layer 904 is patterned on the gate insulating film 903 so as to be in contact therewith and intersect the gate electrode 902b. The semiconductor layer 904 is the TFT 92
It is a semiconductor layer of 0.

A channel protective film 905 is formed in the center of the semiconductor layer 904 so as to be in contact therewith. The channel protective film 905 extends long in the extending direction of the gate electrode 902b. Contact layers 906 and 906 are provided on both sides of the semiconductor layer 904 which are partitioned by the channel protection film 905.
Are formed.

Since this TFT 920 has an inverted staggered structure, the presence of impurities at the interface is extremely small in the manufacturing process, so the switching performance is stable, but the manufacturing process is complicated and the manufacturing cost is high, and the TFT is used. The active matrix type liquid crystal display device is expensive.

On the other hand, since the TFT having the positive stagger structure has a structure in which the manufacturing process is simpler than that of the TFT having the inverted stagger structure, the TFT having the positive stagger structure is used. , It has been proposed to manufacture a TFT active matrix substrate with good yield and at low cost. (M. BONNEL et al., JAPAN
DISPLAY '86, p. 332, 1986).

FIG. 10 shows a TFT installation portion of an active matrix substrate provided with a TFT 1020 having a positive stagger structure. FIG. 10A shows the plan configuration.

The source wiring 100 is formed on the base substrate 1001.
2 and the gate wiring 1008 are formed orthogonally to each other,
A pixel electrode 1009 is formed on the same surface as the source wiring 1002. From this source wiring 1002, the TFT
The source wiring 1002 is formed near the formation portion 1020.
The source electrode 1003 is branched in a direction orthogonal to
The source electrode 1003 is orthogonal to the branching direction at a position slightly branched from the source wiring 1002, and the pixel electrode 100
9 is further branched and extended in the direction toward 9 to form the pixel electrode 100.
It ends before 9. That is, the source electrode 1
The end portion of 003 runs in a direction parallel to the original source wiring 1002. A drain electrode 1004 protruding from a pixel electrode 1009 extends in a direction parallel to the end portion of the source electrode 1003 and the source wiring 1002, and is orthogonal to the source wiring 1002 from the source wiring 1002. It terminates before the running branch.

FIG. 10B shows a line AA 'in FIG. 10A.
And a cross-sectional structure taken along line BB ′.

The source wiring 100 is formed on the base substrate 1001.
2 and the drain electrode 1004 are formed at a predetermined interval. Source wiring 1002 and drain electrode 1004
A contact layer 1005 is formed on the upper surface of each of the contact layers 1005 so as to have the same surface shape. This source wiring 10
02 and a drain electrode 1004 in a direction orthogonal to each other and a semiconductor layer 1006 having a predetermined width and intersecting these. A gate insulating film 1007 and a gate electrode 1008 are laminated in this order on the upper surface of the semiconductor layer 1006 so as to have a uniform surface shape.

A TFT 1020 having such a positive stagger structure
Is produced as follows.

After depositing a metal such as tantalum (Ta) on an insulating base substrate 1001 such as glass by a sputtering method, a contact layer is continuously deposited by using, for example, phosphorus-doped amorphous silicon and patterned. Then, the source wiring 1002, the source electrode 1003, and the drain electrode 1004 are formed.

The source wiring 1002 and the source electrode 10
03, covering the drain electrode 1004, the base substrate 10
The semiconductor layer 1006, the gate insulating film 1007, and the metal film for the gate electrode 1008 are laminated in this order over the entire surface 01.

Next, the semiconductor layer 1006 and the gate insulating film 1 having a predetermined width in the direction orthogonal to the source line 1002 at a position intersecting all of the source line 1002, the drain electrode 1004, and the terminal end of the source electrode 1003.
007 and the gate electrode 1008 are patterned.

In the active matrix substrate having such a structure and the TFT 1020 formed thereon, the drain electrode 1004 is affected by the signal inputted to the adjacent source wiring 1002, so that the display quality is deteriorated. There is a problem. Therefore, the drain electrode 1
A source electrode 1003 is provided between 004 and the nearest source wiring 1002 so as not to be influenced by a signal input to the source wiring 1002.

[0021]

However, in the active matrix substrate using the TFT element having the positive stagger structure as described above, since the conductive film to be the source wiring and the semiconductor layer are directly in contact with each other, the negative electrode is not applied to the gate. The current flowing between the source and the drain is large even when the voltage is applied. for that reason,
When such a TFT and a substrate provided with this TFT are used in a liquid crystal display device, the charge of the pixel electrode cannot be held, so that there is a problem that the display quality is deteriorated.

In order to deal with this, there is a method of laminating an insulating film on a substrate and forming the insulating film on both sides of the gate electrode by a photolithography process. However, this method increases the number of masks in the manufacturing process. There is a problem that the advantage of the simple fabrication process of the TFT having the positive stagger structure is lost.

The present invention has been made to solve the above-mentioned problems of the prior art, and has a positive stagger structure having a structure in which the number of masks is not increased and the source and drain electrodes and the gate electrode are not in contact with each other. It is an object to provide a TFT and a manufacturing method thereof.

[0024]

A thin film transistor according to the present invention comprises a source electrode and a drain electrode, and contact layers having the same shape on the upper surface of the source electrode and the drain electrode, respectively, on the same surface of an insulating substrate. And an insulating film on both side surfaces of the source electrode and / or the drain electrode and the contact layer.
A thin film transistor having a semiconductor layer, a gate insulating film, and a gate wiring in this order and in the same shape on the upper surface of the contact layer in a direction orthogonal to the source electrode and the drain electrode, thereby achieving the above object. To be done.

Preferably, the insulating film is an oxide film.

Further, the method of manufacturing a thin film transistor of the present invention comprises a step of successively laminating a conductive film and a thin film for a contact layer on the entire surface of an insulating substrate in this order, and a source on the upper surface of the thin film for a contact layer. A step of forming a mask for forming an electrode and a drain electrode, and a step of etching the conductive film and a thin film for a contact layer together to form a source electrode and a drain electrode in which a contact layer is formed in the same shape on the upper surface. A step of oxidizing the source electrode and / or the drain electrode and the contact layer while leaving the mask to form an insulating film on each side surface of both steps; a step of removing the mask; A semiconductor layer, a thin film for a gate insulating film, and a conductive film for a gate wiring are provided on the upper surface of the layer in a direction orthogonal to the source electrode and the drain electrode. In the order of, and a manufacturing method of a thin film transistor comprising the laminating formed in the same width, the objects can be achieved.

[0027]

According to the above structure, the TFT of the present invention has the insulating film formed on both side surfaces of the step of the source electrode and / or the drain electrode, and the contact layer formed on the upper surface of both electrodes. Therefore, the source electrode and / or the drain electrode are not in contact with the semiconductor layer formed so as to cover them. Since this insulating film is formed by oxidizing both electrodes while leaving the mask formed on the contact layer for forming the source electrode and the drain electrode, the insulating film is not formed on the surface of the contact layer. Therefore, the contact layer and the semiconductor layer are in contact with each other. In addition, no extra mask is required for forming the insulating film.

[0028]

【Example】

(Embodiment 1) FIG. 1 shows a TFT forming portion according to Embodiment 1 of the present invention. FIG. 1A shows the plan configuration.

The TFT 120 of the first embodiment is shown in FIG.
As shown in FIG. 3, the gate line 110 is provided in the vicinity of the intersection of the source line 102 and the gate line 110 which are vertically and horizontally formed on the insulating base substrate 101.

A source wiring 102 and a gate wiring 108 are formed orthogonally on the base substrate 101, and a pixel electrode 111 is formed on the same surface as the source wiring 102. A source electrode 103 is branched from the source wiring 102 in the direction orthogonal to the source wiring 102 in the vicinity of the TFT 120 formation portion.
3 is a position slightly branched from the source wiring 102, and is branched again in a direction orthogonal to this branch direction and in a direction toward the pixel electrode 111, and terminates before reaching the pixel electrode 111. That is, the end portion of the source electrode 103 runs in a direction parallel to the original source wiring 102. A drain electrode 104 protruding from the pixel electrode 111 extends in a direction parallel to the end portion of the source electrode 103 and the source wiring 102, and runs orthogonal to the source wiring 102 of the source electrode 103. It terminates before the branch.

FIG. 1B shows a sectional structure taken along the line AA ′ in FIG. Further, FIG. 1C shows a cross-sectional structure taken along line BB ′ of FIG.

The source wiring 102 and the drain electrode 104 are formed on the base substrate 101 with a predetermined space. The contact layer 10 is formed on the upper surfaces of the source wiring 102 and the drain electrode 104 so as to have the same surface shape as those of the contact layer
5 is formed. In the direction orthogonal to the source wiring 102 and the drain electrode 104, a semiconductor layer 107 is formed with a predetermined width so as to intersect and overlap these. The gate insulating film 1 having a uniform surface shape on the upper surface of the semiconductor layer 107
08 and the gate electrode 109 are laminated in this order.

The TFT 120 having such a positive stagger structure is manufactured as follows. The schematic manufacturing process is shown in FIG.

First, an insulating base substrate 10 made of glass or the like.
1 on top of 1 by sputtering tantalum (Ta)
Deposit to a thickness of 0 nm. The tantalum film serves as a material for the source wiring 102, the source electrode 103, and the drain electrode 104, and other materials such as N may be used.
A single-layer film or a multi-layer film of a metal such as b, A1, or Mo may be used.

Then, on this tantalum film, P-CV
Amorphous silicon doped with phosphorus by D method 1
Deposition is continued with a thickness of 00 nm. Although this amorphous silicon film doped with phosphorus serves as the contact layer 105, amorphous silicon doped with a group III element or a group V element other than phosphorus may be used.

Next, a photosensitive insulating resin film 109 is deposited on this amorphous silicon film to form a pattern for the source wiring 102, the source electrode 103 and the drain electrode 104.

Subsequently, with the pattern of the photosensitive insulating resin film 109, a two-layer film of tantalum and amorphous silicon successively deposited is simultaneously patterned by etching to form the source wiring 102, the source electrode 103, and the drain electrode 104. Further, the contact layer 105 having the same shape is formed on these layers. The resulting state is shown in FIG.

Next, thermal oxidation is performed while leaving the photosensitive insulating resin film 109 remaining on the contact layer 105,
Source wiring 102, source electrode 103, drain electrode 1
04 and the contact layer 105, oxide films 106 and 106 are formed on both side portions of the step. The resulting state is shown in FIG.

After forming the oxide film 106, the contact layer 10 is formed.
The photosensitive insulating resin film 109 on 5 is removed. The resulting state is shown in FIG.

Next, amorphous silicon to be the semiconductor layer 107 is deposited over the entire surface of the substrate 101 by P-CVD so as to cover all of the wiring, electrodes and contact layer 105 described above. Alternatively, silicon or polysilicon in a microcrystalline state may be used as the material of the semiconductor layer 107.

Subsequently, silicon nitride to be the gate insulating film 108 is deposited to a thickness of 300 nm on the semiconductor layer 107 by the P-CVD method, and an A1 film is further deposited to a thickness of 200 nm by the sputtering method.

After these thin films are continuously deposited, only the uppermost A1 film is patterned to form the gate wiring 110. The resulting state is shown in FIG.

Finally, the gate insulating film 108, the semiconductor layer 107 and the contact layer 105, which are the lower layers, are continuously etched using the gate wiring 110 as a mask,
It is formed in the same shape as the gate wiring 110. Through the above manufacturing process, an active matrix substrate including a TFT having a positive stagger structure as a switching element is obtained. The resulting state is shown in FIG.

According to such an embodiment, since the insulation between the source and the drain in the TFT can be improved, the OF
The F current can be reduced.

In the first embodiment, the source wiring 1
02, the source electrode 103, the drain electrode 104, and the semiconductor layer 107 are directly laminated on the base substrate 101. An insulating film, such as silicon oxide or the like, is formed between the electrodes and the semiconductor layer 107 and the base substrate 101. A film of tantalum oxide Ta ₂ O ₅ or silicon nitride may be laminated.

An insulating film other than silicon nitride, such as silicon oxide, may be used for the gate insulating film 108.

Further, the source wiring 102 and the source electrode 1
03, the drain electrode 104 and the contact layer 105 are oxidized by thermal oxidation, but an oxidation method using O ₂ plasma or the like may be used as another oxidation method.

Further, the source wiring 102 and the source electrode 10
3, when the insulating film is formed by oxidizing the drain electrode 104 and the contact layer 105, there is a method in which the photosensitive insulating resin film 109 serving as a mask is removed and then oxidized. In this case, as shown in FIG. 3A, the contact layer 105
Since the insulating film 106 'is also formed on the upper surface of the insulating film 106', the insulating film 106 'must be removed by etching as shown in FIG. The structure of the thin film transistor manufactured by this method is shown in FIG.

(Embodiment 2) FIG. 5 shows a main part of a TFT according to Embodiment 2 of the present invention. FIG. 5A shows the plan configuration. FIG. 5B shows a sectional structure taken along line AA ′ of FIG. In addition, line B- in FIG. 5A is shown in FIG.
A sectional structure by B'is shown.

The main planar structure of the TFT of the second embodiment is the same as that of the first embodiment in terms of the wiring structure, and therefore the description thereof will be omitted and the cross-sectional structure will be described below.
The same parts as those in the first embodiment will be described with the same reference numerals.

As shown in FIG. 5B, the source wiring 102 and the drain electrode 104 are formed on the base substrate 101 at a predetermined interval. Contact layers 105 are formed on the upper surfaces of the source wiring 102 and the drain electrode 104 so as to have the same surface shape. Insulating films 106 and 106 are formed on both side portions of the step of the source wiring 102 and the contact layer 105 formed on the source wiring 102. A semiconductor layer 107 is formed with a predetermined width in a direction orthogonal to the source wiring 102 and the drain electrode 104. A gate insulating film 108 and a gate wiring 110 are laminated on the upper surface of the semiconductor layer 107 so as to have a uniform surface shape.

The above TFT according to the second embodiment is manufactured as follows. FIG. 6 shows a schematic manufacturing process.

First, an insulating base substrate 10 made of glass or the like.
A metal such as tantalum (Ta) is deposited on the substrate 1 by sputtering to a thickness of 100 nm. After that, the photosensitive insulating resin 109 for a mask for patterning the contact layer 105 is formed, and the manufacturing contents and the manufacturing procedure until the patterning is completed are the same as those in the first embodiment, and therefore the description thereof is omitted. The state of the results so far is shown in FIG.

Source wiring 102 and drain electrode 10
When the pattern formation of No. 4 is completed, the source wiring 102 and the source electrode 103 are anodized while leaving the masking photosensitive insulating resin film 109, and the source wiring 10 is formed.
2. Source electrode 103 and both electrode wirings 102 and 103
Oxide films 106 and 106 are formed on both step sides of the upper contact layer 105. The state of this result is shown in FIG.
It shows in (b).

After forming the oxide film 106, the contact layer 10 is formed.
The photosensitive insulating resin film 109 on 5 is removed. The resulting state is shown in FIG.

Amorphous silicon to be the semiconductor layer 107 is then deposited over the entire surface of the substrate 101 by P-CVD so as to cover all the wirings, electrodes and contact layer 105 described above. This semiconductor layer 107
Alternatively, microcrystalline silicon or polysilicon may be used as the material.

Subsequently, silicon nitride to be the gate insulating film 108 is continuously deposited on the semiconductor layer 107 by P-CVD to a thickness of 300 nm, and further, an A1 film is deposited on the semiconductor layer 107 by sputtering to a thickness of 200 nm. .

After these thin films are continuously deposited, the uppermost A1 film is patterned to form the gate wiring 110. The resulting state is shown in FIG.

Since the subsequent steps are the same as those in the first embodiment, the description thereof will be omitted. The state of the final result is shown in FIG.

Further, the source wiring 102 and the source electrode 10
3 and the contact layer 105 are oxidized to form an insulating film, the photosensitive insulating resin film 109 serving as a mask is removed and then oxidized. In this case, FIG. 7 (a)
As shown in FIG.
Since 6'is formed, this insulating film 106 'is formed as shown in FIG.
It must be removed by etching as in (b). The structure of the thin film transistor manufactured by this method is shown in FIG.

[0061]

In the thin film transistor according to the first aspect of the present invention, the insulating film is formed on both side surfaces of the step of the source electrode and / or the drain electrode, and the upper surfaces of both electrodes are covered with the contact layer. / Or the drain electrode does not contact the semiconductor layer. Therefore, the OFF current between the source and drain can be reduced.

In particular, according to the method of manufacturing a thin film transistor according to the third aspect, both electrodes are oxidized before the mask used for forming the source wiring and the drain electrode is removed. An insulating film can be formed without increasing the number of masks. That is, a TFT having a positive stagger structure with suppressed leakage current can be manufactured at low cost.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a TFT according to the present invention.

FIG. 2 is a schematic diagram of a TFT manufacturing process of Example 1.

FIG. 3 is a schematic view of a modification of the TFT manufacturing process of the first embodiment.

FIG. 4 is a diagram showing a TFT manufactured by a modification of the TFT manufacturing process of the first embodiment.

FIG. 5 is a diagram showing a second embodiment of a TFT according to the present invention.

FIG. 6 is a schematic view of a TFT manufacturing process of Example 2.

FIG. 7 is a schematic view of a modification of the TFT manufacturing process of the second embodiment.

FIG. 8 is a diagram showing a TFT manufactured by a modification of the TFT manufacturing process of the second embodiment.

FIG. 9 is a diagram showing a typical example of a conventional active matrix substrate using a TFT having an inverted stagger structure.

FIG. 10 is a diagram showing a typical example of a conventional active matrix substrate using a TFT having a positive stagger structure.

[Explanation of symbols]

 101 Base Substrate 102 Source Wiring 103 Source Electrode 104 Drain Electrode 105 Contact Layers 106 and 106 'Insulating Film 107 Semiconductor Layer 108 Gate Insulating Film 109 Photosensitive Insulating Resin Film 110 Gate Wiring 111 Picture Element Electrode

Claims (3)

[Claims] 1. A source electrode and a drain electrode on the same surface of an insulating substrate, contact layers having the same shape on the upper surfaces of the source electrode and the drain electrode, and the source electrode and / or the drain. The semiconductor layer, the gate insulating film, and the gate wiring are provided on the upper surface of the contact layer in the direction orthogonal to the source electrode and the drain electrode, while the insulating film is provided on both sides of the electrode and the contact layer. A thin film transistor having the same shape in this order. 2. The thin film transistor according to claim 1, wherein the insulating film is an oxide film. 3. A step of continuously laminating a conductive film and a thin film for a contact layer on the entire surface of an insulating substrate in this order, and a mask for forming a source electrode and a drain electrode on the upper surface of the thin film for the contact layer. A step of forming, a step of etching the conductive film and a thin film for a contact layer together to form a source electrode and a drain electrode having a contact layer of the same shape on the upper surface, and a step of The step of oxidizing the source electrode and / or the drain electrode and the contact layer to form an insulating film on the step side surfaces of each step, the step of removing the mask, the source electrode and the contact layer on the upper surface of the contact layer. A step of stacking a semiconductor layer, a thin film for a gate insulating film, and a conductive film for a gate wiring in this order and in the same width in a direction orthogonal to the drain electrode. The method for fabricating the thin film transistor including.