JPH06268376A - Manufacture of multilayer circuit board - Google Patents

Manufacture of multilayer circuit board

Info

Publication number
JPH06268376A
JPH06268376A JP5351793A JP5351793A JPH06268376A JP H06268376 A JPH06268376 A JP H06268376A JP 5351793 A JP5351793 A JP 5351793A JP 5351793 A JP5351793 A JP 5351793A JP H06268376 A JPH06268376 A JP H06268376A
Authority
JP
Japan
Prior art keywords
circuit board
multilayer circuit
insulating layer
conductor via
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5351793A
Other languages
Japanese (ja)
Inventor
Kishio Yokouchi
貴志男 横内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5351793A priority Critical patent/JPH06268376A/en
Publication of JPH06268376A publication Critical patent/JPH06268376A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To provide high-reliability multilayer circuit boards, concerning to a manufacturing method for multilayer circuit boards for mounting LSIs, etc., with high density. CONSTITUTION:The title manufacture of multilayer circuit board has processes of protruding a conductor via 3 from the surface of a surface insulating layer 21 like a stump by etching the surface of a multilayer circuit board 10 selectively after the formation of the conductor via 3, of forming an insulating film 5 on the surface insulating layer 21 in such a shape as to contain the conductor via 3 protruding like a stump from the surface of the surface insulating layer 21, of grinding the surface of the surface insulating layer 21 flatly covered with the insulating film 5 and removing selectively only the insulating film 5 covering the tip part of the above-mentioned conductor via 3, of forming a wiring pattern 50 on the conductor via 3 whose tip part is exposed by the removal of the insulating film 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、LSI等を高密度に実
装する多層回路基板の製造方法に関する。近年,大型汎
用コンピュータおよびスーパーコンピュータ等に使用さ
れる半導体素子の高速化は著しく、ゲートあたりの遅延
時間が100ps を下回るようになり、相対的に基板の配線
部分における伝送遅延がコンピュータの演算速度を左右
するに到っている。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layer circuit board on which LSIs and the like are mounted at high density. In recent years, the speed of semiconductor devices used in large-scale general-purpose computers and supercomputers has increased remarkably, and the delay time per gate has become less than 100 ps, and the transmission delay in the wiring part of the board relatively increases the computing speed of the computer. It has reached the point of influence.

【0002】この結果、コンピュータに実装される回路
基板は、高密度実装が可能で且つ微細な多層配線にも適
しているセラミックス材を絶縁材料とし、これと導体
(導体ビアおよび配線パターンを含む)を一体的に焼成
して製作される多層セラミックス回路基板(以下多層回
路基板と呼ぶ)が注目されている。
As a result, a circuit board mounted on a computer is made of a ceramic material, which is capable of high-density mounting and is suitable for fine multilayer wiring, as an insulating material, and a conductor (including a conductor via and a wiring pattern). Attention has been paid to a multilayer ceramic circuit board (hereinafter referred to as a multi-layer circuit board) manufactured by integrally baking the above.

【0003】[0003]

【従来の技術】図2(a) と(b) と(c) と(d) は従来の多
層回路基板の製造工程とその問題点を説明するための模
式的要部側断面図である。
2. Description of the Related Art FIGS. 2 (a), 2 (b), 2 (c) and 2 (d) are schematic side sectional views for explaining a conventional manufacturing process of a multilayer circuit board and its problems.

【0004】セラミックス材をベースとし、それに図示
しないビア部と導体配線層を設けた回路基板を積層して
製作されるこの多層回路基板20の表面絶縁層21内には導
体ビア3が形成され、その表面部分にはこの導体ビア3
に接続される配線パターン50が形成される。以下、この
多層回路基板20の製造工程を図2(a) と(b) と(c) と
(d) に基づいて説明する。
A conductor via 3 is formed in a surface insulating layer 21 of a multilayer circuit board 20 which is made by laminating a circuit board having a via portion and a conductor wiring layer (not shown) on the basis of a ceramic material. This conductor via 3 is on the surface
A wiring pattern 50 connected to is formed. The manufacturing process of this multilayer circuit board 20 will be described below with reference to FIGS. 2 (a), (b) and (c).
It will be explained based on (d).

【0005】1.第1工程〔図2(a) 参照〕 複数枚の回路基板を積層して形成された多層回路基板20
の表面部分に表面絶縁層21を形成した後、この表面絶縁
層21の所定位置に直径約 100μmのビア孔15を穿孔す
る。そして、このビア孔15の中に例えば銅等の導電性金
属をペースト化した導体金属8を充填する。
1. First Step [See FIG. 2 (a)] Multilayer circuit board 20 formed by stacking a plurality of circuit boards
After the surface insulating layer 21 is formed on the surface portion of, the via hole 15 having a diameter of about 100 μm is formed at a predetermined position of the surface insulating layer 21. Then, the via hole 15 is filled with a conductive metal 8 in which a conductive metal such as copper is pasted.

【0006】2.第2工程〔図2(b) 参照〕 ビア孔15の中に導体金属8を充填する工程が終了する
と、これを例えば窒素雰囲気炉等に収容して1000℃以下
の温度で焼成する。この焼成工程によってビア孔15内に
充填されている導体金属8は固形化する。但し、この焼
成工程によって導体金属8の外周面とビア孔15の内周面
間には微小間隙Δが生じる。この微小間隙Δはセラミッ
クス材と導体金属8の焼成挙動(焼成によってそれぞれ
の組織が変化する現象をいう)の違いと熱膨張率の差に
よって生じるものである。
2. Second step [see FIG. 2 (b)] When the step of filling the via hole 15 with the conductor metal 8 is completed, the via hole 15 is housed in, for example, a nitrogen atmosphere furnace and fired at a temperature of 1000 ° C. or less. The conductor metal 8 filled in the via hole 15 is solidified by this firing process. However, a minute gap Δ is formed between the outer peripheral surface of the conductor metal 8 and the inner peripheral surface of the via hole 15 by this firing step. This minute gap Δ is caused by the difference in the firing behavior (which means a phenomenon in which the respective structures change due to firing) of the ceramic material and the conductor metal 8 and the difference in the coefficient of thermal expansion.

【0007】3.第3工程〔図2(c) 参照〕 焼成工程が終了すると、次はこの多層回路基板20の面を
平面研削する。この平面研削は焼成工程によって粗面化
(焼成工程後の表面粗さは通常約10μm程度)した多層
回路基板20の表面粗さを1μm以下に制御すると共に、
表面絶縁層21の面から“はみ出している”導体金属8を
削り取って多層回路基板20の面を平坦化するために行わ
れる。この導体金属8の“はみ出し部分”を研削するこ
とによってビア孔15の中に導体ビア3が形成される。
3. Third step [see FIG. 2 (c)] After the firing step is finished, the surface of the multilayer circuit board 20 is next surface-ground. In this surface grinding, the surface roughness of the multilayer circuit board 20 roughened by the firing process (the surface roughness after the firing process is usually about 10 μm) is controlled to 1 μm or less, and
This is carried out in order to flatten the surface of the multilayer circuit board 20 by scraping off the conductive metal 8 that "sticks out" from the surface of the surface insulating layer 21. The conductor via 3 is formed in the via hole 15 by grinding the “protruding portion” of the conductor metal 8.

【0008】4.第4工程〔図2(d) 参照〕 導体ビア3の形成工程が終了すると、今度はこの導体ビ
ア3の上に配線パターン50を形成する。この配線パター
ン50は銅ペースト等をスクリーン印刷してこれを焼成す
ることによって形成される。
4. Fourth Step [see FIG. 2 (d)] When the step of forming the conductor via 3 is completed, the wiring pattern 50 is formed on the conductor via 3 this time. The wiring pattern 50 is formed by screen-printing a copper paste or the like and firing it.

【0009】[0009]

【発明が解決しようとする課題】従来の多層回路基板20
は上記工程を経て製作されるが、この多層回路基板20の
表面絶縁層21上に形成される配線パターン50は、図2
(b) と(c) と(d) に示すように、ビア孔15との間に微小
間隙Δが存在することで位置的に不安定状態にある導体
ビア3の上に形成されることから、その後に実施される
焼成工程等によって該配線パターン50にクラックαを生
じることがある。
A conventional multilayer circuit board 20.
The wiring pattern 50 formed on the surface insulating layer 21 of the multilayer circuit board 20 is manufactured by the above process.
As shown in (b), (c), and (d), it is formed on the conductor via 3 which is in a positionally unstable state due to the existence of the minute gap Δ between the via hole 15. However, cracks α may be generated in the wiring pattern 50 due to a firing process performed thereafter.

【0010】また、前記微小間隙Δの中には、研磨工程
或いは液相プロセス等,以後の工程で使用される各種の
処理液が染み込むことになるのでこれら処理液が配線パ
ターン50と反応することによって断線障害が発生する等
の問題もあった。
Further, various processing solutions used in the subsequent steps such as a polishing step and a liquid phase step will soak into the minute gap Δ, so that these processing solutions react with the wiring pattern 50. There was also a problem such as disconnection failure.

【0011】[0011]

【課題を解決するための手段】本発明による多層回路基
板の製造方法は、図1に示すように、導体ビア3形成後
の多層回路基板10の面を選択的にエッチングすることに
よって該導体ビア3を表面絶縁層21の面から切株状に突
出させる工程と、表面絶縁層21の面から切株状に突出し
た導体ビア3を含む形で表面絶縁層21上に絶縁膜5を形
成する工程と、絶縁膜5で覆われた表面絶縁層21の面を
平面研削して前記導体ビア3の頂部を覆っている絶縁膜
5のみを選択的に除去する工程と、絶縁膜5が除去され
たことによって頂部が露出した導体ビア3の上に配線パ
ターン50を形成する工程、を含むことを特徴とする。
As shown in FIG. 1, a method of manufacturing a multilayer circuit board according to the present invention includes a step of selectively etching the surface of a multilayer circuit board 10 on which a conductive via 3 has been formed. A step of projecting 3 from the surface of the surface insulating layer 21 in a stump shape, and a step of forming the insulating film 5 on the surface insulating layer 21 including the conductor vias 3 protruding in a stump shape from the surface of the surface insulating layer 21. The step of selectively removing only the insulating film 5 covering the top of the conductor via 3 by subjecting the surface of the surface insulating layer 21 covered with the insulating film 5 to surface grinding, and removing the insulating film 5 The step of forming the wiring pattern 50 on the conductor via 3 whose top is exposed by.

【0012】[0012]

【作用】この多層回路基板の製造方法は、導体ビア3と
ビア孔15間に生じた間隙Δを絶縁膜5によって埋める工
程が付加されていることから、導体ビア3とビア孔15間
に間隙Δが存在することによる諸障害(例えば研磨工程
或いは液相プロセス等で使用する各種処理液の染み込み
と残留,さらにはこれら処理液が配線パターン50と反応
することによって発生する断線障害等)が極めて効率的
に解消される。
In this method of manufacturing a multilayer circuit board, since the step of filling the gap Δ generated between the conductor via 3 and the via hole 15 with the insulating film 5 is added, the gap between the conductor via 3 and the via hole 15 is increased. Various obstacles due to the presence of Δ (for example, impregnation and retention of various treatment liquids used in the polishing process or liquid phase process, and further, disconnection faults caused by the reaction of these treatment liquids with the wiring pattern 50) are extremely Efficiently resolved.

【0013】[0013]

【実施例】以下実施例図に基づいて本発明を詳細に説明
する。図1(a) と(b) と(c) と(d) は本発明の一実施例
を工程順に示した模式的要部側断面図であるが、前記図
2と同一部分にはそれぞれ同一符号を付している。
The present invention will be described in detail below with reference to the drawings of the embodiments. 1 (a), 1 (b), 1 (c) and 1 (d) are schematic side cross-sectional views showing an embodiment of the present invention in the order of steps. The code is attached.

【0014】本発明による多層回路基板の製造方法は、
図1(a) と(b) と(c) と(d) に示すように、導体ビア3
形成後の多層回路基板10の面を選択的にエッチングする
ことによって導体ビア3を表面絶縁層21の面から切株状
に突出させる工程と、表面絶縁層21の面から切株状に突
出した導体ビア3を含む形でその表面部分に絶縁膜5を
形成する工程と、絶縁膜5で覆われたこの多層回路基板
10を平面研削して前記導体ビア3の頂部を覆っている絶
縁膜5のみを選択的に除去する工程と、絶縁膜5が除去
されたことによって頂部が露出した導体ビア3の上に配
線パターン50を形成する工程、を含むことをその特徴と
する。
The method of manufacturing a multilayer circuit board according to the present invention is
As shown in Figures 1 (a), (b), (c), and (d), the conductor via 3
A step of selectively projecting the surface of the formed multilayer circuit board 10 to project the conductor via 3 in a stub shape from the surface of the surface insulating layer 21, and a conductor via projecting from the surface of the surface insulating layer 21 in a stub shape. And a step of forming an insulating film 5 on the surface of the multilayer circuit board covered with the insulating film 5.
A step of selectively removing only the insulating film 5 covering the top of the conductor via 3 by surface grinding 10 and a wiring pattern on the conductor via 3 having the top exposed by the removal of the insulating film 5. And forming 50.

【0015】なお、この多層回路基板10は下記手順によ
ってこれを製作する。 (1)平均粒径が約2μmのアルミナ50Wt%と硼珪酸ガラ
ス50Wt%をバインダ樹脂およびアセトン,2−ブタノン
(ブタノール)等の溶剤や可塑材と混練してスラリーを
作成する。
The multilayer circuit board 10 is manufactured by the following procedure. (1) 50 Wt% of alumina having an average particle size of about 2 μm and 50 Wt% of borosilicate glass are kneaded with a binder resin and a solvent such as acetone or 2-butanone (butanol) or a plasticizer to prepare a slurry.

【0016】(2)このスラリーをポリエステルフィルム
上に塗布し、ドクターブレードによってその厚さが300
μmとなるように加工してグリーンシートを形成する。 (3)このグリーンシートを一辺が約 200mmの正方形に
打ち抜いた後、所定部分を例えば直径約 100μmのパン
チで打ち抜いて導体ビアを形成するための貫通孔を形成
する。
(2) This slurry was coated on a polyester film and the thickness was adjusted to 300 with a doctor blade.
A green sheet is formed by processing so as to have a thickness of μm. (3) After punching this green sheet into a square having a side of about 200 mm, a predetermined portion is punched with, for example, a punch having a diameter of about 100 μm to form a through hole for forming a conductive via.

【0017】(4)この貫通孔の中に銅ペーストを充填
し、その後この貫通孔を覆う形で配線パターンをスクリ
ーン印刷する。 (5)このようにして製作したグリーンシートを複数層重
ねてプレスを用いて積層する。
(4) Copper paste is filled in the through holes, and then a wiring pattern is screen-printed so as to cover the through holes. (5) A plurality of green sheets manufactured in this manner are stacked and laminated using a press.

【0018】(6)これを窒素雰囲気炉内に収容して1000
℃以下の温度で焼成する。 以下図1(a) と(b) と(c) と(d) に基づいて本発明によ
る多層回路基板の製造方法を具体的に説明する。なお、
以下に示す工程は、従来の第3工程〔図2(c)参照〕終
了後に実施されるもので、それ以前の工程は従来工程
〔図2(a) と(b)と(c) 〕と同じであるから説明を省略
する。
(6) This was housed in a nitrogen atmosphere furnace and 1000
Baking at a temperature of ℃ or less. Hereinafter, a method for manufacturing a multilayer circuit board according to the present invention will be specifically described with reference to FIGS. 1 (a), 1 (b), 1 (c) and 1 (d). In addition,
The following steps are performed after the completion of the third conventional step [see FIG. 2 (c)], and the steps before that are the conventional steps [FIGS. 2 (a), (b) and (c)]. Since it is the same, the description is omitted.

【0019】1.第1工程〔図1(a) 参照〕 CF4 等のふっ素系化合物或いはCF4 等のふっ素系化
合物を主成分とする混合ガスを使用したプラズマエッチ
ング法等を適用して導体ビア3形成後〔図2(c)参照〕
の多層回路基板10の表面絶縁層21を選択的にエッチング
(2点鎖線で示す部分がエッチング対象部分)して導体
ビア3を表面絶縁層21の面から切株状に突出させる。
1. The first step [see FIG. 1 (a)] CF fluorine such as 4 compound or CF 4 or the like fluorine-based compounds by a plasma etching method using a mixed gas mainly composed conductive via 3 formed later [ See Figure 2 (c)]
The surface insulating layer 21 of the multilayer circuit board 10 is selectively etched (the portion indicated by the chain double-dashed line is the portion to be etched) to project the conductor via 3 from the surface of the surface insulating layer 21 in a stub shape.

【0020】2.第2工程〔図1(b) 参照〕 表面絶縁層21の面から切株状に突出した導体ビア3を含
む形でこの多層回路基板10の表面部分に窒化珪素膜から
なる絶縁膜5を形成する。これによってビア孔15の内周
面と導体ビア3の外周面間に生じている微小間隙Δの中
に絶縁膜5が浸透して微小間隙Δを埋めるので導体ビア
3は極めて安定的なものになる。
2. Second step [see FIG. 1 (b)] An insulating film 5 made of a silicon nitride film is formed on the surface portion of the multilayer circuit board 10 including the conductor vias 3 protruding in a stub shape from the surface of the surface insulating layer 21. . As a result, the insulating film 5 penetrates into the minute gap Δ formed between the inner peripheral surface of the via hole 15 and the outer peripheral surface of the conductor via 3 and fills the minute gap Δ, so that the conductor via 3 is extremely stable. Become.

【0021】3.第3工程〔図1(c) 参照〕 導体ビア3の頂部に形成されている絶縁膜5のみが選択
的に除去されるようにこの多層回路基板10を平面研削す
る。これによって導体ビア3の頂部のみが露出すること
なる。なお、導体ビア3の頂部を除く部分に形成された
絶縁膜5はそのまま残って絶縁層を形成する。
3. Third step (see FIG. 1C) The multilayer circuit board 10 is surface-ground so that only the insulating film 5 formed on the tops of the conductor vias 3 is selectively removed. As a result, only the top of the conductor via 3 is exposed. The insulating film 5 formed on the portion other than the top of the conductor via 3 remains as it is to form an insulating layer.

【0022】4.第4工程〔図1(d) 参照〕 頂部のみが露出状態になった導体ビア3と、表面絶縁層
21上にそのまま残っている絶縁膜5の上に配線パターン
50を形成する。この配線パターン50は、微小間隙Δ内に
浸透した絶縁膜5によって位置が安定している導体ビア
3の上に形成されることになるので前記図2(c) に示さ
れているようなクラックαを生じることはない。また、
この多層回路基板10は、絶縁膜5が研磨工程或いは液相
プロセス等で使用する各種処理液の染み込みを阻止する
ことから、配線パターン50が断線する等の事故が発生す
る危険性が無いので品質的に極めて安定している。
4. Fourth step [see FIG. 1 (d)] Conductor via 3 with only the top exposed, and surface insulating layer
Wiring pattern on the insulating film 5 which remains on 21
Forming 50. Since the wiring pattern 50 is formed on the conductor via 3 whose position is stable by the insulating film 5 that has penetrated into the minute gap Δ, cracks as shown in FIG. It does not produce α. Also,
Since the insulating film 5 prevents the processing liquid used in the polishing process or the liquid phase process from seeping in, the multilayer circuit board 10 has no risk of causing an accident such as disconnection of the wiring pattern 50. Extremely stable.

【0023】以上述べた実施例は複数枚の回路基板を積
層して構成される多層回路基板10を対象としているが、
この方法は多層回路基板10を構成する個々の回路基板に
適用することも可能である。
Although the embodiment described above is intended for the multilayer circuit board 10 constructed by laminating a plurality of circuit boards,
This method can also be applied to individual circuit boards constituting the multilayer circuit board 10.

【0024】[0024]

【発明の効果】以上の説明から明らかなように、本発明
による多層回路基板の製造方法は、焼成工程で導体ビア
とビア孔間に生じた間隙を絶縁膜によって埋める工程が
付加されていることから、導体ビアとビア孔間に間隙が
存在することによって発生する諸障害が極めて効果的に
解消されて多層回路基板の信頼性が著しく向上する。
As is apparent from the above description, the method for manufacturing a multilayer circuit board according to the present invention additionally includes a step of filling the gap between the conductive vias and the via holes in the firing step with the insulating film. Therefore, various obstacles caused by the existence of the gap between the conductive via and the via hole are effectively eliminated, and the reliability of the multilayer circuit board is significantly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施例を工程順に示した模式的要
部側断面図である。
FIG. 1 is a schematic side sectional view of an essential part showing an embodiment of the present invention in the order of steps.

【図2】 従来の多層回路基板の製造工程とその問題点
を説明するための模式的要部側断面図である。
FIG. 2 is a schematic cross-sectional side view of a main part for explaining a conventional manufacturing process of a multilayer circuit board and its problems.

【符号の説明】[Explanation of symbols]

3 導体ビア 5 絶縁膜 8 導体金属 10,20 多層回路基板 15 ビア孔 21 表面絶縁層 50 配線パターン α クラック Δ 微小間隙 3 Conductor via 5 Insulating film 8 Conductor metal 10,20 Multilayer circuit board 15 Via hole 21 Surface insulating layer 50 Wiring pattern α Crack Δ Minute gap

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 表面絶縁層(21)内に形成された導体ビア
(3) に接続される配線パターン(50)がその表面部分に形
成されてなる多層回路基板(10)の製造方法であって、 導体ビア(3) 形成後の多層回路基板(10)の面を選択的に
エッチングすることによって該導体ビア(3) を表面絶縁
層(21)の面から切株状に突出させる工程と、 表面絶縁層(21)の面から切株状に突出した導体ビア(3)
を含む形で表面絶縁層(21)上に絶縁膜(5) を形成する工
程と、 絶縁膜(5) で覆われた表面絶縁層(21)の面を平面研削し
て前記導体ビア(3) の頂部を覆っている絶縁膜(5) のみ
を選択的に除去する工程と、 絶縁膜(5) が除去されたことによって頂部が露出した導
体ビア(3) の上に配線パターン(50)を形成する工程と、 を含むことを特徴とする多層回路基板の製造方法。
1. A conductor via formed in a surface insulating layer (21)
A method for manufacturing a multilayer circuit board (10), wherein a wiring pattern (50) connected to (3) is formed on a surface portion of the wiring pattern (50), the surface of the multilayer circuit board (10) after forming a conductor via (3). A step of projecting the conductor vias (3) in a stump shape from the surface of the surface insulating layer (21) by selectively etching the conductive vias (3), and a conductor via (3) protruding in a stump shape from the surface of the surface insulating layer (21). )
Including the step of forming the insulating film (5) on the surface insulating layer (21), and the surface of the surface insulating layer (21) covered with the insulating film (5) is ground to the conductor via (3). ) Selectively removing only the insulating film (5) covering the top part of the wiring) and the wiring pattern (50) on the conductor via (3) whose top is exposed due to the removal of the insulating film (5). A method of manufacturing a multilayer circuit board, comprising:
【請求項2】 ふっ素系化合物或いはふっ素系化合物を
主成分とする混合ガスを使用したプラズマエッチング法
を適用して前記導体ビア(3) 形成後の多層回路基板(10)
の面を選択的にエッチングするようにしたことを特徴と
する請求項1記載の多層回路基板の製造方法。
2. A multilayer circuit board (10) after the conductor vias (3) are formed by applying a plasma etching method using a fluorine compound or a mixed gas containing a fluorine compound as a main component.
2. The method for manufacturing a multilayer circuit board according to claim 1, wherein the surface of the substrate is selectively etched.
【請求項3】 約50Wt%のガラス材を含むセラミックス
材を溶剤及び可塑剤と混練してなるスラリーを用いて前
記多層回路基板(10)を製作するようにしたことを特徴と
する請求項1記載の多層回路基板の製造方法。
3. The multilayer circuit board (10) is manufactured by using a slurry prepared by kneading a ceramic material containing about 50 Wt% of a glass material with a solvent and a plasticizer. A method for manufacturing the multilayer circuit board described.
JP5351793A 1993-03-15 1993-03-15 Manufacture of multilayer circuit board Withdrawn JPH06268376A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5351793A JPH06268376A (en) 1993-03-15 1993-03-15 Manufacture of multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5351793A JPH06268376A (en) 1993-03-15 1993-03-15 Manufacture of multilayer circuit board

Publications (1)

Publication Number Publication Date
JPH06268376A true JPH06268376A (en) 1994-09-22

Family

ID=12945021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5351793A Withdrawn JPH06268376A (en) 1993-03-15 1993-03-15 Manufacture of multilayer circuit board

Country Status (1)

Country Link
JP (1) JPH06268376A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368368A (en) * 2001-06-04 2002-12-20 Hitachi Chem Co Ltd Connection board, multilayered wiring board using the same, semiconductor package board, semiconductor package, method of manufacturing connection board, method of manufacturing multilayer wiring board therethrough, method of manufacturing semiconductor package board, and method of manufacturing semiconductor package
JP2013033894A (en) * 2011-06-27 2013-02-14 Shinko Electric Ind Co Ltd Wiring board, manufacturing method of the same and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368368A (en) * 2001-06-04 2002-12-20 Hitachi Chem Co Ltd Connection board, multilayered wiring board using the same, semiconductor package board, semiconductor package, method of manufacturing connection board, method of manufacturing multilayer wiring board therethrough, method of manufacturing semiconductor package board, and method of manufacturing semiconductor package
JP2013033894A (en) * 2011-06-27 2013-02-14 Shinko Electric Ind Co Ltd Wiring board, manufacturing method of the same and semiconductor device

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