JPH06268017A - Method for mounting bare chip type semiconductor device - Google Patents

Method for mounting bare chip type semiconductor device

Info

Publication number
JPH06268017A
JPH06268017A JP5450293A JP5450293A JPH06268017A JP H06268017 A JPH06268017 A JP H06268017A JP 5450293 A JP5450293 A JP 5450293A JP 5450293 A JP5450293 A JP 5450293A JP H06268017 A JPH06268017 A JP H06268017A
Authority
JP
Japan
Prior art keywords
melting point
semiconductor device
type semiconductor
point solder
bare chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5450293A
Other languages
Japanese (ja)
Other versions
JPH0779116B2 (en
Inventor
Yoshito Kamioka
義人 上岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5450293A priority Critical patent/JPH0779116B2/en
Publication of JPH06268017A publication Critical patent/JPH06268017A/en
Publication of JPH0779116B2 publication Critical patent/JPH0779116B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To allow inspection, modification and electric inspection of a mounting position. CONSTITUTION:After forming a three-layer bump provided with high-melting point solder 4, a core layer 5 and low-melting point solder 6 on the electrode pad 2 of a bare chip type semiconductor device 1, the bare chip type semiconductor device 1 is mounted on a wiring board 10. Then, the device 1 is tentatively connected on the mounting pad 9 of the wiring board 10 by heating and melting the bump at the melting temperature of the solder 6 and the device 1 is inspected under such conditions. The bump is heated and melted at the melting temperature of the high-melting point solder 4 and pressure is applied so as to connect the high-melting point solder 4 with the mounting pad 9.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はベアチップ型半導体装置
の実装方法、特に、はんだバンプを用いて半導体装置を
基板に接続するベアチップ型半導体装置の実装方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bare chip type semiconductor device mounting method, and more particularly to a bare chip type semiconductor device mounting method for connecting a semiconductor device to a substrate using solder bumps.

【0002】[0002]

【従来の技術】図4(a)〜(f)は従来の一例を説明
する工程断面図である。図4(a)〜(f)に示すベア
チップ型半導体装置の実装方法は、ベアチップ型半導体
装置1の電極パッド2上にメッキ法を用いてはんだバン
プ6aを形成し、その後フロー工程ではんだバンプ6a
を半球状にし図4(e)に示すように配線基板10上の
搭載パッド9上に位置合わせして搭載する。搭載後図4
(f)に示すようにはんだの溶融温度に加熱することに
より搭載パッド9とはんだバンプ6aとを接合する。ま
た、特開昭62−250647号公報に示されているよ
うに、はんだバンプ6aを半溶融状態になるまで加熱し
つつベアチップ型半導体装置1の動作検査を行う技術が
ある。
2. Description of the Related Art FIGS. 4 (a) to 4 (f) are process sectional views for explaining an example of the prior art. In the bare chip type semiconductor device mounting method shown in FIGS. 4A to 4F, the solder bumps 6a are formed on the electrode pads 2 of the bare chip type semiconductor device 1 by using a plating method, and then the solder bumps 6a are formed by a flow process.
Is formed into a hemispherical shape and is aligned and mounted on the mounting pad 9 on the wiring board 10 as shown in FIG. Figure 4 after mounting
As shown in (f), the mounting pad 9 and the solder bump 6a are joined by heating to the melting temperature of the solder. Further, as disclosed in Japanese Unexamined Patent Publication No. 62-250647, there is a technique of performing an operation inspection of the bare chip type semiconductor device 1 while heating the solder bumps 6a to a semi-molten state.

【0003】[0003]

【発明が解決しようとする課題】この従来のベアチップ
型半導体装置の実装方法は、搭載パッド5とはんだバン
プ7との位置ずれが発生した場合、または電気的検査に
より不良品と判定した場合には、はんだバンプ7を加熱
溶融してベアチップ型半導体装置1を基板から取り外し
再搭載しなければならない。従来のベアチップ型半導体
装置の実装方法では、ベアチップ型半導体装置1を配線
基板6から取り外す際に、搭載パッド5上にはんだが残
るとともにバンプ7の形状が破壊される。従って位置ず
れ修正の際には、はんだバンプの形状不良によるオープ
ン不良が発生する。また、良品ベアチップを再搭載する
際には搭載パッド5上のはんだ残りによる隣接間パッド
のショート不良が発生したり、他パッドと比較してはん
だ残りの少ないパッドでオープン不良が発生するという
問題があった。また、はんだバンプを半溶融温度に加熱
しつつベアチップ型半導体装置の動作検査を行う方法で
は高精度の温度コントロールが必要となり、製造工程を
安定に維持することが困難であるという問題があった。
This conventional bare-chip type semiconductor device mounting method is used when the mounting pad 5 and the solder bump 7 are misaligned or when an electrical inspection determines that the product is defective. It is necessary to heat and melt the solder bumps 7 and remove the bare chip type semiconductor device 1 from the substrate and mount it again. In the conventional bare chip type semiconductor device mounting method, when the bare chip type semiconductor device 1 is removed from the wiring substrate 6, solder remains on the mounting pads 5 and the shape of the bumps 7 is destroyed. Therefore, when the misalignment is corrected, an open defect occurs due to a defective shape of the solder bump. Further, when the non-defective bare chip is remounted, a short circuit between adjacent pads may occur due to a solder residue on the mounting pad 5, or an open defect may occur in a pad having less solder residue than other pads. there were. Further, in the method of performing the operation inspection of the bare chip type semiconductor device while heating the solder bumps to the semi-melting temperature, it is necessary to control the temperature with high accuracy, and it is difficult to stably maintain the manufacturing process.

【0004】[0004]

【課題を解決するための手段】本発明のベアチップ型半
導体装置の実装方法は、ベアチップ型半導体装置の電極
パッド上に高融点はんだとコア層と低融点はんだとを有
する3層バンプを形成し、あるいはベアチップ型半導体
装置の電極パッド上に高融点はんだとコア層とを有する
2層バンプを形成し低融点はんだを配線基板または電気
的選別治具の搭載パッド上に形成する。次いで低融点は
んだの溶融温度に加熱しベアチップ型半導体装置を仮実
装した状態で電気的検査および搭載位置検査を実施す
る。このとき電気的検査不合格または搭載位置不良の場
合は、再度低融点はんだの溶融温度に加熱して不良品ま
たは搭載不良のベアチップ型半導体装置を取り外し、良
品のベアチップ型半導体装置を搭載する。または搭載位
置を修正する。電気的検査と搭載位置が正常の場合に
は、高融点はんだの溶融温度に加熱するとともに加圧
し、コア層を高融点はんだで包み込み高融点はんだと配
線基板の搭載パッドとを接続する。
According to a method of mounting a bare chip type semiconductor device of the present invention, a three-layer bump having a high melting point solder, a core layer and a low melting point solder is formed on an electrode pad of the bare chip type semiconductor device, Alternatively, a two-layer bump having a high melting point solder and a core layer is formed on the electrode pad of the bare chip type semiconductor device, and the low melting point solder is formed on the mounting pad of the wiring board or the electrical selection jig. Next, an electrical inspection and a mounting position inspection are carried out in a state where the bare chip type semiconductor device is temporarily mounted by heating to the melting temperature of the low melting point solder. At this time, if the electrical inspection fails or the mounting position is defective, the bare chip type semiconductor device having the defective product or the mounting defect is removed by heating again to the melting temperature of the low melting point solder, and the non-defective bare chip semiconductor device is mounted. Or correct the mounting position. When the electrical inspection and the mounting position are normal, the melting point of the high melting point solder is heated and pressed, the core layer is wrapped with the high melting point solder, and the high melting point solder and the mounting pad of the wiring board are connected.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0006】図1(a)〜(g)は、本発明の第1の実
施例を示す工程断面図である。図1(a)〜(d)はバ
ンプを形成する工程を示す。このバンプの製造に当たっ
ては、まず、ベアチップ型半導体装置1の電極パッド2
以外のところへ図1(b)のようにレジスト3を形成
し、次いで電極パッド2上に電解メッキ法を用いて図1
(c)のように高融点はんだ4(Pb−Sn5wt%S
n)、コア層5(Cu)、低融点はんだ6(Sn−Pb
37wt%Pb)を順次メッキする。その後図1(d)
のようにレジスト3を剥離する。
FIGS. 1A to 1G are process sectional views showing a first embodiment of the present invention. 1A to 1D show steps of forming bumps. In manufacturing the bump, first, the electrode pad 2 of the bare chip semiconductor device 1 is manufactured.
A resist 3 is formed elsewhere as shown in FIG. 1B, and then the electrode pad 2 is electroplated to form the resist 3 shown in FIG.
High melting point solder 4 (Pb-Sn 5 wt% S as shown in (c))
n), core layer 5 (Cu), low melting point solder 6 (Sn-Pb)
37 wt% Pb) is sequentially plated. After that, Fig. 1 (d)
Then, the resist 3 is peeled off.

【0007】図1(e)〜(g)はベアチップ型半導体
装置を配線基板に実装する工程を示す。図1(e)のよ
うにベアチップ型半導体装置1上に形成した高融点はん
だ4とコア層5と低融点はんだ6とからなる3層バンプ
を配線基板10上の搭載パッド9へ位置を合わせ搭載す
る。図1(f)は低融点はんだの溶融温度に加熱し(本
実施例では高融点はんだの溶融温度以下の220℃とし
た)、低融点はんだ6と搭載パッド9とを接合した状態
の断面図である。この状態で搭載位置の検査および電気
的検査を実施する。搭載位置がずれている場合もしくは
電気的検査不合格の場合には低融点はんだ6の溶融温度
に再加熱しベアチップ型半導体装置1を取り外す。ベア
チップ型半導体装置1を取り外す際にコア層5がバリア
の役目をするので高融点はんだ4の一部が低融点はんだ
6へ溶け込むことがなく安定した温度で低融点はんだ6
を溶融することができる。また、ベアチップ型半導体装
置1を取り外した際に高融点はんだ4が破壊されないこ
とと、搭載パッド9上の残留はんだが微量であることに
より、搭載位置ずれを修正する際のバンプ形状不良によ
るオープン不良および良品のベアチップ型半導体装置を
再搭載する際に搭載パッド上のはんだ残留による隣接パ
ッド間のショート不良をなくすることができる。図1
(g)は搭載位置検査および電気的検査完了後、高融点
はんだの溶融温度(本実施例では324℃とした)に加
熱するとともにベアチップ型半導体装置1を加圧し、コ
ア層5を高融点はんだ4で包み込み、高融点はんだ4と
搭載パッド9とを接合した状態の断面図である。このよ
うにコア層5を包み込んで接合することにより、バンプ
の機械的強度が向上し、冷却モジュール等を装着した際
の荷重によるバンプ潰れを低減することができる。
FIGS. 1E to 1G show a process of mounting a bare chip type semiconductor device on a wiring board. As shown in FIG. 1E, a three-layer bump made of a high melting point solder 4, a core layer 5 and a low melting point solder 6 formed on the bare chip type semiconductor device 1 is mounted on a mounting pad 9 on a wiring substrate 10 by aligning the positions. To do. FIG. 1F is a cross-sectional view showing a state in which the low melting point solder 6 and the mounting pad 9 are joined by heating to the melting temperature of the low melting point solder (220 ° C. which is lower than the melting temperature of the high melting point solder in this embodiment). Is. In this state, the mounting position inspection and electrical inspection are performed. When the mounting position is displaced or when the electrical inspection fails, the bare chip type semiconductor device 1 is removed by reheating to the melting temperature of the low melting point solder 6. When the bare chip type semiconductor device 1 is detached, the core layer 5 functions as a barrier, so that the high melting point solder 4 does not partially melt into the low melting point solder 6 and the low melting point solder 6 is maintained at a stable temperature.
Can be melted. Further, since the high melting point solder 4 is not destroyed when the bare chip type semiconductor device 1 is removed and the amount of the residual solder on the mounting pad 9 is small, an open defect due to a bump shape defect when correcting the mounting position deviation. Further, when a non-defective bare chip type semiconductor device is re-mounted, it is possible to eliminate short-circuit defects between adjacent pads due to residual solder on the mounting pads. Figure 1
After the mounting position inspection and the electrical inspection are completed, (g) shows that the core chip 5 is heated to the melting temperature of the high melting point solder (which is 324 ° C. in this embodiment) and the bare chip type semiconductor device 1 is pressed to make the core layer 5 high melting point solder 4 is a cross-sectional view showing a state in which the high melting point solder 4 and the mounting pad 9 are wrapped in each other and joined to each other. By wrapping and bonding the core layer 5 in this way, the mechanical strength of the bumps is improved, and bump crushing due to the load when the cooling module or the like is mounted can be reduced.

【0008】図2(a)〜(b)は本発明の第2の実施
例を示す工程断面図である。ポンチ7とダイス8とを用
いて高融点はんだ4(Pb−Sn5wt%Sn)とコア
層5(Cu)と低融点はんだ6(Sn−Pb37wt%
Pb)とからなる三層箔材11を打ち抜いて、この際の
ポンチ7のストロークで打ち抜き片を加熱(本実施例で
は120℃とした)したベアチップ型半導体装置1の電
極パッド2上に熱圧着する。
2 (a) and 2 (b) are process sectional views showing a second embodiment of the present invention. Using the punch 7 and the die 8, the high melting point solder 4 (Pb-Sn 5 wt% Sn), the core layer 5 (Cu), and the low melting point solder 6 (Sn-Pb 37 wt%).
Pb) is punched out from the three-layer foil material 11, and the punched piece is heated by the stroke of the punch 7 at this time (120 ° C. in this embodiment) to be thermocompression bonded onto the electrode pad 2 of the bare chip type semiconductor device 1. To do.

【0009】図3(a)〜(c)は、本発明の第3の実
施例を示す工程断面図である。本実施例ではバンプ形成
は、図1(a)〜(d)で説明したようなメッキ法を用
いて、ベアチップ型半導体装置1の電極パッド2上に高
融点はんだ4とコア層5とを形成し、あるいは図2
(a)〜(b)で説明したような打ち抜き法を用いて、
ベアチップ型半導体装置1の電極パッド2上に高融点は
んだ4とコア層5とからなる二層材の打ち抜き片を熱圧
着する。これらの場合、配線基板10の搭載パッド9上
に低融点はんだ6をメッキ法を用いて形成する。搭載位
置検査および電気的検査は第1の実施例と同様に行うこ
とができる。また、ベアチップ型半導体装置を配線基板
上に本接続する際も第1の実施例と同様に行うことがで
きる。
3A to 3C are process sectional views showing a third embodiment of the present invention. In this embodiment, the bumps are formed by forming the high melting point solder 4 and the core layer 5 on the electrode pad 2 of the bare chip type semiconductor device 1 by using the plating method as described with reference to FIGS. Or Fig. 2
Using the punching method as described in (a) and (b),
On the electrode pad 2 of the bare chip type semiconductor device 1, a punched piece of a two-layer material composed of the high melting point solder 4 and the core layer 5 is thermocompression bonded. In these cases, the low melting point solder 6 is formed on the mounting pad 9 of the wiring board 10 by the plating method. The mounting position inspection and the electrical inspection can be performed in the same manner as in the first embodiment. Also, when the bare chip type semiconductor device is permanently connected to the wiring substrate, it can be performed in the same manner as in the first embodiment.

【0010】電気的選別治具でベアチップ型半導体装置
を検査する場合は、ベアチップ型半導体装置を電気的選
別治具に搭載し、低融点はんだの溶融温度に加熱して仮
接続し、その状態で電気的検査を行い、その後低融点は
んだの溶融温度に再加熱してベアチップ型半導体装置を
電気的選別治具から取り外して配線基板に移載し、高融
点はんだの溶融温度に加熱しベアチップ型半導体装置を
配線基板に本接続する。
When the bare chip type semiconductor device is inspected by the electrical sorting jig, the bare chip type semiconductor device is mounted on the electrical sorting jig, heated to the melting temperature of the low melting point solder and temporarily connected, and in that state. Conduct an electrical inspection, then reheat to the melting temperature of the low melting point solder, remove the bare chip type semiconductor device from the electrical sorting jig, transfer it to the wiring board, heat to the melting temperature of the high melting point solder, and bare chip type semiconductor The device is permanently connected to the wiring board.

【0011】[0011]

【発明の効果】以上説明したように本発明は、ベアチッ
プ型半導体装置に形成するバンプを高融点はんだとコア
層と低融点はんだとを有する三層構造とすることによ
り、またはベアチップ型半導体装置に形成するバンプを
高融点はんだとコア層とを有する二層構造とし配線基板
の搭載パッドもしくは電気的治具の搭載パッドに低融点
はんだ設けて等価的な三層構造とすることにより、基板
への実装を2段階の加熱溶融によって行うことができる
ので、低融点はんだ溶融接合段階で搭載位置の検査およ
び電気的検査が実施できる。すなわち、検査不良時に低
融点はんだの溶融温度にしてベアチップ型半導体装置を
取り外す際に高融点はんだバンプの形状が破壊されない
こと、また搭載パッド上の残留はんだが微量であること
により、搭載位置ずれを修正する際のバンプの形状不良
によるオープン不良および良品のベアチップ型半導体装
置を再搭載する際の搭載パッド上の残留はんだによる隣
接パッド間のショート不良や他のパッドに比べて残留は
んだが少ないパッドのオープン不良をなくすることがで
きる。また、不良のベアチップ型半導体装置を取り外す
際に、コア層がバリアの役目をするので高融点はんだの
一部が低融点はんだへ溶け込むことがなくなり安定した
温度で低融点はんだを溶融することができる。良品のベ
アチップ型半導体装置を配線基板上に実装する際に、加
熱するとともに加圧し、コア層を高融点はんだで包み込
んだ形状にすることにより、バンプの機械的強度が向上
し、冷却モジュール等を装着した際の荷重によるバンプ
潰れを低減することができるというような効果がある。
As described above, according to the present invention, a bump formed on a bare chip type semiconductor device has a three-layer structure having a high melting point solder, a core layer and a low melting point solder, or a bare chip type semiconductor device. The bump to be formed has a two-layer structure having a high melting point solder and a core layer, and a low melting point solder is provided on the mounting pad of the wiring board or the mounting pad of the electric jig to form an equivalent three layer structure. Since the mounting can be carried out by heating and melting in two steps, the mounting position inspection and the electrical inspection can be performed in the low melting point solder melting and joining step. That is, when the inspection is defective, the melting point of the low melting point solder is set to the melting point and the shape of the high melting point solder bump is not destroyed when the bare chip type semiconductor device is removed. Open defects due to bump shape defects when repairing, short defects between adjacent pads due to residual solder on the mounting pads when remounting a good bare chip type semiconductor device, and pads with less residual solder than other pads Open defects can be eliminated. Further, when the defective bare chip type semiconductor device is removed, the core layer serves as a barrier so that a part of the high melting point solder does not melt into the low melting point solder and the low melting point solder can be melted at a stable temperature. . When mounting a good bare chip type semiconductor device on the wiring board, it is heated and pressed, and the core layer is wrapped with high-melting point solder to improve the mechanical strength of the bumps and improve the cooling module. There is an effect that bump crushing due to the load when mounted can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(g)は本発明の第1の実施例を示す
工程断面図である。
1A to 1G are process cross-sectional views showing a first embodiment of the present invention.

【図2】(a)〜(b)は本発明の第2の実施例を示す
工程断面図である。
2A to 2B are process sectional views showing a second embodiment of the present invention.

【図3】(a)〜(c)は本発明の第3の実施例を示す
工程断面図である。
3A to 3C are process sectional views showing a third embodiment of the present invention.

【図4】(a)〜(f)は従来の一例を示す工程断面図
である。
4A to 4F are process cross-sectional views showing a conventional example.

【符号の説明】[Explanation of symbols]

1 ベアチップ型半導体装置 2 電極パッド 3 レジスト 4 高融点はんだ 5 コア層 6 低融点はんだ 6a はんだバンプ 7 ポンチ 8 ダイス 9 搭載パッド 10 配線基板 11 三層箔材 1 Bare Chip Type Semiconductor Device 2 Electrode Pad 3 Resist 4 High Melting Point Solder 5 Core Layer 6 Low Melting Point Solder 6a Solder Bump 7 Punch 8 Die 9 Mounting Pad 10 Wiring Board 11 Three Layer Foil Material

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 ベアチップ型の半導体装置の電極部に高
融点はんだ層とコア層と低融点はんだ層とを有する三層
バンプを形成した後、前記ベアチップ型半導体装置を配
線基板上に搭載し、次いで前記低融点はんだの溶融温度
で前記低融点はんだを加熱溶融して前記配線基板上の搭
載パッド上に仮接続し、この状態で前記ベアチップ型半
導体装置の検査を行い不良品があった場合は良品と交換
し、その後前記高融点はんだの溶融温度で前記高融点は
んだを加熱溶融するとともに前記ベアチップ型半導体装
置を加圧して前記ベアチップ型半導体装置を前記配線基
板上の搭載パッドに本接続することを特徴とするベアチ
ップ型半導体装置の実装方法。
1. A three-layer bump having a high melting point solder layer, a core layer and a low melting point solder layer is formed on an electrode portion of a bare chip type semiconductor device, and then the bare chip type semiconductor device is mounted on a wiring board. Next, the low melting point solder is heated and melted at the melting temperature of the low melting point solder to be temporarily connected to the mounting pad on the wiring board, and in this state, the bare chip type semiconductor device is inspected and if there is a defective product, Replacing with a non-defective product, and then heating and melting the high melting point solder at the melting temperature of the high melting point solder and pressurizing the bare chip type semiconductor device to permanently connect the bare chip type semiconductor device to a mounting pad on the wiring board. A method for mounting a bare chip type semiconductor device, comprising:
【請求項2】 ベアチップ型の半導体装置の電極部に高
融点はんだ層とコア層と低融点はんだ層とを有する三層
バンプを形成した後、前記ベアチップ型半導体装置を電
気的選別治具上に搭載し、次いで前記低融点はんだの溶
融温度で前記低融点はんだを加熱溶融して前記電気的選
別治具の搭載パッドに仮接続し、この状態で前記ベアチ
ップ型半導体装置の検査を行い、その後前記低融点はん
だの溶融温度で前記低融点はんだを再加熱溶融して前記
ベアチップ型半導体装置を前記電気的選別治具から取り
外し、良品として選別された前記ベアチップ型半導体装
置のみを配線基板の搭載パッドに搭載して前記高融点は
んだの溶融温度で前記高融点はんだを加熱溶融するとと
もに前記ベアチップ型半導体装置を加圧して前記ベアチ
ップ型半導体装置を前記配線基板の搭載パッドに本接続
することを特徴とするベアチップ型半導体装置の実装方
法。
2. After forming a three-layer bump having a high melting point solder layer, a core layer and a low melting point solder layer on an electrode portion of a bare chip type semiconductor device, the bare chip type semiconductor device is placed on an electrical sorting jig. After mounting, the low melting point solder is heated and melted at the melting temperature of the low melting point solder to be temporarily connected to the mounting pad of the electrical sorting jig, and in this state, the bare chip type semiconductor device is inspected, and then the Re-melt the low melting point solder at the melting temperature of the low melting point solder and remove the bare chip type semiconductor device from the electrical sorting jig, and only the bare chip type semiconductor device selected as a good product is mounted on the wiring board mounting pad. The bare chip type semiconductor device is mounted by pressing the bare chip type semiconductor device while heating and melting the high melting point solder at the melting temperature of the high melting point solder. A method of mounting a bare chip type semiconductor device, comprising: making a main connection to a mounting pad of the wiring board.
【請求項3】 ベアチップ型半導体装置の電極部に高融
点はんだ層とコア層とを有する二層バンプを形成すると
ともに配線基板の搭載パッド上に低融点はんだ層を形成
した後、前記ベアチップ型半導体装置を配線基板上に搭
載し、次いで前記低融点はんだの溶融温度で前記低融点
はんだを加熱溶融して前記配線基板上の搭載パッド上の
前記低融点はんだ層に仮接続し、この状態で検査を行い
不良品があった場合は良品と交換し、その後前記高融点
はんだの溶融温度で加熱溶融するとともに前記ベアチッ
プ型半導体装置を加圧し、前記ベアチップ型半導体装置
を前記配線基板上の搭載パッドに本接続することを特徴
とするベアチップ型半導体装置の実装方法。
3. A bare chip type semiconductor device, wherein a two-layer bump having a high melting point solder layer and a core layer is formed on an electrode portion of the bare chip type semiconductor device, and a low melting point solder layer is formed on a mounting pad of a wiring board, and then the bare chip type semiconductor device is formed. The device is mounted on a wiring board, then the low melting point solder is heated and melted at the melting temperature of the low melting point solder, and temporarily connected to the low melting point solder layer on the mounting pad on the wiring board, and in this state, inspection is performed. If there is a defective product, replace it with a non-defective product, then heat and melt at the melting temperature of the high melting point solder and pressurize the bare chip type semiconductor device, and mount the bare chip type semiconductor device on a mounting pad on the wiring board. A method for mounting a bare chip type semiconductor device, characterized in that the main connection is performed.
【請求項4】 ベアチップ型半導体装置の電極部に高融
点はんだ層とコア層とを有する二層バンプを形成すると
ともに電気的選別治具の搭載パッドと配線基板の搭載パ
ッド上に低融点はんだ層を形成した後、前記ベアチップ
型半導体装置を前記電気的選別治具上に搭載し、次いで
前記低融点はんだの溶融温度で低融点はんだを加熱溶融
して前記電気的選別治具の搭載パッドに仮接続し、この
状態で検査を行い、その後前記低融点はんだの溶融温度
で加熱溶融して前記ベアチップ型半導体装置を前記電気
的選別治具から取り外し、良品として選別された前記ベ
アチップ型半導体装置のみを前記配線基板に搭載して前
記高融点はんだの溶融温度で前記高融点はんだを加熱溶
融するとともに前記ベアチップ型半導体装置を加圧して
前記ベアチップ型半導体装置を前記配線基板の搭載パッ
ドに本接続することを特徴とするベアチップ型半導体装
置の実装方法。
4. A two-layer bump having a high melting point solder layer and a core layer is formed on an electrode portion of a bare chip type semiconductor device, and a low melting point solder layer is formed on a mounting pad of an electrical selection jig and a mounting pad of a wiring board. After forming the above, the bare chip type semiconductor device is mounted on the electrical sorting jig, and then the low melting point solder is heated and melted at the melting temperature of the low melting point solder to temporarily mount it on the mounting pad of the electrical sorting jig. Connect, inspect in this state, then remove the bare chip type semiconductor device by heating and melting at the melting temperature of the low melting point solder from the electrical sorting jig, and only the bare chip type semiconductor device sorted as a good product The bare chip type semiconductor device is mounted on the wiring board to heat and melt the high melting point solder at the melting temperature of the high melting point solder, and pressurize the bare chip type semiconductor device. A method of mounting a bare chip type semiconductor device, characterized in that a conductor device is permanently connected to a mounting pad of the wiring board.
【請求項5】 前記三層バンプが、高融点はんだ層,コ
ア層,低融点はんだ層の順にメッキ法により形成される
請求項1,2記載のベアチップ型半導体装置の実装方
法。
5. The method of mounting a bare chip type semiconductor device according to claim 1, wherein said three-layer bump is formed by a plating method in the order of a high melting point solder layer, a core layer and a low melting point solder layer.
【請求項6】 前記三層バンプが、高融点はんだ層,コ
ア層,低融点はんだ層を有する3層箔材料を打ち抜いて
形成される請求項1,2記載のベアチップ型半導体装置
の実装方法。
6. The method of mounting a bare chip type semiconductor device according to claim 1, wherein the three-layer bump is formed by punching out a three-layer foil material having a high melting point solder layer, a core layer and a low melting point solder layer.
【請求項7】 前記二層バンプが、高融点はんだ層とコ
ア層の順にメッキ法により形成され、前記低融点はんだ
層がメッキ法により前記配線基板の搭載パッドに形成さ
れる請求項3,4記載のベアチップ型半導体装置の実装
方法。
7. The double-layer bump is formed by plating a high melting point solder layer and a core layer in this order, and the low melting point solder layer is formed on a mounting pad of the wiring board by a plating method. A method for mounting a bare chip type semiconductor device as described.
【請求項8】 前記二層バンプが、高融点はんだ層,コ
ア層を有する2層箔材料を打ち抜いて形成され、前記低
融点はんだ層がメッキ法により前記配線基板の搭載パッ
ドに形成される請求項3,4記載のベアチップ型半導体
装置の実装方法。
8. The two-layer bump is formed by stamping a two-layer foil material having a high melting point solder layer and a core layer, and the low melting point solder layer is formed on a mounting pad of the wiring board by a plating method. Item 4. A method of mounting a bare chip type semiconductor device according to items 3 and 4.
JP5450293A 1993-03-16 1993-03-16 Bare chip type semiconductor device mounting method Expired - Fee Related JPH0779116B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5450293A JPH0779116B2 (en) 1993-03-16 1993-03-16 Bare chip type semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5450293A JPH0779116B2 (en) 1993-03-16 1993-03-16 Bare chip type semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JPH06268017A true JPH06268017A (en) 1994-09-22
JPH0779116B2 JPH0779116B2 (en) 1995-08-23

Family

ID=12972412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5450293A Expired - Fee Related JPH0779116B2 (en) 1993-03-16 1993-03-16 Bare chip type semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JPH0779116B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19653499B4 (en) * 1995-12-25 2010-04-29 Mitsubishi Denki K.K. Lotzuführgerät and Lotzuführverfahren
JP2014183100A (en) * 2013-03-18 2014-09-29 Fujitsu Ltd Method for joining electronic components and electronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19653499B4 (en) * 1995-12-25 2010-04-29 Mitsubishi Denki K.K. Lotzuführgerät and Lotzuführverfahren
JP2014183100A (en) * 2013-03-18 2014-09-29 Fujitsu Ltd Method for joining electronic components and electronic device

Also Published As

Publication number Publication date
JPH0779116B2 (en) 1995-08-23

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