JPH06261337A - Digital signal processing circuit and inter-frame arithmetic circuit - Google Patents

Abstract

PURPOSE:To reduce the storage capacity of a memory for obtaining a frame delay signal by storing a digital signal whose lower bit is eliminated. CONSTITUTION:A decoding television signal converted into the digital signal is supplied to a bit elimination circuit 32 and an adder 34 through an input terminal 31. The bit elimination circuit 32 eliminates the lowest bit of a signal quantized by eight quantization bits, for example, and outputs highest seven bits to a frame memory 33. The frame memory 33 delays the decoding television signal of seven bits by one frame period and outputs it to an adder 34. The adder 34 adds the signal of eight bits at present time, which is inputted from the input terminal 31, with the output of the frame memory 33 being the signal of highest seven bits, which is prior by one frame period, by corresponding bits, and outputs an obtained two-fold Y signal to a coefficient unit 35. The coefficient unit 35 decreases the Y signal inputted from the adder 34 by 1/2, and outputs it to a mixer through an output terminal 36 as a still picture Y signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit and an interframe arithmetic circuit for adding and subtracting a digital signal delayed for a predetermined period and a digital signal before delay.

[0002]

2. Description of the Related Art In recent years, television receivers have been developed which convert television signals into digital signals and perform digital signal processing. By converting a television signal into a digital signal and performing digital signal processing in this way,
Three-dimensional Y / C separation using a digital memory can be performed, and highly accurate Y / C separation characteristics can be obtained. An example of such a conventional digital Y / C division circuit will be described below with reference to FIGS.

FIG. 2 is a diagram showing the configuration of a conventional digital Y / C division circuit. In FIG. 2, the decoded television signal is supplied to the A / D converter 2 via the input terminal 1.
The A / D converter 2 converts the input decoded television signal into a digital signal and outputs it to the inter-frame Y / C separator 3, the intra-field Y / C separator 4, the motion detector 5 and the subtractor 7. To do.

The inter-frame Y / C separator 3 extracts a still picture Y signal, which is a Y signal used during still picture, by adding the decoded television signal of one frame before stored in the inter-frame Y / C separator 3 and mixing them. Output to the container 6. Y in the field
The / C separator 4 extracts the moving picture Y signal, which is the Y signal used for the moving picture, by adding it to the decoded television signals of one line before and after stored inside, and outputs it to the mixer 6. The motion detector 5 detects the motion of the input decoded television signal by a method generally used in the past,
A motion detection signal corresponding to this motion is output to the mixer 6.

The mixer 6 mixes the input moving image Y signal and still image Y signal at a ratio according to the motion detection signal, and the mixed Y signal is subtracted as a three-dimensional Y / C separated Y signal. 7 and D / A converter 10. The mixer 6 increases the ratio of moving images when the motion of the decoded television signal is large, and increases the ratio of still images when the motion of the decoded television signal is small.

The subtractor 7 subtracts the three-dimensional Y / C separated Y signal, which is the output of the mixer 6, from the digitized decoded television signal to perform color demodulation as a three-dimensional Y / C separated C signal. Output to the circuit 8. The color demodulation circuit 8 demodulates the input C signal and outputs it to the D / A converter 9. D / A
The converter 9 converts the demodulated C signal into an analog signal and outputs it to the output terminal 11. The D / A converter 10 converts the three-dimensional Y / C separated Y signal, which is the output signal of the mixer 6, into an analog signal and outputs the analog signal to the output terminal 12.

Next, the inter-frame Y / C separator 3 of FIG. 2 will be described in more detail with reference to FIG. In FIG. 3, the output of the A / D converter 2 is supplied to the frame memory 22 and the adder 23 via the input terminal 21. The frame memory 22 is a memory that can store a decoded television signal converted into a digital signal for one frame, and delays the input decoded television signal for one frame period and outputs the delayed decoded television signal to the adder 23. The adder 23 adds 1 to the current decoded television signal input from the input terminal 21.
The output of the frame memory 22, which is the decoded television signal before the frame period, is added, and the obtained Y signal of twice the magnitude is output to the coefficient unit 24. The coefficient unit 24 halves the Y signal of twice the size input from the adder 23 and outputs it as a still image Y signal to the mixer 6 via the output end 25.

The capacity of the frame memory 22 is A / D
When the quantized bits of the digital signal output from the converter 2 are 8 bits, 525 lines × 910 pixels × 8 bits = 3,822,000 bits. As described above, since a memory of about 4 Mbits is required, there is a problem that the circuit scale becomes large.

[0009]

As described above, in the conventional three-dimensional Y / C separation circuit, a memory of at least about 4 Mbits is required to obtain the frame delay signal, and the circuit scale becomes large. was there. It is an object of the present invention to eliminate the above-mentioned drawbacks of the prior art and reduce the memory for obtaining the frame delay signal.

[0010]

In order to achieve the above object, in the present invention, the number of quantization bits M (M>
1) The input terminal to which the digital signal is input, the storage means for storing for a predetermined period except at least one bit belonging to the lower side of the digital signal, and the digital signal and the output of the storage means are added (or And a calculation means for performing subtraction).

In addition, the input terminal to which the television signal is input and the number of quantization bits M (M> M) for the television signal.
1) A / D converter for converting into a digital signal and outputting a digital television signal; storage means for storing for a predetermined period excluding at least one lower bit of the digital television signal; There is provided an interframe arithmetic circuit including an arithmetic means for adding (or subtracting) a television signal and an output of the storage means. Further, the storage means provides the inter-frame arithmetic circuit characterized by storing only a least significant bit for a predetermined period. Further, the storage means provides the inter-frame arithmetic circuit characterized by storing for one horizontal scanning period or an integral multiple of one field period.

[0012]

With the above-mentioned structure, a digital signal having a quantization bit number M (M> 1) is input to the input end. The storage means stores the digital signal for a predetermined period except at least one bit belonging to the lower side. Since the arithmetic means adds the digital signal supplied to the input end and the output of the storage means and outputs the result, the storage capacity of the storage means can be reduced.

In such a configuration, a television signal is input to the input terminal, and this television signal is converted into a digital television signal by the A / D converter. This digital television signal is stored by the storage means except at least one bit belonging to the lower side. The output of the storage means and the output of the A / D converter are subjected to addition or subtraction calculation by the calculation means.

[0014]

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 and 2. The structure of the three-dimensional Y / C separation circuit of this embodiment is the same as that of FIG.

FIG. 1 is a diagram showing a configuration in which a digital signal processing circuit according to an embodiment of the present invention is used in the inter-frame Y / C separation circuit 3 of FIG. It is assumed that the quantized bits of this digitally converted decoded television signal are 8 bits.

In FIG. 1, the decoded television signal converted into a digital signal is supplied to a bit reduction circuit 32 and an adder 34 via an input terminal 31. The bit reduction circuit 32 deletes the least significant bit of the signal quantized with 8 quantized bits and outputs the upper 7 bits to the frame memory 33. The frame memory 33 delays the 7-bit decoded television signal for one frame period and adds the adder 3
Output to 4. The adder 34 adds the current 8-bit decoded television signal input from the input terminal 31 and the output of the frame memory 33, which is a high-order 7-bit decoded television signal one frame period before, with corresponding bits. Then, the obtained Y signal of about twice the magnitude is applied to the coefficient unit 35.
Output to. The coefficient unit 35 halves the Y signal of about twice the size input from the adder 34, and outputs it as a still image Y signal to the mixer 6 via the output end 36.

Since the least significant bit is reduced in the output of the frame memory 33 of this embodiment, an error corresponding to the least significant bit occurs at the maximum. However, since the frame addition is performed with 8 bits including the least significant bit, the error is half the error of the least significant bit. If there is an error of this degree, there is no problem since it has almost no effect on the image quality.

With respect to the capacity of the frame memory 33, since the bits output from the bit reduction circuit 32 are the higher 7 bits, 525 lines × 910 pixels × 7 bits = 3.
It becomes 344,250 bits, and can be reduced to 7/8. As a result, the circuit scale of the memory can be reduced without deterioration of image quality.

Further, in this embodiment, the bit reduction circuit 32 is used.
Has reduced only the least significant bit, but if the image quality may deteriorate slightly, not only the least significant bit but also the least significant bit and this one higher bit may be reduced, or further reduced. good.

In this embodiment, the Y / C separator 3 between frames is applied, but the Y / C separator 4 in the field is also applied to a memory for storing decoded television signals of about one line. Is also good. Further, in this embodiment, it is used as a Y / C separator, but it may be used as a noise eliminator that performs addition and subtraction with a signal delayed for a predetermined period such as between frames.

[0021]

According to the present invention, since the digital signal in which the lower bits of the digital signal are deleted is stored in the memory,
The capacity of the memory used for delay can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a digital signal processing circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of a conventional digital and Y / C separation circuit according to the present invention.

FIG. 3 is a diagram showing a configuration of a conventional inter-frame Y / C separation separator.

[Explanation of symbols]

31 ... Input end, 32 ... Bit reduction circuit, 33 ... Frame memory, 34 ... Adder, 35 ... Coefficient multiplier, 36 ... Output end.

Claims (4)

[Claims] 1. An input terminal to which a digital signal having a quantization bit number M (M> 1) is input, storage means for storing for a predetermined period except at least one bit belonging to the lower side of the digital signal, A digital signal processing circuit comprising: an arithmetic means for adding (or subtracting) a digital signal and an output of the storage means. 2. An input terminal to which a television signal is input, and an A / D converter which converts the television signal into a digital signal with a quantization bit number M (M> 1) and outputs a digital television signal. Storage means for storing a predetermined period except for at least one bit belonging to at least the lower side of the digital television signal, and operation means for adding (or subtracting) the digital television signal and the output of the storage means. An interframe arithmetic circuit characterized by being provided. 3. The inter-frame arithmetic circuit according to claim 2, wherein the storage means stores only a least significant bit for a predetermined period. 4. The interframe arithmetic circuit according to claim 2, wherein the storage means stores a period which is an integral multiple of one horizontal scanning period or one field period.