JPH0759087A - Picture signal receiver - Google Patents

Abstract

PURPOSE:To obtain an excellent picture by controlling a median filter provided to a decoder output section in response to a decoded signal component. CONSTITUTION:A picture signal received by a terminal 300 is outputted in a form of a signal in matching a decoding rate of a variable length decoding circuit 302 at a reception buffer 301. The circuit 302 applies variable length decoding to the input signal in matching that of a sender side and inputs the result to an inverse quantization circuit 303. The circuit 303 quantizes the input signal and an inverse DCT circuit 304 applies inverse DCT processing. The inverse DCT signal is inputted to an adder circuit 305. Its output is converted into a raster scanning signal at a block raster conversion circuit 309. The transformed output is inputted to a median filter 310 and a selector 311. Input data occupancy information of the broadcast 301 is inputted to a median on/off control circuit 311 via a delay circuit 312. When the occupancy rate of data exceeds a set value in the circuit 313, the selector 310 selects an output of the filter 310 to reduce mosquito noise.

Description

Detailed Description of the Invention

[0001]

This invention relates to interframe prediction, D
The present invention relates to an image signal receiver that receives and decodes a coded signal that has been digitally coded using CT (discrete cosine transform) processing or the like.

[0002]

2. Description of the Related Art In recent years, with the widespread use of television broadcasting and the rapid development of Japanese high-definition technology, AT, which is the next-generation TV system centered on terrestrial broadcasters in the United States
V has been developed. In 1987, the FCC (Federal Communications Commission of the United States) established an advisory committee, publicly invited the ATV transmission method from each group inside and outside the country, and conducted comparative experiments on the proposed method such as image quality and propagation. Then, the method of deciding the method is clarified. In this situation, ATVs in the United States are dominated by digital transmission methods.

Generally, when a video signal is digitized, the amount of information thereof becomes enormous, and it is expected that it will be quite difficult to directly transmit the information through a transmission path or store it in a recording medium.
For example, the current overall data rate of 525, 2: 1 interlaced signals is 216 Mbps, 525,
With a 1: 1 non-interlaced signal, it becomes 432 Mbps.

Therefore, the image compression technique is indispensable, but the image signal is encoded using a combination of DCT processing, interframe predictive coding, run length coding, and entropy coding from various image compression technology items. As a technology to
There is a CCITT H261 model used for video conferences and the like, and a digital transmission TV system has been proposed based on this technology.

FIG. 10 shows a block diagram of a general model encoder of CCITT H261. A raster scanning video signal is input to the video input terminal 100, and the raster block conversion circuit 101 outputs 8 × 8 signals that are input in raster in the horizontal and vertical directions.
Block conversion of pixels (hereinafter referred to as DCT blocks) is performed. The converted video signal is input to the difference circuit 102 and the motion vector detection circuit 109. The motion vector detection circuit 109 simultaneously receives the current signal input from the raster block conversion circuit 101 and the signal delayed by one frame from the frame memory 108, and based on the signal, the DCT block unit or 16 × 16 pixels (hereinafter An image motion vector in units of macro blocks) is detected. This motion vector is transmitted to the motion correction circuit 110. The motion correction circuit 110 motion-corrects the output of the frame memory 108 according to the motion vector, and supplies the output to the difference circuit 102 and the addition circuit 107. Here, the switch 111 is turned off by a determination circuit (not shown) when the difference value (total of 8 × 8 pixels) between the current signal and the signal delayed by one frame is larger than the threshold value. As a result, the difference circuit 102 No signal is sent to the adder circuit 107. The switch 111 is turned off at the time of a fast-moving image or a scene change, and at the time of performing signal processing which does not perform the frame difference necessary for reproducing the image on the receiver side. This mode is generally called intra mode. On the contrary, when the switch 111 is turned on, the difference circuit 102 performs the frame difference process, and the addition circuit 107 performs the frame addition process. This mode is generally called an inter mode. Intra /
The interprocessed output of the difference circuit 102 is sent to the DCT circuit 103. The DCT circuit 103 performs DCT processing on the transmitted signal in DCT block units, and sends it to the quantization circuit 104. The quantization circuit 104 quantizes the input DCT coefficient based on the quantization table given from the quantization table selection circuit 114, and sends the output to the variable length coding circuit 112. This signal is generally a run length code and a level signal.

On the other hand, the output of the quantizing circuit 104 is input to the inverse quantizing circuit 105, where it is inversely quantized and converted into a signal almost the same as the input signal of the quantizing circuit 104. Further, the output signal of the inverse quantization circuit 105 is the inverse DCT circuit 1
The signal is input to the input signal 06, subjected to inverse DCT processing, and converted into a signal substantially equal to the input signal of the DCT circuit 103. The reason why they are almost equal is that they include a quantization error.
Next, in the adder circuit 107, the output signal of the inverse DCT circuit 106 and the signal delayed by one frame (in the inter mode) are added, and the added output is added to the frame memory 108.
To enter. When in intra mode, switch 111
Is turned off, the output of the inverse DCT circuit 106 is directly input to the frame memory 108 via the adder circuit 107. The output signal of the adder circuit 107 is generally a local decoder output.

The signal input to the variable length coding circuit 112 is subjected to variable length coding processing using a Huffman table or the like. The variable-length coded signal is input to the transmission buffer 113. The transmission buffer 113 is for temporarily holding the data because the data amount changes depending on the content of the image to be encoded, and for transmitting the signal from the output terminal 115 at a constant rate. For this reason, the variable-length coded signal in the transmission buffer 113 becomes extremely small, and the data occupation amount of the buffer becomes 0%. Conversely, the number of input signals becomes extremely large and the data occupation amount becomes 100%. Is being prevented. Therefore, the data occupation amount of the buffer is constantly monitored by the quantization table selection circuit 114. When the data occupation amount decreases, the quantization table selection circuit 114 selects the table in the quantization circuit 104 to increase the number of quantization bits to increase the data amount input to the transmission buffer 113, and conversely, when the data occupation amount increases. , The transmission buffer 113 with a reduced number of quantization bits
The amount of data input to is reduced. This allows the output data from the transmission buffer 113 to maintain a constant rate.

FIG. 11 shows a block diagram of a decoder corresponding to the above encoder. Video input terminal 200
A variable-length coded signal is input to. The reception buffer 201 outputs a signal in accordance with the rate at which the variable-length coded signal is decoded by the variable-length decoding circuit 202. The variable length decoding circuit 202 performs variable length decoding matching the transmitting side. The variable-length decoded signal is input to the inverse quantization circuit 203 and inversely quantized,
The inversely quantized signal is input to the inverse DCT circuit 204 and subjected to inverse DCT processing. The output of the inverse DCT circuit 204 is supplied to the adding circuit 205. In the adder circuit 205, in the inter mode, the signal obtained from the inverse DCT circuit 204 and the signal frame-delayed by the frame memory 206 and motion-corrected by the motion correction circuit 207 are added. In the intra mode, switch 2
08 is turned off and the signal delayed by one frame is added to the adder circuit 2
Not entered in 05. The switch 208 is switched by an inter / intra switching signal obtained from the variable length decoding circuit 202. The output of the adder circuit 205 is
After being converted into a raster scanning signal by the block raster conversion circuit 209, it is sent to the video signal output terminal 210 as a decoder output.

Although the encoder / decoder of the H261 model has been described above, since the coded signal is transmitted at a fixed rate in this model, the more complicated the content of the video signal, the more bits allocated per pixel. Will decrease, and mosquito noise etc. will increase. Further, when the superimposed image is quantized, since the supermarket has high frequency components, a lot of mosquito noise tends to occur around the supermarket. In order to eliminate these image quality deteriorations, it is conceivable to increase the transmission rate or to encode using a horizontal and vertical low-pass filter and remove the horizontal and vertical high frequency components before encoding.

[0010]

As described above, in the conventional apparatus, when a video signal or a superposed signal is quantized with a small number of bits, mosquito noise due to insufficient number of quantized bits, etc. Is increasing.

Therefore, an object of the present invention is to provide an image signal receiving apparatus capable of reducing mosquito noise and the like only on the decoder side without changing the configuration of the encoder.

[0012]

According to the present invention, a median filter is provided at an output part of a decoder, and means for performing on / off control of the median filter according to a component of a signal to be decoded is provided.

[0013]

By the above means, when a video signal or a signal obtained by quantizing a superimposed signal with a small number of bits arrives, the median filter acts to effectively reduce mosquito noise.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. A variable-length coded signal is input to the video input terminal 300 and introduced into the reception buffer 301. Receive buffer 301
Outputs the variable-length coded signal into a signal that matches the rate of decoding by the variable-length decoding circuit 302 in the next stage, and supplies the signal to the variable-length decoding circuit 302. The variable length decoding circuit 302 performs variable length decoding matching the transmitting side. The variable-length decoded signal is input to the inverse quantization circuit 303. The inverse quantization circuit 303 inversely quantizes the input signal, and the output thereof is the inverse DCT circuit 30.
4 is input. The inverse DCT circuit 304 performs inverse DCT processing on the input signal. The inverse DCT processed signal is
It is input to the adder circuit 305. In the inter mode, the adder circuit 305 adds the signal from the inverse DCT circuit 304 and the signal whose frame has been delayed by the frame memory 306 and whose image motion has been corrected by the motion correction circuit 307. In the intra mode, the motion correction circuit 30
Since the switch 308 provided between the No. 7 and the adder circuit 305 is turned off, the signals delayed by one frame are not added.

The switch 308 is a variable length decoding circuit 30.
The switching is controlled by the inter / intra switching signal obtained from 2. The output of the adder circuit 305 is supplied to the frame memory 306 and also to the block raster conversion circuit 309. Here, the pixel block is converted into a raster scan signal, and the conversion output is
It is supplied to the median filter 310 and the selector 311. The configuration of the median filter 310 is shown in FIGS.
Will be explained. Also, the block raster conversion circuit 30
A delay circuit for compensating for the delay of the median filter 310 is provided on the line in which the output of 9 is directly input to the selector 311, but it is not shown. The output of the median filter 310 is input to the selector 311. The signal selected by the selector 311 is output to the video signal output terminal 314 as a decoder output.

The input selection operation of the selector 311 is performed as follows. The input data occupation information of the reception buffer 301 is input to the median on / off control circuit 313 via the delay circuit 312. The delay circuit 312 includes a variable length decoding circuit 302, an inverse quantization circuit 303, an inverse DCT circuit 304, an addition circuit 305, and a block raster conversion circuit 30.
9 and the delay amount of the median filter 309. Median on / off control circuit 31
The control unit 3 controls the selector 311 to select the output of the median filter 310 when the data occupancy rate of the reception buffer 301 exceeds the set threshold value. To the median on / off control circuit 313, for example, the data itself of the reception buffer 301 is input as the input data occupation information.

From this, the following can be said. That is, the fact that the data occupancy rate of the reception buffer 301 is large means that data having a small number of quantization bits per pixel has been sent or data having many high frequency components has been sent. However, the small number of quantization bits per pixel means that mosquito noise may occur in the decoded output. Therefore, in this system, the decoded output is passed through the median filter 310 to be taken out, so that the final output from which mosquito noise is removed can be surely obtained.

FIG. 2 shows the configuration of a median filter using 3 pixels in the horizontal direction. The signal supplied to the input terminal 400 is the latch circuit 401 and the maximum value detection circuit 4
03, 405, and the output of the latch circuit 401 is
It is input to the latch circuit 402 and the maximum value detection circuits 403 and 404, and the output of the latch circuit 402 is the maximum value detection circuit 4
04 and 405 are input. Maximum value detection circuits 403-4
In 05, the larger of the two input signals is detected and supplied to the minimum value detection circuit 406. The minimum value detection circuit 406 detects the minimum value of the input signal, and this output becomes the output of the median filter.

FIG. 3 shows the configuration of a median filter using 5 pixels in the horizontal direction. The signal of the input terminal 410 is input to the latch circuit 411, the maximum value detection circuit 415, the minimum value detection circuit 416, and the selector circuit 418, and the output of the latch circuit 411 is the latch circuit 412, the maximum value detection circuit 415, and the minimum value detection circuit 415. The output of the latch circuit 412 is input to the circuit 416 and the selectors 418 and 419, and the output of the latch circuit 413 is input to the latch circuit 413 and the maximum value detection circuit 415 and the minimum value detection circuit 416 and the selectors 418, 419, and 420, and the output of the latch circuit 413 is latched. Circuit 414
And the maximum value detection circuit 415, the minimum value detection circuit 416 and the selector 420, and the output of the latch circuit 414 is input to the maximum value detection circuit 415, the minimum value detection circuit 416 and the selectors 419 and 420. That is, the input signal and the outputs of the latch circuits 411 to 414 become the input data of 5 pixels of the median filter.

In the maximum value detection circuit 415, the input 5
The maximum one is detected from the pixel data, and the system of the input signal of this data is output by 3 bits (000 to 100). Similarly, the minimum value detection circuit 416 outputs the data of the input 5 pixels. The minimum value is detected and the input signal of this system is output by 3 bits (000 to 100). The maximum value detection circuit 415 and the minimum value detection circuit 416 output the maximum value from the input results. A selection signal for selecting three systems of signals excluding the system of the value and the minimum value is output to the selectors 418 to 420.

The data selection circuit 417 is composed of a ROM or the like and has a conversion table as shown in FIG. The selector 418 receives the data obtained from the input terminal 410 and the outputs of the latch circuits 411 and 412, and the selector 419 receives the latch circuits 411, 412 and 41.
3 is input, and the outputs of the latch circuits 412, 413, and 414 are input to the selector 420, and the outputs are derived by being controlled by the selector control signals shown in FIG.

The signal obtained from the selector 418 is input to the maximum value detection circuits 421 and 422, and the selector 419.
From the selector 420 are input to the maximum value detection circuits 421 and 423, and the signals obtained from the selector 420 are input to the maximum value detection circuits 422 and 423, and the maximum values are detected. The output signals of the maximum value detection circuits 421 to 423 are input to the minimum value detection circuit 424, and the minimum value one is obtained at the output terminal 435. The output of the output terminal 425 becomes the output of the median filter.

FIG. 5A shows a block diagram of a median filter having a total of 5 pixels in the horizontal and vertical directions. The circuit operation is almost the same as that of FIG. 3, except that the memory circuits 431 and 434 of which the respective capacitances of the latch circuits 411 and 414 of FIG. 3 are (the number of pixels of line-1).
It has only been replaced by. That is, by arranging the line memory circuits 431 and 434, it is possible to configure a median filter of horizontal and vertical 5 pixels as shown in FIG. Since the other parts are the same as those in the circuit of FIG. 3, the same reference numerals as those in FIG. In addition, although a median filter having 9 pixels in the horizontal and vertical directions (not shown) and the like can be considered, any one of them is arranged in the median filter 310.

FIG. 6 is a block diagram of a decoder according to the second embodiment of the present invention. The same parts as those in the embodiment of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the case of the second embodiment, the median filter ON / OFF control circuit 313 monitors the table of the dequantized signal decoded by the variable length decoding circuit 302 as the control signal for controlling the selector 311. The median filter on / off control circuit 313 causes the selector 311 to select the output of the median filter 310 only when the inverse quantization table has a bit number smaller than the set threshold value.

Median filter on / off control circuit 3
The selector switching timing obtained from 13 is DC
Since it is in units of T blocks, it is converted into a raster by the block raster conversion circuit 514, and the median filter is turned on / off at the timing matching the DCT block of the image.
Off is controlled. In this case, although the number of bits of the quantization table is small, specifically, a certain range is set to effectively operate the filter action. Further, in the above description, ON / OFF control of the median filter is performed by referring to the number of bits in the quantization table, but in addition to this, inter / intra information obtained from the variable length coding circuit 302, It may be controlled according to the presence / absence of motion correction and the degree of motion correction.

FIG. 7 is a block diagram of a decoder according to the third embodiment of the present invention. The same parts as those in the embodiment of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the case of this embodiment, the output of the adder circuit 305 is input to the DCT block internal edge detection circuit 501, and the output of the DCT block internal edge detection circuit 501 is input to the median on / off control circuit 502. DCT block edge detection circuit 501 and median on / off control circuit 502
Is a median filter when the absolute value of the difference between vertically and diagonally adjacent pixels is obtained using the DCT block (8 × 8 pixels: 16 pixels in total) and the magnitude exceeds a set threshold value. A control signal for taking out the output of 310 is obtained. Median on / off control circuit 50
In No. 2, timing control is also performed so that the output of the median filter 310 is switched and derived for each DCT block. In the block raster conversion circuit 503, the control signal obtained in block units from the median on / off control circuit 502 is supplied to the selector 31 in accordance with the video signal.
It is adjusted so as to be given to 1 as a switching signal.

FIG. 8A shows a specific example of the DCT block edge detection circuit 501. Input terminal 6
The signal input to 50 is input to the latch circuit 651 and the subtraction circuits 655 to 658. The output of the latch circuit 651 is supplied to the 6-clock delay circuit 652 and the subtraction circuit 655, and the output of the 6-clock delay circuit 652 is supplied to the latch circuit 653 and the subtraction circuit 656, and the latch circuit 653.
Is supplied to the latch circuit 654 and the subtraction circuit 657, and the output of the latch circuit 654 is supplied to the subtraction circuit 658. The outputs of the subtraction circuits 655 to 658 are input to the maximum value extraction circuit 659. The output of the maximum value extraction circuit 659 is input to the hold circuit 661 and the maximum value detection circuit 660. The maximum value detection circuit 660 includes a hold circuit 661.
The data on the input side and the data on the output side are compared, and the hold circuit 611 is controlled so that the hold data of the hold circuit 661 is replaced only when the value of the data on the input side is large. The data held in the hold circuit 611 appears at the output terminal 662.

The latch circuits 651, 653, 654 have a delay amount of one clock. In this circuit, the subtraction circuits 655 to 658 take the difference between horizontally, vertically, and diagonally adjacent pixels with respect to the input signal. FIG. 8B shows the concept. Black circle is input terminal 6
There are 50 data. In this calculation process, FIG.
In the black portion of (C), the data of the white circle portion of FIG. 8B is out of the DCT block, and the data of that portion is not input to the maximum value extraction circuit 659, although not shown here. It has become.

An edge in the DCT block is detected by the circuit as described above. And a big edge (high frequency)
And the level exceeds the set value,
The median filter will work and you will get noise reduction.

FIG. 9 is a block diagram of a decoder according to the fourth embodiment of the present invention. The same parts as those in the embodiment of FIG. 7 are designated by the same reference numerals and the description thereof will be omitted. In the case of this embodiment, the output of the addition circuit 305 is input to the minimum / maximum difference detection circuit 510 in the DCT block. This DC
The detection output of the minimum / maximum difference detection circuit 510 in the T block is input to the median on / off control circuit 502. The other parts are the same as in the previous embodiment. In this embodiment, the minimum / maximum difference detection circuit 51 in the DCT block is
At 0, the data of the minimum value and the maximum value is detected using the DCT block (8 × 8 pixels: 16 pixels in total), and when the difference exceeds the set threshold value, the output of the median filter 310 A control signal for selectively deriving is generated.

[0031]

As described above, according to the present invention, the case where an image having a small number of quantization bits or an image including abrupt edges is sent is detected, and the decoded output image is filtered by the median filter. Like this
It is possible to reduce mosquito noise and obtain a good image.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of the median filter of FIG.

FIG. 3 is a diagram showing another example of the median filter of FIG.

FIG. 4 is a diagram showing an example of a conversion table of the data selection circuit of FIG.

5 is a diagram showing still another example of the median filter of FIG. 1. FIG.

FIG. 6 is a diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram showing a third embodiment of the present invention.

8A and 8B are diagrams showing a specific example of the DCT block edge detection circuit of FIG. 7 and a diagram for explaining the operation thereof.

FIG. 9 is a diagram showing a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a conventional image compression encoder.

FIG. 11 is a diagram showing a conventional decoder.

[Explanation of symbols]

301 ... Reception buffer, 302 ... Variable length decoding circuit, 3
03 ... Inverse quantization circuit, 304 ... Inverse DCT circuit, 305 ...
Addition circuit, 306 ... Frame memory, 307 ... Motion correction circuit, 308 ... Switch, 309 ... Block raster conversion circuit, 310 ... Median filter, 311 ... Selector, 312 ... Delay circuit, 313 ... Median on / off control circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03M 7/30 A 8522-5J 9191-5L G06F 15/68 400 A

Claims (4)

[Claims] 1. A discrete cosine transform (DCT) of an image signal.
In a decoding device that processes and decodes a quantized coded signal with varying number of bits and obtains a decoded output, is the data occupancy rate in the receiving buffer for fetching the coded signal larger than a set value? Detecting means for detecting whether or not, when the detecting means detects that the data occupancy in the receiving buffer is larger than a set value,
An image signal receiving apparatus, comprising: means for filtering the decoded output by a median filter to obtain a final decoded output. 2. A discrete cosine transform (DCT) of an image signal
In a decoding device that processes and decodes a quantized coded signal with varying number of bits, and obtains a decoded output, a dequantization unit that dequantizes the coded signal, and a dequantization unit A detection unit that detects whether or not the number of bits of the inverse quantization coefficient is larger than a set value, and the detection unit detects that the number of bits of the inverse quantization coefficient is smaller than the set value. An image signal receiving device, characterized in that it further comprises means for performing filtering by a median filter on the decoded output to obtain a final decoded output. 3. An image signal is subjected to a discrete cosine transform (DCT).
In a decoding device for processing and decoding a quantized coded signal with varying number of bits to obtain a decoded output, the coded signal is inversely quantized, then inverse DCT processing is performed, and then the inverse Using the DCT block at the stage in which the corresponding inverse DCT output of the previous frame is added to the DCT output, this DCT
Detecting means for detecting an edge in the block and detecting whether or not the edge is larger than a set threshold value; and the detecting means detects that the edge is larger than the set threshold value. And a means for filtering the decoded output with a median filter to obtain a final decoded output. 4. A discrete cosine transform (DCT) of an image signal
In a decoding device for processing and decoding a quantized coded signal with varying number of bits to obtain a decoded output, the coded signal is inversely quantized, then inverse DCT processing is performed, and then the inverse This DCT block is used by using the DCT block at the stage in which the corresponding inverse DCT output of the previous frame is added to the DCT output.
Detecting the maximum value and the minimum value in the block, detecting means for detecting whether the difference between the maximum value and the minimum value is larger than a set threshold value, and the detecting means sets the difference. An image signal receiving apparatus comprising: means for filtering the decoded output by a median filter to obtain a final decoded output when it is detected that the decoded output is larger than a threshold value.