JP2730066B2 - Motion detection signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a television receiver for performing image quality improvement processing such as motion adaptive scanning line interpolation such as an IDTV, and a 1-bit motion detection signal. The present invention relates to a processing circuit for converting a signal into a signal.

[Summary of the Invention]

According to the present invention, the reference level in the level comparison means for converting a motion detection signal into a 1-bit signal is controlled by a vertical edge detection means or a horizontal edge detection means, so that an appropriate signal conversion according to the image content is achieved. Is made.

[Conventional technology]

FIG. 3 shows a configuration of an example of a television receiver.

In the figure, the video signal from the input terminal (62)
After being converted to a digital signal by the D converter (63), Y / C
The luminance signal Y and the chrominance signal C are supplied to the separation circuit (64).
Is separated into

The luminance signal Y output from the Y / C separation circuit (64) is supplied to a scanning line interpolation circuit (65Y). Y / C separation circuit (64)
The output color signal C is supplied to a chroma decoder (66) and color-demodulated. The time-division signals RY / BY of the red difference signal RY and the blue difference signal BY output from the chroma decoder (66) are supplied to a scanning line interpolation circuit (65C). From the interpolation circuits (65Y) and (65C), in addition to the main scanning line signals Ym, Rm-Ym / Bm-Ym, the interpolation scanning line signals Yc, R
c−Yc / Bc−Yc are output simultaneously.

The luminance signal Y output from the Y / C separation circuit (64)
Is supplied to the motion detection circuit (50), and the motion detection signal from the motion detection circuit (50) is supplied to the level comparator (51). From the level comparator (51), when the motion detection signal is equal to or higher than the level of the reference level signal _Vth , the level is "1",
On the other hand, in the following, a low level "0" signal is output. That is, the motion detection signal is 1 by the level comparator (51).
It is converted to a bit signal.

The output signal of the level comparator (51) is supplied to a coefficient generator (52). Scan line interpolation circuit (65Y), (65C)
Is generated by this coefficient generator (52),
The value is changed according to the magnitude of the motion detection signal. For example, K is set to 0 in a still image portion, and the maximum value of K is set to 1.

The motion detection circuit (50) is configured as shown in FIG. In the figure, a luminance signal Y supplied from a Y / C separation circuit (64) is applied to a field memory (40) constituting a delay line.
It is supplied to the series circuit of 1) and (402). The delay time of the series circuit of the field memories (401) and (402) is
One frame (263H + 262H) is set.

The input signal of the field memory (401) and the output signal of the field memory (402) are supplied to a subtractor (403) and subtracted. The frame difference signal output from the subtracter (403) is subjected to a low-pass filter (404) to remove high-frequency noise components and dot interference components, and then converted to an absolute value by an absolute value circuit (405). This absolute value circuit (40
The output signal of 5) is used as a motion detection signal.

The detection of the motion from the frame difference signal as described above is described in, for example, Japanese Patent Application Laid-Open No. 55-8124.

The scanning line interpolation circuit (65Y) is configured as shown in FIG. In the figure, a luminance signal Y supplied from a Y / C separation circuit (64) is a line memory (60) constituting a delay line.
Supplied to 1). The input signal and output signal of the line memory (601) are supplied to an adder (602) and averaged. The output signal of the adder (602) is multiplied by K (K ≦ 1) by a coefficient unit (603). After that, it is supplied to the adder (604).

The luminance signal Y is supplied to a field memory (605) constituting a delay line. This field memory (605)
Is 263H. The output signal of the field memory (605) is supplied to the adder (604) after being multiplied by (1-K) by the coefficient unit (606).

FIG. 6 is a diagram showing a scanning line structure on the time-vertical plane, and the circles indicate scanning lines of each field. Assuming that the input signal is h, the output signal of the line memory (601) is i, and the output signal of the field memory (605) is j, these signals h to j have the positional relationship shown in FIG.

In the scanning line interpolation circuit (65Y), the output signal of the adder (602) Becomes the interpolation scanning line signal of the moving image portion, and the output signal j of the field memory (605) becomes the interpolation scanning line signal of the still image portion. Therefore, the adder (604) outputs an interpolated scanning line signal Yc in which the interpolated scanning line signals of the moving image portion and the still image portion are added at a ratio corresponding to the degree of motion.
The interpolation scanning line is shown in FIG. Position.

Further, the input signal h is used as it is as the main scanning line signal Ym.

Although the description is omitted, the scanning line interpolation circuit (65C) is similarly configured.

Main scanning line signals Ym, Rm-Ym / Bm-Ym and interpolation scanning line signals Yc, Rc output from the scanning line interpolation circuits (65Y) and (65C).
−Yc / Bc−Yc are time compression circuits (67Y) and (67C), respectively.
Supplied to In the time compression circuits (67Y) and (67C), the main scanning line signals Ym, Rm-Ym / Bm-Ym and the interpolation scanning line signals Y
c, Rc−Yc / Bc−Yc are each time-axis-compressed by 1/2, and are continuously output. In this case, the time compression circuit (76C)
Outputs a red color difference signal and a blue color difference signal separately.

The double-speed luminance signal and chrominance signal output from the time compression circuits (67Y) and (67C) are output from the D / A converter (68Y) and
(68R) and (68B) are analog signals.

The double-speed luminance signal and color difference signal output from the D / A converters (68Y), (68R), and (68B) are supplied to the matrix circuit (73). The double-speed red, green, and blue signals R, G, and B output from the matrix circuit (73) are supplied to a color picture tube (75) via amplifiers (74R), (74G), and (74B), respectively. In this color picture tube (75), a non-interlaced scanning display with twice the number of scanning lines is displayed.

[Problems to be solved by the invention]

In the example of FIG. 3, the motion detection signal is converted into a 1-bit signal by the level comparator (51), thereby suppressing noise below a certain level.

Conventionally, the reference level signal V in the level comparator (51)
_{The th} level is fixed. This reference level signal V _th
Is set to the maximum value of the frame difference signal in the still image source, for example, a detection error occurs on the still image (where a low-level “0” signal should be output as a still image,
Although a high-level "1" signal is not generated), there is a disadvantage in that the ability to detect and detect motion in a moving image is deteriorated. on the other hand,
When the level of the reference level signal _Vth is set to, for example, the level of a frame difference signal of a flat portion of a still image source,
Although the motion detection capability at the time of moving images is improved, at the time of a still image, there is a problem that a detection error occurs due to noise or the like generated in a portion having a high frequency component such as an edge portion.

Therefore, it is an object of the present invention to perform appropriate signal conversion according to image content.

[Means for solving the problem]

The present invention provides a level comparing means (51) for converting an output signal of a motion detecting means (50) into a 1-bit signal, and a level setting means (10) for setting a reference level supplied to the level comparing means (51). ) And vertical edge detecting means (1) to
(3) or horizontal edge detecting means (5) to (7), wherein the level setting means (10) includes vertical edge detecting means (1) to (3) or horizontal edge detecting means (5). To (7).

[Action]

In the above-described configuration, when a vertical edge portion or a horizontal edge portion is detected, for example, the reference level is increased, so that it is possible to avoid a detection error from occurring at a high level of noise generated at the edge portion in a still image. When neither a vertical edge portion nor a horizontal edge portion is detected, for example, the reference level is lowered, so that the motion detection ability at the time of moving image does not deteriorate.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the figure, reference numeral (10) denotes a changeover switch which constitutes a level setting means.
Voltage terminals V _th1 , V _th2 , V _th3
Is supplied. The levels of these voltages V _th1 , V _th2 , V _th3 are
V _th1 > V _th2 > V _th3 . The output signal of the changeover switch (10) is supplied to a level comparator (5
1) is supplied as a reference level signal _Vth .

The luminance signal Y output from the Y / C separation circuit (64) (not shown in FIG. 1) is supplied to the vertical edge detector (1). The vertical edge detector (1) outputs a line difference signal. The line difference signal is supplied to a level comparator (3) after being converted into an absolute value by an absolute value circuit (2). When the supplied line difference signal is equal to or more than the reference level signal _Vt1 , a signal of, for example, a high level “1” is output from the level comparator (3) as a vertical edge portion, and the signal is equal to or less than one. At times, a low level “0” signal is output.

The luminance signal Y output from the Y / C separation circuit (64)
Are supplied to a horizontal edge detector (5). A pixel difference signal is output from the horizontal edge detector (5), and the pixel difference signal is supplied to a level comparator (7) after being converted into an absolute value by an absolute value circuit (6). When the supplied pixel difference signal is equal to or more than the reference level signal _{Vt2, the} level comparator (7) outputs a signal of, for example, a high level "1" as a horizontal edge portion, and the signal is equal to or less than one. At times, a low level “0” signal is output.

The output signals of the level comparators (3) and (7) are supplied to a logic circuit (4) and operated. The changeover switch (10) is controlled by the output signal of the logic circuit (4). That is, when the output signal of the level comparator (3) is at the high level "1" in the case of a vertical edge portion and a horizontal edge portion, or in the case of a vertical edge portion and not a horizontal edge portion, the changeover switch (10) Connected to a side.
In the case where the horizontal edge portion is not the vertical edge portion, when the output signals of the level comparators (3) and (7) become low level “0” and high level “1”, respectively, the changeover switch (1)
0) is connected to the b side. When neither the vertical edge portion nor the horizontal edge portion is present, and the output signals of the level comparators (3) and (7) are both at the low level "0", the changeover switch (10) is connected to the c side.

In the present example having such a configuration, in the vertical edge portion and the horizontal edge portion, the changeover switch (10) is set to the a side or the b side.
And the reference level signal V _th supplied to the level comparator (51) is V _th1 or V _th1 as shown in FIG.
_th2 . For this reason, the reference level is increased, and high-level noise generated at the edge portion during a still image is suppressed. Therefore, it is possible to prevent a detection error from occurring.

Here, in the vertical edge portion, the changeover switch (10) is set to a
Side, the reference level signal V _th becomes V _th1 , and the reference level is set to the highest level. For example, when the Y / C separation circuit (64) is configured by a comb filter using line correlation, This is because the motion detection signal contains a large amount of dot interference components corresponding to the vertical edge portions, and is likely to be affected by this.

When neither the vertical edge portion nor the horizontal edge portion is present, the changeover switch (10) is connected to the c side, and the reference level signal _Vth supplied to the level comparator (51) is, as shown in FIG. V _th3 . Therefore, the reference level is lowered, and the ability to detect a moving image does not deteriorate.

In the above embodiment, the reference level signal V _th is V
_{Since the} switching can be performed in three stages from _{th1 to} V _th3 , the switching may be performed in more stages or may be changed linearly.

Further, in the above-described embodiment, the reference level is controlled by detecting both the vertical edge portion and the horizontal edge portion. However, the reference level may be controlled by detecting only one of them. Good.

〔The invention's effect〕

According to the present invention, the reference level is controlled by the vertical edge detecting means or the horizontal edge detecting means. For example, the reference level is set to be high in the vertical edge portion and the horizontal edge portion. The high-level noise that is generated can be suppressed to prevent detection errors from occurring, and the reference level is set to be low in portions that are neither vertical edges nor horizontal edges. Does not deteriorate. Therefore,
According to the present invention, there is an advantage that an appropriate signal conversion according to the image content is performed.

[Brief description of the drawings]

FIG. 1 is a structural diagram showing one embodiment of the present invention, FIG. 2 is a diagram for explaining the embodiment, FIG. 3 is a structural diagram of an example of a television receiver, and FIG. 4 is a structural diagram of a motion detecting circuit. FIG. 5 is a configuration diagram of a scanning line interpolation circuit, and FIG. 6 is a diagram showing a scanning line structure on a time-vertical plane. (1) is a vertical edge detector, (2) and (6) are absolute value circuits, (3) and (7) are level comparators, (4) is a logic circuit, (5) is a horizontal edge detector, ( 10) is a changeover switch, (50) is a motion detection circuit, (51) is a level comparator,
(52) is a coefficient generator.

Claims (1)

(57) [Claims] A level comparing means for converting an output signal of the motion detecting means into a 1-bit signal; a level setting means for setting a reference level supplied to the level comparing means; a vertical edge detecting means or a horizontal edge detecting means; Means for controlling the motion detection signal, wherein the level setting means is controlled by the vertical edge detecting means or the horizontal edge detecting means.