JPH06260845A - Differential input type reception circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption when a reception function is stopped by providing a functional control element at a differential amplifier circuit, and controlling the amplification function of the differential amplifier circuit based on an operation permission signal. CONSTITUTION:The differential amplifier circuit 11 which performs the differential amplification of two input signals IN1, IN2, and an output control circuit 12 which outputs a differentially amplified signal level based on the operation permission signal IN3 are provided. The functional control element 13 is provided at the circuit 11, and the element 13 controls the amplification function of the amplifier circuit 11 based on the signal IN3. For example, the element 13 consists of an n-field effect transistor TN, and the transistor TN is connected between a differential point (c) provided at the amplifier circuit 11 and a constant current source Io, and the signal IN3 is supplied to the gate of the transistor TN. As a result, it is possible to supply the operation permission signal to the differential input/output stages of the amplifier circuit 11 and to control an amplification output function and to reduce the power consumption when the reception function is stopped.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field of the Invention Conventional Technology (FIG. 32) Problem to be Solved by the Invention Means for Solving the Problems (FIGS. 1 to 4) Action Example (1) First Example (FIGS. 5, 6) (2) Second embodiment (FIGS. 7, 8) (3) Third embodiment (FIGS. 9, 10) (4) Fourth embodiment (FIGS. 11, 12) (5) ) Fifth embodiment (FIG. 13) (6) Sixth embodiment (FIG. 14) (7) Seventh embodiment (FIG. 15) (8) Eighth embodiment (FIG. 16) (9) 9th embodiment (FIG. 17) (10) 10th embodiment (FIG. 18) (11) 11th embodiment (FIG. 19) (12) 12th embodiment (FIG. 20) (13) 13th embodiment Example (Fig. 21) (14) Fourteenth Example (Fig. 22) (15) Fifteenth Example (Fig. 23) (16) Sixteenth Example (Fig. 24) (17) Seventeenth Example (Figure 25) (18) 18th Example (Figure 26) (19) 19th Example (Figure 27) (20) 20th Example (Figure 28) (21) 21st Example Example (29) (22) Example of 22 (FIG. 30) (23) 23 Example (FIG. 31) the effect of the invention of

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential input type receiving circuit, and more particularly to improvement of a receiving circuit used as an input interface circuit of a communication modem connected to a telephone line. . 2. Description of the Related Art In recent years, a semiconductor integrated circuit (hereinafter referred to as LSI) device used as an input interface circuit of a communication modem has been required in response to a demand for reduction of power consumption of electronic devices connected to a telephone line or a dedicated line for various information communication. Also, low power consumption is required.

According to this, a 3-state circuit for switching between stopping and continuing the receiving function of the communication modem is connected to a subsequent stage of the differential amplifier circuit, and an enable signal is supplied only to the 3-state circuit. Therefore, although the receiving function of the communication modem is stopped by the enable signal, the constituent transistors of the differential amplifier circuit continue the ON / OFF operation in response to the input signal of the telephone line or the dedicated line, and the receiving function is stopped. Power consumption continues to occur even in the state.

Therefore, there is a demand for a circuit capable of supplying an enable signal to the differential amplifier circuit and the three-state circuit to control the amplification output function and reducing power consumption as much as possible when the reception function is stopped. .

[0005]

2. Description of the Related Art FIG. 32 is a block diagram of a differential input type receiving circuit according to a conventional example. For example, a differential input type receiving circuit as found in an input interface circuit such as a communication modem connected to a telephone line or a dedicated line comprises a differential amplifier circuit 1 and a 3-state circuit 2 in FIG. The differential amplifier circuit 1 is composed of n-type field effect transistors TN1 to TN4 and p-type field effect transistors TP1 to TP3. For example, a constant current source transistor TN1 and a differential pair transistor TN3, T.
N4, current mirror transistors TP1 and TP2, a bias circuit 1B and an inverter 1A. The three-state circuit 2 is connected to switch the receiving function of the communication modem between stop and continue.

The operation of the differential input type receiving circuit is ON when the enable signal IN3 = “H” (high) level, for example.
It operates and continues the receiving function of the communication modem. Here, when the voltage relationship between the input signals IN1 and IN2 is IN1> IN2, the potentials at points a and b of the differential amplifier circuit 1 are Va <Vb, and the threshold voltage Vth of the inverter 1A and the potential Va at point a are Va. If the relation with Vth> Va, then the transistor TP3
Is turned on and the point e becomes "H" level.

Similarly, when the input voltage is IN1 <IN2,
If the potential relationship between points a and b is Va> Vb, and the threshold relationship of the inverter 1A is Vth <Va, the transistor TN2 is turned on and the point e becomes "L" (low) level. At this time, from the bias circuit 1B to the transistor TN1
Further, a gate voltage that determines the operating current of the differential amplifier circuit 1 is supplied. When the enable signal IN3 = “L” level, the reception function of the communication modem is stopped, that is, the three-state circuit 2 performs the OFF operation, and the output part thereof is set to the high impedance state (hereinafter referred to as the Z state).

[0008]

By the way, according to the conventional example, the 3-state circuit 2 for switching the stop / continuation of the receiving function of the communication modem is connected to the subsequent stage of the differential amplifier circuit 1 and the enable signal IN3 is set to 3. It is supplied only to the state circuit (hereinafter also referred to as the output control circuit) 2. For this reason,
Enable signal (hereinafter also referred to as operation enable signal) IN3 =
Although the receiving function of the communication modem is stopped by the "L" level, the voltage relationship between the input signals IN1 and IN2, IN1> IN
2 and IN1 <IN2 are received, the transistors TP1, TP2, TN1, TN3, and TN4 of the differential amplifier circuit 1 continue ON / OFF operation.

As a result, power consumption continues to occur even when the reception function is stopped, which hinders the reduction of power consumption of electronic equipment that is connected to a telephone line or a dedicated line to perform various information communications. . The present invention was created in view of the problems of the conventional example, and supplies an operation permission signal to the differential input stage and its output stage to control the amplification output function,
An object of the present invention is to provide a differential input type receiving circuit that can reduce power consumption as much as possible when the receiving function is stopped.

[0010]

1 to 4 respectively show principle diagrams (1 to 4) of a differential input type receiving circuit according to the present invention. As shown in FIG. 1, a first differential input type receiving circuit of the present invention operates a differential amplifier circuit 11 for differentially amplifying two input signals IN1 and IN2, and a differentially amplified signal level. An output control circuit 12 that outputs based on the permission signal IN3, a function control element 13 is provided in the differential amplifier circuit 11, and the function control element 13 operates based on the operation permission signal IN3. It is characterized by controlling the amplification function of.

In the first differential input type receiving circuit of the present invention, the function control element 13 is composed of an n-type field effect transistor TN, and as shown in FIG. The effect transistor TN is connected between the differential point c provided in the differential amplifier circuit 11 and the constant current source Io,
An operation permission signal IN3 is supplied to the gate of the n-type field effect transistor TN.

Further, in the second differential input type receiving circuit of the present invention, as shown in FIG. 2B, the function control element 13 is composed of a bias supply control circuit 13A, and the bias supply control circuit 13A is It is characterized in that it is connected between the constant current source Io of the differential amplifier circuit 11 and the bias circuit 11A, and the bias supply control circuit 13A is controlled based on the operation permission signal IN3.

Further, in the third differential input type receiving circuit of the present invention, as the function control element 13 is as shown in FIG.
It is composed of a p-type field effect transistor TP and an n-type field effect transistor TN, and the p-type field effect transistor TP is a current mirror circuit 11B of the differential amplifier circuit 11.
Of the n-type field effect transistor TN connected between the common gate of the current mirror circuit 11B and the power source line Vcc on the high potential side, and the differential pair transistor TN3 or TN4 of the differential amplifier circuit 11 and the common gate of the current mirror circuit 11B. Of the p-type and n-type field effect transistors TP and T connected to the drains of the
The operation enable signal IN3 is supplied to the N gate.

Further, in the fourth differential input type receiving circuit of the present invention, as shown in FIG. 3B, the function control element 13 comprises a first switching circuit 13B, and the first switching circuit 13B. Is connected between the gates of the differential pair transistors TN3 and TN4 of the differential amplifier circuit 11 and the power supply line GND on the low potential side and the supply parts of the input signals IN1 and IN2, and the first switching circuit 13B operates. It is characterized in that it is controlled based on the permission signal IN3 and an inverted signal of the operation permission signal IN3.

Further, in the fifth differential input type receiving circuit of the present invention, as shown in FIG. 4 (A), the function control element 13 comprises a second switching circuit 13C, and the second switching circuit 13C. Is connected between the differential pair transistors TN3 and TN4 of the differential amplifier circuit 11 and the current mirror circuit 11C, and the second switching circuit 13C is based on the operation permission signal IN3 or the inverted signal of the operation permission signal IN3. It is characterized by being controlled.

The sixth differential input type receiving circuit of the present invention is the same as the first to fourth differential input type receiving circuits shown in FIG.
As shown in (B), the function control element 13 includes an n-type field effect transistor TN or a p-type field effect transistor TP, and the n-type field effect transistor TN.
Alternatively, the p-type field effect transistor TP is the differential amplifier circuit 1.
1 is connected to the output circuit 11D, and the n-type field effect transistor TN or the p-type field effect transistor TP is
It is characterized in that it is controlled based on the operation permission signal IN3, an inverted signal of the operation permission signal IN3, or a delay signal of both signals.

Further, the seventh differential input type receiving circuit of the present invention is the same as the first to sixth differential input type receiving circuits, as shown in FIG.
The third delay circuit 14 is connected, and the delay circuit 14 delays the operation permission signal IN3, thereby achieving the above object.

[0018]

[Operation] According to the first differential input type receiving circuit of the present invention, the differential amplifier circuit 11 and the output control circuit 12 are provided as shown in FIG. 1, and the function control element 13 is the differential amplifier circuit 1.
1 and controls the amplification function of the differential amplifier circuit 11 based on the operation permission signal IN3.

For example, when receiving the input signals IN1 and IN2, as shown in FIG. 2A, n connected between the differential point c of the differential amplifier circuit 11 and the constant current source Io. -Type field effect transistor TN (function control element 13) is supplied with the operation permission signal IN3 = “H” level, the transistor TN is turned on, and the amplification function of the differential amplifier circuit 11 is maintained. , The input signals IN1 and IN2 are differentially amplified. Further, the differentially amplified signal level is based on the operation permission signal IN3 = “H” level, and the output control circuit 12
Output to the internal circuit.

Further, when the reception of the input signals IN1 and IN2 is stopped (reception refusal), the operation permission signal IN3 = “L” level is supplied to the gate of the transistor TN so that the transistor TN performs the OFF operation. Then, the amplification function of the differential amplifier circuit 11 is stopped, and at the same time, the operation permission signal IN
3 = The output function of the output control circuit 12 is stopped based on the “L” level.

Therefore, the operation enable signal IN3 = "L" level stops the receiving function of the differential input type receiving circuit, and the voltage relationship between the input signals IN1 and IN2 is IN1> IN.
2 and IN1 <IN2, even if the supply state changes, the power supply line V CC of the differential amplifier circuit 11 in the state where the receiving function is stopped
The current path between the ground lines GND is cut off by the transistor TN, and the transistor operation of the differential amplifier circuit 11 can be forcibly stopped. This makes it possible to suppress the power consumption of the differential amplifier circuit 11 when the reception function is stopped as much as possible.

As a result, when the differential input type receiving circuit is incorporated in an electronic device which is connected to a telephone line or a dedicated line for various information communication, the power consumption can be reduced. . Further, according to the second differential input type receiving circuit of the present invention, as shown in FIG. 2B, the bias supply control circuit 13A is connected between the constant current source Io and the bias circuit 11A.

For example, in FIG. 2B, the input signal IN
When receiving 1 and IN2, the bias supply control circuit 13
By supplying the operation permission signal IN3 = “H” level to A, the control circuit 13A is activated and the bias circuit 11A is activated.
And the constant current source Io are connected, the amplifying function of the differential amplifier circuit 11 is maintained, and the input signals IN1 and IN2 are differentially amplified. The differentially amplified signal level is output from the output control circuit 12 to the internal circuit based on the operation permission signal IN3 = “H” level as in the first differential input type receiving circuit.

Further, when the reception of the input signals IN1 and IN2 is stopped, the bias supply control circuit 13A is supplied with the operation permission signal IN3 = “L” level so that the control circuit 13A is inactivated. , Bias circuit 11A and constant current source I
O is disconnected and the amplification function of the differential amplifier circuit 11 is stopped, and at the same time, the output function of the output control circuit 12 is stopped based on the operation permission signal IN3 = “L” level.

For this reason, like the first differential input type receiving circuit, the reception function is stopped by the operation permission signal IN3 = "L" level, and the input signals IN1 and IN2 are changed to the differential pair transistor TN3 ,. Even when supplied to TN4, it is possible to forcibly stop the transistor operation of the differential amplifier circuit 11 when reception is stopped. As a result, like the first differential input type receiving circuit, it becomes possible to suppress the power consumption of the differential amplifier circuit 11 when the receiving function is in a stopped state as much as possible, and an electronic device incorporating the differential input type receiving circuit. It is possible to reduce the power consumption of the device.

Further, according to the third differential input type receiving circuit of the present invention, as shown in FIG. 3A, between the common gate of the current mirror circuit 11B and the power supply line VCC on the high potential side. A p-type field effect transistor TP is connected, and an n-type field effect transistor TN is connected between the common gate of the p-type field effect transistor TP and the drain of one of the differential pair transistors TN3 or TN4 of the differential amplifier circuit 11. The operation permission signal IN3 is supplied to the gates of TP and TN.

For example, in FIG. 3A, the input signal IN
When receiving 1 and IN2, the transistors TP and TN
By supplying the operation enable signal IN3 = “H” level to the gate of the transistor, the transistor TP performs the OFF operation and the transistor TN performs the ON operation. As a result, the current mirror circuit 11B is activated, the amplification function of the differential amplifier circuit 11 is maintained, and the input signals IN1 and IN2 are differentially amplified.
Further, the differentially amplified signal level is output from the output control circuit 12 to the internal circuit based on the operation permission signal IN3 = “H” level as in the first and second differential input type receiving circuits.

Furthermore, when the reception of the input signals IN1 and IN2 is stopped, the transistor TP is turned on by supplying the operation permission signal IN3 = “L” level to the gates of the transistors TP and TN. TN is O
Perform FF operation. As a result, the current mirror circuit 11B is deactivated, the amplification function of the differential amplifier circuit 11 is stopped, and at the same time, the output function of the output control circuit 12 is stopped based on the operation permission signal IN3 = “L” level. It

Therefore, like the first and second differential input type receiving circuits, the operation permission signal IN3 = “L” level causes
Even when the reception function is stopped and the input signals IN1 and IN2 are supplied to the differential pair transistors TN3 and TN4, the transistor operation of the differential amplifier circuit 11 when the reception is stopped is forcibly stopped. Is possible. As a result, like the first and second differential input type receiving circuits, it becomes possible to suppress the power consumption of the differential amplifier circuit 11 when reception is stopped as much as possible, and an electronic device incorporating the differential input type receiving circuit. It is possible to reduce the power consumption of the device.

Further, according to the fourth differential input type receiving circuit of the present invention, as shown in FIG. 3B, the gates of the differential pair transistors TN3 and TN4 and the power source line GND on the low potential side are inputted. First switching circuit between the signal IN1 and IN2 supply section
13B is connected, and the circuit 13B is controlled based on the operation permission signal IN3 and its inverted signal. For example, FIG. 3 (B)
In the case of receiving the input signals IN1 and IN2, the operation permission signal IN3 = “H” is sent to the first switching circuit 13B.
The first switching circuit by supplying the level
13B is turned on, the input signals IN1 and IN2 are supplied to the gates of the differential pair transistors TN3 and TN4, respectively, and both input signals IN1 and IN2 are differentially amplified. The differentially amplified signal level is output from the output control circuit 12 to the internal circuit based on the operation permission signal IN3 = “H” level as in the first to third differential input type receiving circuits.

Further, when the reception of the input signals IN1 and IN2 is stopped, the operation permission signal IN3 = “L” level is supplied to the first switching circuit 13B so that the first switching circuit 13B is turned off. Then, the gates of the differential pair transistors TN3 and TN4 are fixed to the low potential side, the supply of both input signals IN1 and IN2 is cut off, the amplifying function of the differential amplifier circuit 11 is stopped, and at the same time, the operation permission signal IN3. = "L"
The output function of the output control circuit 12 is stopped based on the level.

Therefore, like the first to third differential input type receiving circuits, the operation permission signal IN3 = “L” level causes
The reception function is stopped and the differential pair transistor TN
By fixing the gate of 3, TN4 to "L" level,
It is possible to stop the amplification operation of the differential amplifier circuit 11 when reception is stopped. As a result, like the first to third differential input type receiving circuits, the differential amplifier circuit 11 when reception is stopped
It is possible to suppress the power consumption of the device as much as possible, and it is possible to reduce the power consumption of the electronic device incorporating the differential input type receiving circuit.

Further, according to the fifth differential input type receiving circuit of the present invention, as shown in FIG. 4A, the second pair is provided between the differential pair transistors TN3 and TN4 and the current mirror circuit 11C.
The switching circuit 13C is connected, and the circuit 13C is controlled based on the operation permission signal IN3 or the inverted signal of the operation permission signal IN3. For example, in FIG. 4A, the input signal
When receiving IN1 and IN2, by supplying the operation permission signal IN3 = “H” level to the second switching circuit 13C, the second switching circuit 13C is turned on and the difference from the current mirror circuit 11C. Dynamic pair transistor TN
3, TN4 are connected, the amplification function of the differential amplifier circuit 11 is maintained, and the input signals IN1 and IN2 are differentially amplified. The differentially amplified signal level is output from the output control circuit 12 to the internal circuit based on the operation permission signal IN3 = “H” level as in the first to fourth differential input type receiving circuits.

Further, when the reception of the input signals IN1 and IN2 is stopped, the second switching circuit 13C is turned off by supplying the operation permission signal IN3 = "L" level to the second switching circuit 13C. Then, the current mirror circuit 11C and the differential pair transistors TN3 and TN4 are disconnected, the amplifying function of the differential amplifier circuit 11 is stopped, and at the same time, based on the operation permission signal IN3 = “L” level. The output function of the output control circuit 12 is stopped.

Therefore, like the first to fourth differential input type receiving circuits, the receiving function is stopped by the operation permission signal IN3 = “L” level or its inverted signal, and the second switching circuit is used. By the ON operation of 13C, it becomes possible to stop the amplification operation of the differential amplifier circuit 11 when the reception is stopped. As a result, like the first to fourth differential input type receiving circuits, it becomes possible to suppress the power consumption of the differential amplifier circuit 11 when reception is stopped as much as possible, and an electronic device incorporating the differential input type receiving circuit. It is possible to reduce the power consumption of the device.

According to the sixth differential input type receiving circuit of the present invention, the differential input type receiving circuit as shown in FIGS. 2 (A), (B), 3 (A) and 3 (B). 4B, the n-type field effect transistor TN or the p-type field effect transistor TP is connected to the output circuit 11D of the differential amplifier circuit 11 as shown in FIG.
It is controlled based on the operation permission signal IN3 or its inverted signal.

For example, in FIG. 2A, the input signal IN
When receiving 1 and IN2, by supplying the operation permission signal IN3 = “H” level to the transistor TN, the transistor TN is turned on, the amplification function of the differential amplifier circuit 11 is maintained, and the input signal is input. The signals IN1 and IN2 are differentially amplified. In addition, the differentially amplified signal level is the operation permission signal.
Output from the output control circuit 12 to the internal circuit based on IN3 = “H” level.

Further, when the reception of the input signals IN1 and IN2 is stopped, the operation permission signal IN3 = is applied to the gate of the transistor TN connected between the constant current source Io and the differential point c.
An inverted signal of the operation permission signal IN3 = “H” is supplied to the transistor TN which supplies the “L” level and is connected to the output circuit 11D.
By supplying the level, the transistor TN connected to the constant current source Io performs the OFF operation, and the differential amplifier circuit 11
The amplification function of is stopped, and at the same time, the transistor TN connected to the output circuit 11D is turned on based on the delayed inverted signal = “H” level of the operation permission signal IN3, so that the input part of the output circuit 11D becomes “ It is fixed at the "L" level.

Therefore, compared with the first to fifth differential input type reception circuits, the reception function is stopped and the output circuit 11D is connected by the operation enable signal IN3 = "L" level inversion signal. By turning on the transistor TN,
It is possible to stop the amplifying operation of the differential amplifier circuit 11 when the reception is stopped and also stop the amplifying operation of the output circuit 11D.

This makes it possible to further reduce the power consumption of the differential amplifier circuit 11 when reception is stopped, as compared with the first to fifth differential input type receiver circuits, and the differential input type receiver circuits. It is possible to reduce the power consumption of the electronic device incorporating the receiving circuit. Further, according to the seventh differential input type receiving circuit of the present invention, in the first to sixth differential input type receiving circuits, as shown in FIG. 1, the output control circuit 12 or the function control element 13 has a delay circuit. 14 is connected to the circuit 1
4 delays the operation enable signal IN3.

Therefore, in the first to fifth differential input type receiving circuits of the present invention, the function control element 13 of the differential amplifier circuit 11 is used.
In contrast, the operation permission signal IN3 is faster than the output control circuit 12.
Is supplied and the potential level at the operating point a of the differential amplifier circuit 11 reaches the threshold voltage Vth of the output circuit 11D, the delay signal of the operation permission signal IN3 can be supplied to the output control circuit 12.

Particularly, by supplying the delayed signal of the operation permission signal IN3 to the gate of the n-type field effect transistor TN or the p-type field effect transistor TP connected to the input part of the output circuit 11D, After the potential level at the operating point a of the amplifier circuit 11 reaches the threshold voltage Vth of the output circuit 11D, it can be supplied to the output circuit 11D.

As a result, when the differential input type receiving circuit shifts from the reception stopped state to the operating state, the differential amplifier circuit 11 transits to a stable operation and then the output high impedance state is released. More stable input signal
Since IN1 and IN2 can be incorporated into the internal circuit, it greatly contributes to the improvement of the reliability of the interface circuit for communication modem etc. in which the differential input type receiving circuit is incorporated.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, each embodiment of the present invention will be described with reference to the drawings. 5 to 31 are diagrams for explaining the differential input type receiving circuit according to the embodiment of the present invention. (1) Description of First Embodiment FIG. 5 is a configuration diagram of a differential input type receiving circuit according to a first embodiment of the present invention, and FIG. 6 is a supplementary explanatory diagram thereof.

For example, as shown in FIG. 5A, the differential input type receiving circuit applicable to the input interface circuit of a communication modem or the like connected to a telephone line or a dedicated line is, as shown in FIG. It consists of a 3-state circuit 12. The logical symbol of the differential input type receiving circuit is shown in FIG.
It shows in (A). That is, the differential amplifier circuit 11 is connected to a telephone line or a dedicated line, differentially amplifies two input signals IN1 and IN2, and outputs the signal level at the output operating point a to the inverter INV1. The differential amplifier circuit 11 includes a transistor for constant current source (hereinafter also simply referred to as constant current source Io) TN1, a differential pair transistor TN3, TN4, an n-type field effect transistor TN51, a bias circuit 11A, and a current mirror circuit 11.
It consists of C and inverter INV1.

The constant current source transistor TN1 is composed of an n-type field effect transistor, the gate of which is connected to the bias circuit 11A and the source of which is connected to the ground line GND. The differential pair transistors TN3 and TN4 are composed of n-type field effect transistors and have two input signals at their gates.
IN1 and IN2 are supplied. Also, both transistors TN3,
Each drain of TN4 is connected to the current mirror circuit 11C, and its common source connection point (differential point) c is connected to the drain of the n-type field effect transistor TN51.

The n-type field effect transistor TN51 is an example of the function control element 13, and the differential pair transistor TN3,
It is connected between the differential point c of TN4 and the constant current source Io, and an operation enable signal (hereinafter referred to as an enable signal) IN3 is supplied to the gate of the transistor TN51. As a result, the differential pair transistors TN3 and TN4 are generated based on the enable signal IN3.
It is possible to control the amplification function of the differential amplifier circuit 11 by shutting off the operating current.

Further, the bias circuit 11A is a transistor T
The gate voltage is supplied to N1, and the current mirror circuit 11C adjusts the operating current of the differential pair transistors TN3 and TN4. The current mirror circuit 11C is a p-type field effect transistor T.
P1 and TP2, the sources of which are connected to the power supply line Vcc and the common gate of which is connected to the drain of the differential pair transistor TN4. The inverter INV1 is an example of the output circuit 11D, and is composed of p-type and n-type field effect transistors TP3 and TN2 connected in series between the power supply line VCC and the ground line GND, and the drain of the differential pair transistor TN3 (output operating point The signal level of a) is inverted and amplified and output to the 3-state circuit 12.

The 3-state circuit 12 is an example of the output control circuit 12, and outputs the differentially amplified signal level to the internal circuit of the next stage based on the enable signal IN3. The three-state circuit 12 is composed of a transfer gate in which an inverter INV is combined with a circuit in which n-type and p-type field effect transistors TN and TP are connected in parallel as shown in FIGS. 6B and 6C, for example.

The function of the transfer gate is shown in FIG.
When the inverter INV is connected to the gate side of the p-type field effect transistor TP as shown in (B), the enable signal IN3 = “H” level is turned on, while the signal IN3 = “L” level is turned on. The OFF operation is performed with to set the output high impedance state. Table 1 shows enable "L"
In the case (operating condition), the output truth values of the output unit OUT with respect to the input truth values of the input signals IN1 and IN2 and the enable signal IN3 are shown.

[0051]

[Table 1]

In addition, as shown in FIG.
When INV is connected to the gate side of the n-type field effect transistor TN, the transfer gate is turned on by the enable signal IN3 = “L” level, and the signal is reversed.
The OFF operation is performed at IN3 = “H” level to maintain the output high impedance state. Table 2 shows the input signals IN1 and IN when the enable is “L” (operating condition).
2 and the output truth value of the output unit OUT for the input truth value of the enable signal IN3.

[0053]

[Table 2]

In this way, according to the differential input type receiving circuit of the first embodiment of the present invention, as shown in FIG.
A differential amplifier circuit 11 and a three-state circuit 12 are provided,
Differential point c of the differential pair transistors TN3 and TN4 and the constant current source I
An n-type field effect transistor TN51 is connected to the gate of the transistor o and the gate of the transistor TN51 has an enable signal IN.
It is controlled based on 3.

For example, when receiving the input signals IN1 and IN2, in the operation explanatory diagram of FIG. 5B, the enable signal IN3 = "H" level is supplied to the gate of the transistor TN51 so that the transistor TN51 is supplied. Turns on, the amplifying function of the differential amplifier circuit 11 is maintained, and the input signals IN1 and IN2 are differentially amplified. Further, the differentially amplified signal level is output from the three-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level.

Further, when the reception of the input signals IN1 and IN2 is stopped (reception refusal), the enable signal IN3 = "L" level is supplied to the gate of the transistor TN51 so that the transistor TN51 performs the OFF operation. , The amplification function of the differential amplifier circuit 11 is stopped, and at the same time, the 3-state circuit 1 is generated based on the enable signal IN3 = “L” level.
The output of 2 is put in the "Z" (high impedance) state.

Therefore, the enable signal IN3 = “L” level stops the receiving function of the differential input type receiving circuit, and the voltage magnitude relationship between the input signals IN1 and IN2 is IN.
1> IN2 and IN1 <IN2, and even if the gates of the differential pair transistors TN3 and TN4 are excited, the power supply line Vcc of the differential amplifier circuit 11 in the stopped state of the reception function
The current path between the ground line GND and the ground line GND is cut off by the transistor TN51, and the transistor operation of the differential amplifier circuit 11 can be forcibly stopped. This makes it possible to suppress the power consumption of the differential amplifier circuit 11 when the reception function is stopped as much as possible.

As a result, when the differential input type receiving circuit is incorporated in an electronic device which is connected to a telephone line or a dedicated line for various information communication, the power consumption can be reduced. . (2) Description of Second Embodiment FIG. 7 is a configuration diagram of a differential input type receiver circuit according to a second embodiment of the present invention, and FIGS. 8 (A) and 8 (B) are explanatory diagrams of its operation. Are shown respectively.

In FIG. 7, the second embodiment differs from the first embodiment in that the differential amplifier circuit 21 is provided with a bias supply control circuit 13A. That is, the bias supply control circuit 13A is another example of the function control element 13, and is connected between the constant current source transistor TN1 of the differential amplifier circuit 21 and the bias circuit 11A. For example, the bias supply control circuit 13A is an n-type field effect transistor TN5.
2, TN62 and an inverter INV2, the source of the transistor TN52 is connected to the drain of the transistor TN62 and to the gate of the transistor TN1.

The drain of the transistor TN52 is connected to the bias circuit 11A, and the enable signal IN3 is supplied to its gate. The source of the transistor TN62 is connected to the ground line GND, and its gate has an enable signal.
IN3 is supplied via the inverter INV2. The constant current source transistor TN1, the differential pair transistor TN3,
Since the TN4, the bias circuit 11A, the current mirror circuit 11C, the inverter INV1 and the three-state circuit 12 are the same as those in the first embodiment, the description thereof will be omitted.

In this way, according to the differential input type receiving circuit of the second embodiment of the present invention, as shown in FIG.
Bias supply control circuit 13A is a constant current source transistor T
It is connected between N1 and the bias circuit 11A. For example, in the operation explanatory diagram of FIG. 8A, when the reception of the input signals IN1 and IN2 is stopped, by supplying the enable signal IN3 = "L" level to the bias supply control circuit 13A, the transistor TN52 is turned on. OFF circuit, bias circuit
By disconnecting 11A and the constant current source Io and turning on the transistor TN62, the "L" level is supplied to the transistor TN1. As a result, the amplifying function of the differential amplifier circuit 21 is stopped, and at the same time, the 3-state circuit 12 is driven based on the enable signal IN3 = "L" level.
Is put in the "Z" state.

When the input signals IN1 and IN2 are received, the enable signal IN3 = "H" level is supplied to the bias supply control circuit 13A in the operation explanatory diagram of FIG. The circuit 13A is activated, the bias circuit 11A and the constant current source Io are connected, the amplification function of the differential amplifier circuit 21 is maintained, and the input signals IN1 and IN2 are differentially amplified. The differentially amplified signal level is the first
Similar to the embodiment described above, the 3-state circuit 12 outputs the signal to the internal circuit based on the enable signal IN3 = "H" level.

Therefore, similarly to the first embodiment, the receiving function is stopped by the enable signal IN3 = "L" level, and the input signals IN1 and IN2 are supplied to the differential pair transistors TN3 and TN4. Even in the state, it is possible to forcibly stop the transistor operation of the differential amplifier circuit 21 when reception is stopped. As a result, it becomes possible to suppress the power consumption of the differential amplifier circuit 21 when the receiving function is stopped as much as possible as in the first embodiment, and the power consumption of the electronic device incorporating the differential input type receiving circuit. Can be reduced.

(3) Description of Third Embodiment FIG. 9 is a configuration diagram of a differential input type receiving circuit according to a third embodiment of the present invention, and FIGS. 10 (A) and 10 (B) show the same. Each operation explanatory view is shown. In FIG. 9, the difference from the first and second embodiments is that in the third embodiment, a differential amplifier circuit 31
The current mirror circuit 11B is connected with a p-type field effect transistor TP43 and an n-type field effect transistor TN53.

That is, the current mirror circuit 11B has the first
Unlike the current mirror circuit 11C according to this embodiment, the transistor TP43 is connected between the common gates of the transistors TP1 and TP2 connected to the power supply line Vcc and the power supply line Vcc. In addition, the common gate and the differential pair transistor TN4
A transistor TN53 is connected to the drain of the transistor (operating point b). The gates of both transistors TP43 and TN53 are connected, and the enable signal IN
3 is supplied.

Further, depending on the usage of the differential output signal,
When the common gate potential of the transistors TP1 and TP2 is supplied from the drain of the differential pair transistor TN3, the source of the transistor TN53 is connected to the drain of the transistor TN3. The constant current source transistor TN1, the differential pair transistors TN3 and TN4, the bias circuit 11A, the inverter INV1 and the three-state circuit 12 are the same as those in the first and second embodiments, and the description thereof will be omitted.

In this way, according to the differential input type receiving circuit of the third embodiment of the present invention, as shown in FIG.
A transistor TP43 is connected between the common gates of the transistors TP1 and TP2 and the power supply line Vcc, and the transistor T43 is connected between the common gate and the drain of the transistor TN4.
N53 is connected, and the gates of both transistors TP43 and TN53 are controlled based on the enable signal IN3.

For example, in the operation explanatory diagram of FIG. 10A, when the reception of the input signals IN1 and IN2 is stopped, the enable signal IN is applied to the gates of the transistors TP43 and TN53.
By supplying 3 = “L” level, the transistor TP43 is turned on and the transistor TN53 is turned off. As a result, the transistors TP1 and TP2 perform the OFF operation, the current mirror circuit 11B is deactivated, the amplifying function of the differential amplifier circuit 31 is stopped, and at the same time, when the enable signal IN3 = “L” level is set to 3 State circuit 1
The output of 2 is put in the "Z" state.

When receiving the input signals IN1 and IN2, the enable signal IN3 = “H” is applied to the gates of the transistors TP43 and TN53 in the operation explanatory diagram of FIG. 10B.
By supplying the level, the transistor TP43 is turned off.
FF operation is performed, and the transistor TN53 is turned on. As a result, the current mirror circuit 11B is activated, the amplification function of the differential amplifier circuit 31 is maintained, and the input signals IN1, IN
2 is differentially amplified. The differentially amplified signal level is based on the enable signal IN3 = “H” level as in the first and second differential input type receiving circuits.
Output to the internal circuit.

Therefore, like the first and second embodiments,
Even when the reception function is stopped by the enable signal IN3 = “L” level and the input signals IN1 and IN2 are supplied to the differential pair transistors TN3 and TN4, the differential amplifier circuit 31 when the reception is stopped It is possible to forcibly stop the transistor operation. As a result, the first and second
It is possible to suppress the power consumption of the differential amplifier circuit 31 when reception is stopped as much as possible as in the above embodiment, and it is possible to reduce the power consumption of the electronic device incorporating the differential input type receiving circuit. Becomes

(4) Description of Fourth Embodiment FIG. 11 is a configuration diagram of a differential input type receiving circuit according to a fourth embodiment of the present invention, and FIGS. 12 (A) and 12 (B) show the same. Each operation explanatory view is shown. The fourth embodiment is different from the first to third embodiments in that the first switching circuit 13B shown in the principle diagram of FIG. 3B has four n-type field effect transistors TN54. , TN64, TN74, TN84
Composed of.

That is, in FIG. 11, the transistor T
N54 is connected between the ground line GND and the gate of the differential pair transistor TN3, and transistor TN64 is connected between the ground line GND and the gate of the differential pair transistor TN4. Further, the transistor TN74 is connected between the supply section of the input signal IN1 and the gate of the differential pair transistor TN3, and the transistor TN84 is connected between the supply section of the input signal IN2 and the gate of the differential pair transistor TN4. . The inverter INV2 is connected to the gates of the transistors TN54 and TN64, the inverted signal of the enable signal IN3 is supplied, and the enable signal is supplied to the gates of the transistors TN74 and TN84.
IN3 is supplied. In addition, the constant current source transistor TN
1, differential pair transistors TN3, TN4, bias circuit 11
The A, the inverter INV1 and the three-state circuit 12 are the same as those in the first to third embodiments, and the description thereof will be omitted.

Thus, according to the differential input type receiving circuit of the fourth embodiment of the present invention, as shown in FIG.
Transistors TN54 and TN64 are connected between the gates of the differential pair transistors TN3 and TN4 and the ground line GND, and transistors TN74 and TN84 are connected between the supply parts of the input signals IN1 and IN2 and the gates of the transistors TN3 and TN4. Both transistors TN54 and TN64 are controlled based on the inverted signal of the enable signal IN3, and both transistors TN74 and T4 are controlled.
N84 is controlled based on the enable signal IN3.

For example, in the operation explanatory diagram of FIG. 12A, when the reception of the input signals IN1 and IN2 is stopped, the enable signal IN3 = is applied to the transistors TN54 and TN64.
By supplying the "L" level inversion signal, the transistors TN54 and TN64 are turned on, and the gates of the differential pair transistors TN3 and TN4 are fixed to the ground line GND level. Further, by supplying the enable signal IN3 = “L” level to the transistors TN74, TN84, the transistors TN74, TN84 perform an OFF operation, and both input signals IN
The supply of 1 and IN2 is cut off, the amplifying function of the differential amplifier circuit 41 is stopped, and at the same time, the output of the 3-state circuit 12 is set to the "Z" state based on the enable signal IN3 = "L" level.

When receiving the input signals IN1 and IN2, the enable signal IN3 = "H" level inverted signal is supplied to the transistors TN54 and TN64 in the operation explanatory diagram of FIG. The transistor TN54
, TN64 operates OFF, and the differential pair transistor TN3,
The gate of TN4 is released from the ground line GND level. Also, the enable signal IN3 is applied to the transistors TN74 and TN84.
= “H” level is supplied, the transistors TN74 and TN84 are turned on and both input signals IN1 and IN2 are turned on.
Are supplied to the gates of the differential pair transistors TN3 and TN4, respectively, and both input signals IN1 and IN2 are differentially amplified. Further, the differentially amplified signal level is 3 based on the enable signal IN3 = “H” level as in the first to third embodiments.
It is output from the state circuit 12 to the internal circuit.

Therefore, as in the first to third embodiments,
By the enable signal IN3 = “L” level, the reception function is stopped, and the gates of the differential pair transistors TN3 and TN4 are fixed to the “L” level, so that the amplification of the differential amplifier circuit 41 when the reception is stopped. It is possible to stop the operation. As a result, similarly to the first to third embodiments, it is possible to suppress the power consumption of the differential amplifier circuit 41 when reception is stopped as much as possible, and the power consumption of the electronic device incorporating the differential input type receiver circuit. Can be reduced.

(5) Description of the Fifth Embodiment FIG. 13 is an explanatory diagram of a differential input type receiving circuit according to the fifth embodiment of the present invention, and FIG. 13 (A) is its configuration diagram. , Figure
13 (B) is a diagram for explaining the operation. The fifth embodiment differs from the first to fourth embodiments in that
As shown in the principle diagram of FIG. 4A, the second switching circuit 13C is an n-type field effect transistor TN55, TN65.
Composed of.

That is, in FIG. 13A, the transistor TN55 is connected between the drain of the differential pair transistor TN3 and the drain of the transistor TP1 of the current mirror circuit, and the transistor TN65 is connected to the differential pair transistor T.
N4 drain and current mirror circuit transistor TP2
Connected to the drain of each. The enable signal IN3 is applied to the gates of both transistors TN55 and TN65.
Is supplied. Regarding the constant current source transistor TN1, the differential pair transistors TN3, TN4, the bias circuit 11A, the inverter INV1 and the three-state circuit 12,
-Since it is the same as the fourth embodiment, the description thereof is omitted.

In this way, according to the differential input type receiving circuit of the fifth embodiment of the present invention, as shown in FIG. 13A, the differential pair transistors TN3 and TN4 and the current mirror circuit are provided. Transistors TN55 and TN65 are connected between
It is controlled based on the enable signal IN3. For example, in the operation explanatory diagram of FIG.
When stopping the reception of IN2, the transistor TN55,
By supplying the enable signal IN3 = “L” level to the gate of TN65, both transistors TN55 and TN65 perform the OFF operation, and the current mirror circuit and the differential pair transistors TN3 and TN4 are disconnected. The amplification function of the differential amplifier circuit 51 is stopped, and at the same time, the enable signal IN
The output of the 3-state circuit 12 is set to the “Z” state based on 3 = “L” level.

When the input signals IN1 and IN2 are received, both transistors TN55 and TN65 are turned on by supplying the enable signal IN3 = “H” level to the gates of the transistors TN55 and TN65. The mirror circuit and the differential pair transistors TN3 and TN4 are connected, the amplification function of the differential amplification circuit 51 is maintained, and the input signal
IN1 and IN2 are differentially amplified. The differentially amplified signal level is the enable signal as in the first to fourth embodiments.
It is output from the 3-state circuit 12 to the internal circuit based on IN3 = "H" level.

Therefore, as in the first to fourth embodiments,
When the enable signal IN3 = "L" level, the reception function is stopped and both transistors TN55 and TN65 are turned off.
The FF operation makes it possible to stop the amplification operation of the differential amplifier circuit 51 when reception is stopped. As a result, similarly to the first to fourth embodiments, it is possible to suppress the power consumption of the differential amplifier circuit 51 when reception is stopped as much as possible, and the power consumption of the electronic device incorporating the differential input type receiver circuit. Can be reduced.

(6) Description of Sixth Embodiment FIG. 14 is an explanatory diagram of a differential input type receiving circuit according to a sixth embodiment of the present invention, and FIG. 14 (A) is its configuration diagram. , Figure
14B shows the operation explanatory diagrams thereof. The sixth embodiment differs from the first to fifth embodiments in that
As shown in the principle diagram of FIG. 4A, the second switching circuit 13C is a p-type field effect transistor TP46, TP56.
Composed of.

That is, in FIG. 14A, the transistor TP46 is connected between the drain of the differential pair transistor TN3 and the drain of the transistor TP1 of the current mirror circuit, and the transistor TP56 is connected to the differential pair transistor T.
N4 drain and current mirror circuit transistor TP2
Connected to the drain of each. Further, an inverter INV2 is connected to the gates of both transistors TP46 and TP56, and an inverted signal of the enable signal IN3 is supplied. The constant current source transistor TN1, differential pair transistors TN3 and TN4, bias circuit 11A, inverter INV
The 1- and 3-state circuits 12 are similar to those in the first to fifth embodiments, and therefore their explanations are omitted.

In this way, according to the differential input type receiving circuit of the sixth embodiment of the present invention, as shown in FIG. 14A, the differential pair transistors TN3 and TN4 and the current mirror circuit are provided. Transistors TP46 and TP56 are connected between
It is controlled based on the inverted signal of the enable signal IN3. For example, in the operation explanatory diagram of FIG. 14B, when the reception of the input signals IN1 and IN2 is stopped, the enable signal IN3 = is applied to the gates of the transistors TP46 and TP56.
By supplying the inverted signal of "L" level, both transistors TP46 and TP56 perform the OFF operation, the current mirror circuit and the differential pair transistors TN3 and TN4 are disconnected, and the differential amplifier circuit 61 is connected. The amplification function of the
At the same time, the output of the 3-state circuit 12 is set to the "Z" state based on the enable signal IN3 = "L" level.

When the input signals IN1 and IN2 are received, both transistors TP46 and TP56 are turned on by supplying an enable signal IN3 = "H" level inverted signal to the gates of the transistors TP46 and TP56. Then
The current mirror circuit and the differential pair transistors TN3 and TN4 are connected to maintain the amplification function of the differential amplifier circuit 61,
The input signals IN1 and IN2 are differentially amplified. The differentially amplified signal level is output from the three-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level as in the first to fourth embodiments.

Therefore, as in the first to fifth embodiments,
When the enable signal IN3 = "L" level, the reception function is stopped and both transistors TP46 and TP56 are turned off.
The FF operation makes it possible to stop the amplification operation of the differential amplifier circuit 61 when reception is stopped. As a result, it becomes possible to suppress the power consumption of the differential amplifier circuit 61 when reception is stopped as much as possible like the first to fifth embodiments, and the power consumption of the electronic device incorporating the differential input type receiver circuit. Can be reduced.

(7) Description of Seventh Embodiment FIG. 15 is a block diagram of a differential input type receiver circuit according to the seventh embodiment of the present invention. 15, in the seventh embodiment, a differential amplifier circuit 11 of the first embodiment is provided with an n-type field effect transistor TN9, an inverter INV3 and a delay circuit 14 to form a differential amplifier circuit 71.

That is, in FIG. 15, the n-type field effect transistor TN9 is another example of the function control element 13, and the drain (operating point a) of the differential pair transistor TN3 and the common gate (point d) of the inverter INV1. Is connected between the connection point and the ground line GND. Further, the inverted signal of the enable signal IN3 delayed by the delay circuit 14 is supplied to the gate of the transistor TN9. The constant current source transistor TN1, the differential pair transistors TN3 and TN4, the bias circuit 11A, the inverter INV1 and the three-state circuit 12
Since the above is the same as that of the first embodiment, the description thereof will be omitted.

As described above, according to the differential input type receiver circuit of the seventh embodiment of the present invention, the differential amplifier circuit 11 of the first embodiment has the n-type as shown in FIG. Field effect transistor TN9, inverter INV3 and delay circuit 14 of
Are provided to configure the differential amplifier circuit 71, and the transistor TN9 is controlled based on the delayed inverted signal of the enable signal IN3.

For example, when the reception of the input signals IN1 and IN2 is stopped, the transistor T is used as in the first embodiment.
By supplying the enable signal IN3 = “L” level to the gate of N51, the transistor TN51 performs the OFF operation, the amplification function of the differential amplifier circuit 11 is stopped, and at the same time,
The output of the 3-state circuit 12 is set to the "Z" state based on the enable signal IN3 = "L" level.

Here, a signal "H" level obtained by delaying and inverting the enable signal IN3 is supplied to the transistor TN9,
By turning on the transistor TN9, the common gate of the inverter INV1 is fixed to the “L” level. When the input signals IN1 and IN2 are received, the enable signal IN3 = "H" level is supplied to the gate of the transistor TN51 so that the transistor TN51 is turned on.
The differential amplifier circuit 11 operates and the amplifying function of the differential amplifier circuit 11 is maintained, and the input signals IN1 and IN2 are differentially amplified.

Here, the signal = "L" level obtained by delaying and inverting the enable signal IN3 is supplied to the transistor TN9, so that the transistor TN9 performs the OFF operation, so that the common gate of the inverter INV1 changes from the "L" level. It will be released. Further, the differentially amplified signal level is output from the three-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level.

Therefore, as compared with the first embodiment, the receiving function is stopped and the transistor TN9 connected to the inverter INV1 is turned on by the inversion signal of the enable signal IN3 = “L” level. Stopping the amplifying operation of the differential amplifier circuit 71 when reception is stopped,
Also, the amplification operation of the inverter INV1 can be stopped together. In particular, by supplying the delayed inverted signal of the enable signal IN3 to the gate of the n-type field effect transistor TN9 connected to the inverter INV1, the potential level at the operating point a of the differential amplifier circuit 71 is changed to the inverter INV1.
After reaching the threshold voltage Vth of 1, the inverter INV
Can be supplied to one common gate.

As a result, compared with the first embodiment, the power consumption of the differential amplifier circuit 71 when reception is stopped can be further suppressed and the performance can be improved. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (8) Description of Eighth Embodiment FIG. 16 is a configuration diagram of a differential input type reception circuit according to an eighth embodiment of the present invention. 16, in the eighth embodiment, a differential amplifier circuit 21 of the second embodiment is provided with an n-type field effect transistor TN9, an inverter INV3 and a delay circuit 14 to form a differential amplifier circuit 81.

The transistor TN9 and the inverter INV
3 and the delay circuit 14 are connected in the same way as in the seventh embodiment, and the constant current source transistor TN1, the differential pair transistors TN3 and TN4, the bias circuit 11A, the bias control circuit 13A, the inverter INV1 and the three states are connected. The circuit 12 is the same as that of the second embodiment, so its explanation is omitted.

In this way, according to the differential input type receiving circuit of the eighth embodiment of the present invention, the differential amplifier circuit 21 of the second embodiment has the n-type as shown in FIG. Field effect transistor TN9, inverter INV3 and delay circuit 14 of
Are provided to configure the differential amplifier circuit 81. Further, the transistor TN9 is controlled based on the delayed inverted signal of the enable signal IN3.

For example, when the reception of the input signals IN1 and IN2 is stopped, by supplying the enable signal IN3 = "L" level to the bias supply control circuit 13A, the transistor TN52 is supplied as in the second embodiment. Turned off,
The bias circuit 11A and the constant current source Io are disconnected from each other, and the transistor TN62 is turned on to supply the "L" level to the transistor TN1. As a result, the amplifying function of the differential amplifier circuit 81 is stopped, and at the same time, the output of the 3-state circuit 12 is set to the "Z" state based on the enable signal IN3 = "L" level.

Here, a signal "H" level obtained by delaying and inverting the enable signal IN3 is supplied to the transistor TN9,
By turning on the transistor TN9, the common gate of the inverter INV1 is fixed to the “L” level. When the input signals IN1 and IN2 are received, the enable signal IN3 = "H" level is supplied to the bias supply control circuit 13A to activate the control circuit 13A, as in the second embodiment. Then, the bias circuit 11A and the constant current source Io are connected, the amplifying function of the differential amplifier circuit 21 is maintained, and the input signals IN1 and IN2 are differentially amplified.

Here, the signal = "L" level obtained by delaying and inverting the enable signal IN3 is supplied to the transistor TN9 so that the transistor TN9 performs the OFF operation, so that the common gate of the inverter INV1 is changed from the "L" level. It will be released. Further, the differentially amplified signal level is output from the three-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level.

Therefore, as compared with the second embodiment, the receiving function is stopped and the transistor TN9 connected to the inverter INV1 is turned on by the inversion signal of the enable signal IN3 = “L” level. Stopping the amplifying operation of the differential amplifier circuit 81 when reception is stopped,
Also, the amplification operation of the inverter INV1 can be stopped together. In particular, by supplying the delayed inverted signal of the enable signal IN3 to the gate of the n-type field effect transistor TN9 connected to the inverter INV1, the potential level of the operating point a of the differential amplifier circuit 81 is changed to the inverter INV1.
After reaching the threshold voltage Vth of 1, the inverter INV
Can be supplied to one common gate.

As a result, compared with the second embodiment, it is possible to further suppress the power consumption of the differential amplifier circuit 81 when reception is stopped and to improve the performance. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (9) Description of Ninth Embodiment FIG. 17 is a configuration diagram of a differential input type receiver circuit according to a ninth embodiment of the present invention. 17, in the ninth embodiment, a differential amplifier circuit 31 of the third embodiment is provided with an n-type field effect transistor TN9, an inverter INV3 and a delay circuit 14 to form a differential amplifier circuit 91. The method of connecting the transistor TN9, the inverter INV3 and the delay circuit 14 is the same as in the seventh and eighth embodiments, and the constant current source transistor TN1, the differential pair transistors TN3 and TN4, the inverter INV1 and the p-type are used. Field effect transistor TP43,
The n-type field effect transistor TN53 and the three-state circuit 12 are the same as those in the third embodiment, and therefore their explanations are omitted.

In this way, according to the differential input type receiver circuit of the ninth embodiment of the present invention, the differential amplifier circuit 31 of the third embodiment has the same n-type as shown in FIG. Field effect transistor TN9, inverter INV3 and delay circuit 14 of
Are provided to configure the differential amplifier circuit 91. Further, the transistor TN9 is controlled based on the delayed inverted signal of the enable signal IN3.

For example, when the reception of the input signals IN1 and IN2 is stopped, the transistor T is used as in the third embodiment.
By supplying the enable signal IN3 = "L" level to the gates of P43 and TN53, the transistor TP43 is turned on.
Then, the transistor TN53 is turned off. As a result, the transistors TP1 and TP2 perform an OFF operation, the current mirror circuit 11B is deactivated, and the differential amplifier circuit 91
The amplification function of is stopped, and at the same time, enable signal IN3 =
The output of the 3-state circuit 12 is "based on the" L "level.
Z ”state.

Here, the signal = "H" level obtained by delaying and inverting the enable signal IN3 is supplied to the transistor TN9,
By turning on the transistor TN9, the common gate of the inverter INV1 is fixed to the “L” level. When receiving the input signals IN1 and IN2, the enable signal IN3 = “H” level is supplied to the gates of the transistors TP43 and TN53 as in the third embodiment, so that the transistor TP43 is turned off. Then, the transistor TN53 turns on. As a result, the current mirror circuit 11B is activated, the amplification function of the differential amplifier circuit 31 is maintained, and the input signals IN1 and IN2 are differentially amplified.

Here, the signal ‘L’ level obtained by delaying and inverting the enable signal IN3 is supplied to the transistor TN9, so that the transistor TN9 performs the OFF operation, so that the common gate of the inverter INV1 changes from the “L” level to It will be released. Further, the differentially amplified signal level is output from the three-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level.

Therefore, as compared with the third embodiment, the receiving function is stopped and the transistor TN9 connected to the inverter INV1 is turned on by the inversion signal of the enable signal IN3 = “L” level. Stopping the amplification operation of the differential amplifier circuit 91 when reception is stopped,
Also, the amplification operation of the inverter INV1 can be stopped together. In particular, by supplying the delayed inverted signal of the enable signal IN3 to the gate of the n-type field effect transistor TN9 connected to the inverter INV1, the potential level at the operating point a of the differential amplifier circuit 91 is changed to the inverter INV1.
After reaching the threshold voltage Vth of 1, the inverter INV
Can be supplied to one common gate.

As a result, as compared with the third embodiment, it is possible to further suppress the power consumption of the differential amplifier circuit 91 when reception is stopped and to improve the performance. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (10) Description of Tenth Embodiment FIG. 18 is a configuration diagram of a differential input type receiver circuit according to a tenth embodiment of the present invention. In FIG. 18, in the tenth embodiment, a differential amplifier circuit 41 of the fourth embodiment is provided with an n-type field effect transistor TN9, an inverter INV3 and a delay circuit 14 to form a differential amplifier circuit 100. The method of connecting the transistor TN9, the inverter INV3 and the delay circuit 14 is the same as in the seventh to ninth embodiments, and the constant current source transistor TN1, the differential pair transistors TN3, TN4, the inverters INV1, n type are connected. Field effect transistor TN54,
The TN64, TN74, TN84, the inverter INV2, and the three-state circuit 12 are the same as those in the fourth embodiment, and therefore their explanations are omitted.

In this way, according to the differential input type receiving circuit of the tenth embodiment of the present invention, the differential amplifier circuit 41 of the fourth embodiment has the n-type as shown in FIG. Field effect transistor TN9, inverter INV3 and delay circuit 14 of
Are provided, and the differential amplifier circuit 100 is configured. Further, the transistor TN9 is controlled based on the delayed inverted signal of the enable signal IN3.

For example, when the reception of the input signals IN1 and IN2 is stopped, the transistor T is used as in the fourth embodiment.
By supplying the enable signal IN3 = "L" level inverted signal to N54 and TN64,
TN64 turns on and differential pair transistors TN3 and TN4
Is fixed to the ground line GND level. The enable signal IN3 = "L" is applied to the transistors TN74 and TN84.
By supplying a level, the transistor TN74,
TN84 operates OFF, the supply of both input signals IN1 and IN2 is cut off, the amplifying function of the differential amplifier circuit 41 is stopped, and at the same time, the output of the 3-state circuit 12 based on the enable signal IN3 = “L” level. Is brought to the "Z" state.

Here, the signal = "H" level obtained by delaying and inverting the enable signal IN3 is supplied to the transistor TN9,
By turning on the transistor TN9, the common gate of the inverter INV1 is fixed to the “L” level. When receiving the input signals IN1 and IN2, as in the fourth embodiment, the enable signal IN3 = "H" level inverted signal is supplied to the transistors TN54 and TN64 so that the transistors TN54 and TN64 are supplied. Turned off,
The gates of the differential pair transistors TN3 and TN4 are released from the ground line GND level. Also, the transistors TN74, TN8
By supplying the enable signal IN3 = "H" level to 4, the transistors TN74 and TN84 are turned on, and both input signals IN1 and IN2 are connected to the differential pair transistor TN3,
Both input signals IN1 and IN are supplied to the gate of TN4 respectively.
2 is differentially amplified.

Here, the signal = "L" level obtained by delaying and inverting the enable signal IN3 is supplied to the transistor TN9, so that the transistor TN9 performs the OFF operation, so that the common gate of the inverter INV1 changes from the "L" level. It will be released. The differentially amplified signal levels are
Similar to the third embodiment, it is output from the 3-state circuit 12 to the internal circuit based on the enable signal IN3 = "H" level.

Therefore, as compared with the fourth embodiment, the receiving function is stopped and the transistor TN9 connected to the inverter INV1 is turned on by the inversion signal of the enable signal IN3 = “L” level. Stopping the amplifying operation of the differential amplifier circuit 100 when the reception is stopped,
Also, the amplification operation of the inverter INV1 can be stopped together. In particular, by supplying the delayed inverted signal of the enable signal IN3 to the gate of the n-type field effect transistor TN9 connected to the inverter INV1, the potential level of the operating point a of the differential amplifier circuit 100 is changed to the inverter INV1.
After reaching the threshold voltage Vth of 1, the inverter INV
Can be supplied to one common gate.

As a result, as compared with the fourth embodiment, it is possible to further suppress the power consumption of the differential amplifier circuit 100 when the reception is stopped and to improve the performance. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (11) Description of Eleventh Embodiment FIG. 19 is a configuration diagram of a differential input type reception circuit according to an eleventh embodiment of the present invention. In FIG. 19, in the eleventh embodiment, the differential amplifier circuit 11 of the first embodiment is provided with a p-type field effect transistor TP5 and a delay circuit 14,
Make up 111.

That is, in FIG. 19, the p-type field effect transistor TP5 is another example of the function control element 13, and the drain of the differential pair transistor TN3 (operating point a) and the common gate of the inverter INV1 (point d). Is connected between the connection point and the power supply line VCC. The enable signal IN3 delayed by the delay circuit 14 is supplied to the gate of the transistor TP5. The constant current source transistor T
N1, differential pair transistors TN3, TN4, bias circuit 11
The A, the inverter INV1 and the three-state circuit 12 are the same as those in the first embodiment, and therefore their explanations are omitted.

In this way, according to the differential input type receiver circuit of the eleventh embodiment of the present invention, the differential amplifier circuit 11 of the first embodiment has the p-type as shown in FIG. The field effect transistor TP5 and the delay circuit 14 are provided to configure the differential amplifier circuit 111. Further, the transistor TP5 is controlled based on the delay signal of the enable signal IN3. For example, to stop receiving the input signals IN1 and IN2,
Similar to the first embodiment, by supplying the enable signal IN3 = "L" level to the gate of the transistor TN51, the transistor TN51 performs the OFF operation, the amplifying function of the differential amplifier circuit 11 is stopped, and at the same time, , Enable signal
The output of the 3-state circuit 12 is set to the "Z" state based on IN3 = "L" level. Here, the signal "L" level obtained by delaying the enable signal IN3 is supplied to the transistor TP5, and the transistor TP5 is turned on,
The common gate of the inverter INV1 is fixed to "H" level.

When receiving the input signals IN1 and IN2, the enable signal IN is applied to the gate of the transistor TN51.
By supplying 3 = “H” level, the transistor TN51 is turned on, the amplifying function of the differential amplifier circuit 11 is maintained, and the input signals IN1 and IN2 are differentially amplified. When the signal = "H" level obtained by delaying the enable signal IN3 is supplied to the transistor TP5, the transistor TP5 performs the OFF operation, and the common gate of the inverter INV1 is released from the "H" level. Further, the differentially amplified signal level is output from the three-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level.

Therefore, as compared with the first embodiment, the delay function of the enable signal IN3 = "L" level causes the reception function to be stopped and the transistor TP5 connected to the inverter INV1 to be turned on. Stopping the amplifying operation of the differential amplifier circuit 111 when reception is stopped,
Also, the amplification operation of the inverter INV1 can be stopped together. In particular, by supplying the delay signal of the enable signal IN3 to the gate of the p-type field effect transistor TP5 connected to the inverter INV1, the potential level at the operating point a of the differential amplifier circuit 111 becomes the threshold voltage Vth of the inverter INV1. Once reached, it can be fed to the common gate of inverter INV1.

As a result, compared with the first embodiment, the power consumption of the differential amplifier circuit 111 when reception is stopped can be further suppressed and the performance can be improved. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (12) Description of Twelfth Embodiment FIG. 20 is a configuration diagram of a differential input type reception circuit according to a twelfth embodiment of the present invention. 20, in the twelfth embodiment, the differential amplifier circuit 21 of the second embodiment is provided with a p-type field effect transistor TP5 and a delay circuit 14,
Make up 112.

The method of connecting the p-type field effect transistor TP5 and the delay circuit 14 is the same as in the eleventh embodiment. Further, the constant current source transistor TN1, the differential pair transistors TN3 and TN4, the bias circuit 11A, the bias control circuit 13A, the inverter INV1 and the three-state circuit 1
Since No. 2 is similar to that of the second embodiment, its explanation is omitted.

As described above, according to the differential input type receiver circuit of the twelfth embodiment of the present invention, the differential amplifier circuit 21 of the second embodiment has the p-type as shown in FIG. The field effect transistor TP5 and the delay circuit 14 are provided to configure the differential amplifier circuit 112. Further, the transistor TP5 is controlled based on the delay signal of the enable signal IN3. For example, to stop receiving the input signals IN1 and IN2,
As in the second embodiment, by supplying the enable signal IN3 = "L" level to the bias supply control circuit 13A, the transistor TN52 is turned off as in the second embodiment.
By operating the bias circuit 11A and the constant current source Io in a non-connected state, and turning on the transistor TN62, an "L" level is supplied to the transistor TN1. As a result, the amplifying function of the differential amplifier circuit 112 is stopped, and at the same time, the output of the 3-state circuit 12 is set to the "Z" state based on the enable signal IN3 = "L" level.

Here, the signal "L" level obtained by delaying the enable signal IN3 is supplied to the transistor TP5, and the transistor TP5 is turned on, whereby the inverter I
The common gate of NV1 is fixed at "H" level. In addition,
When the input signals IN1 and IN2 are received, the enable signal is sent to the bias supply control circuit 13A as in the second embodiment.
By supplying IN3 = “H” level, the control circuit
13A activates, bias circuit 11A and constant current source Io
Are connected, the amplification function of the differential amplifier circuit 21 is maintained, and the input signals IN1 and IN2 are differentially amplified.

When the signal = "H" level obtained by delaying the enable signal IN3 is supplied to the transistor TP5, the transistor TP5 performs the OFF operation and the inverter TP5 is turned off.
The common gate of INV1 is released from "H" level. The differentially amplified signal level is the enable signal IN3 =
It is output from the 3-state circuit 12 to the internal circuit based on the "H" level.

Therefore, as compared with the second embodiment, the enable function IN3 = "L" level delay signal causes the reception function to be stopped and the transistor TP5 connected to the inverter INV1 to be turned on. Stopping the amplification operation of the differential amplifier circuit 112 when reception is stopped,
Also, the amplification operation of the inverter INV1 can be stopped together. In particular, by supplying the delay signal of the enable signal IN3 to the gate of the p-type field effect transistor TP5 connected to the inverter INV1, the potential level at the operating point a of the differential amplifier circuit 112 becomes the threshold voltage Vth of the inverter INV1. Once reached, it can be fed to the common gate of inverter INV1.

As a result, compared with the second embodiment, it is possible to further suppress the power consumption of the differential amplifier circuit 112 when reception is stopped and to improve the performance. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (13) Description of Thirteenth Embodiment FIG. 21 is a configuration diagram of a differential input type reception circuit according to a thirteenth embodiment of the present invention. 21, in the thirteenth embodiment, a p-type field effect transistor TP5 and a delay circuit 14 are provided in the differential amplifier circuit 31 of the third embodiment, and the differential amplifier circuit
Make up 113.

The method of connecting the p-type field effect transistor TP5 and the delay circuit 14 is the same as in the eleventh and twelfth embodiments. In addition, the constant current source transistor TN1,
Differential pair transistors TN3, TN4, bias circuit 11A, inverter INV1, p-type field effect transistor TP43,
The n-type field effect transistor TN53 and the three-state circuit 12 are the same as those in the third embodiment, and therefore their explanations are omitted.

Thus, according to the differential input type receiving circuit of the thirteenth embodiment of the present invention, the differential amplifier circuit 31 of the third embodiment has the p-type as shown in FIG. The field effect transistor TP5 and the delay circuit 14 are provided to configure the differential amplifier circuit 113. Further, the transistor TP5 is controlled based on the delay signal of the enable signal IN3. For example, to stop receiving the input signals IN1 and IN2,
As in the third embodiment, by supplying the enable signal IN3 = "L" level to the gates of the transistors TP43 and TN53, the transistor TP43 is turned on and the transistor TN53 is turned off. As a result, the transistors TP1 and TP2 perform the OFF operation and the current mirror circuit
11B is deactivated, the amplifying function of the differential amplifier circuit 113 is stopped, and at the same time, the output of the 3-state circuit 12 is set to the "Z" state based on the enable signal IN3 = "L" level.

Here, the signal "L" level obtained by delaying the enable signal IN3 is supplied to the transistor TP5, and the transistor TP5 is turned on, whereby the inverter I
The common gate of NV1 is fixed at "H" level. In addition,
When receiving the input signals IN1 and IN2, the enable signal IN3 = “H” level is supplied to the gates of the transistors TP43 and TN53 as in the third embodiment.
The transistor TP43 operates OFF, and the transistor TN5
3 turns ON. This makes the current mirror circuit
11B is activated, the amplification function of the differential amplifier circuit 31 is maintained, and the input signals IN1 and IN2 are differentially amplified.

When the signal = "H" level obtained by delaying the enable signal IN3 is supplied to the transistor TP5, the transistor TP5 performs the OFF operation and the inverter TP5 is turned off.
The common gate of INV1 is released from "H" level. The differentially amplified signal level is the enable signal IN3 =
It is output from the 3-state circuit 12 to the internal circuit based on the "H" level.

Therefore, as compared with the third embodiment, the delay function of the enable signal IN3 = "L" level causes the reception function to be stopped and the transistor TP5 connected to the inverter INV1 to be turned on. Stopping the amplification operation of the differential amplifier circuit 113 when reception is stopped,
Also, the amplification operation of the inverter INV1 can be stopped together. In particular, by supplying the delay signal of the enable signal IN3 to the gate of the p-type field effect transistor TP5 connected to the inverter INV1, the potential level at the operating point a of the differential amplifier circuit 113 becomes the threshold voltage Vth of the inverter INV1. Once reached, it can be fed to the common gate of inverter INV1.

As a result, compared with the third embodiment, the power consumption of the differential amplifier circuit 113 when reception is stopped can be further suppressed and the performance can be improved. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (14) Description of Fourteenth Embodiment FIG. 22 is a configuration diagram of a differential input type reception circuit according to a fourteenth embodiment of the present invention. 22, in the fourteenth embodiment, the differential amplifier circuit 41 of the third embodiment is provided with a p-type field effect transistor TP5 and a delay circuit 14,
Make up 114.

The method of connecting the p-type field effect transistor TP5 and the delay circuit 14 is the same as in the eleventh to thirteenth embodiments. In addition, the constant current source transistor TN1,
Differential pair transistors TN3, TN4, bias circuit 11A, inverter INV1, n-type field effect transistor TN54,
The TN64, TN74, TN84 and the three-state circuit 12 are the same as those in the fourth embodiment, so the description thereof will be omitted.

Thus, according to the differential input type receiving circuit of the fourteenth embodiment of the present invention, the differential amplifier circuit 41 of the fourth embodiment has the p-type as shown in FIG. The field effect transistor TP5 and the delay circuit 14 are provided to configure a differential amplifier circuit 114. Further, the transistor TP5 is controlled based on the delay signal of the enable signal IN3. For example, to stop receiving the input signals IN1 and IN2,
Similar to the fourth embodiment, by supplying the enable signal IN3 = "L" level inverted signal to the transistors TN54 and TN64, the transistors TN54 and TN64 are turned on, and the differential pair transistors TN3 and TN4 are turned on. The gate is fixed to the ground line GND level. Also, the transistor TN74
, TN84 are supplied with an enable signal IN3 = “L” level, so that the transistors TN74, TN84 are turned off.
It operates, the supply of both input signals IN1 and IN2 is cut off, the amplifying function of the differential amplifier circuit 41 is stopped, and at the same time, the 3-state circuit 1 is operated based on the enable signal IN3 = “L” level.
The output of 2 is put in the "Z" state.

Here, the signal "L" level obtained by delaying the enable signal IN3 is supplied to the transistor TP5, and the transistor TP5 is turned on, whereby the inverter I
The common gate of NV1 is fixed at "H" level. In addition,
When the input signals IN1 and IN2 are received, as in the fourth embodiment, the enable signal IN3 = "H" level inverted signal is supplied to the transistors TN54 and TN64 so that the transistors TN54 and TN64 are turned off. In operation, the gates of the differential pair transistors TN3 and TN4 are released from the level of the ground line GND. Also, the transistors TN74, TN84
By supplying the enable signal IN3 = “H” level to the transistors TN74 and TN84, the transistors TN74 and TN84 are turned on,
Both input signals IN1 and IN2 are differential pair transistors TN3 and TN4
Of the input signals IN1 and IN2 are differentially amplified.

When the signal = "H" level obtained by delaying the enable signal IN3 is supplied to the transistor TP5, the transistor TP5 performs the OFF operation and the inverter TP5
The common gate of INV1 is released from "H" level. The differentially amplified signal level is the enable signal IN3 =
It is output from the 3-state circuit 12 to the internal circuit based on the "H" level.

Therefore, compared with the fourth embodiment, the receiving function is stopped by the enable signal IN3 = “L” level delay signal, and the transistor TP5 connected to the inverter INV1 is turned on. Stopping the amplification operation of the differential amplifier circuit 114 when reception is stopped,
Also, the amplification operation of the inverter INV1 can be stopped together. In particular, by supplying the delay signal of the enable signal IN3 to the gate of the p-type field effect transistor TP5 connected to the inverter INV1, the potential level of the operating point a of the differential amplifier circuit 114 becomes the threshold voltage Vth of the inverter INV1. Once reached, it can be fed to the common gate of inverter INV1.

As a result, compared with the fourth embodiment, the power consumption of the differential amplifier circuit 114 when reception is stopped can be further suppressed and the performance can be improved. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (15) Description of Fifteenth Embodiment FIG. 23 is a configuration diagram of a differential input type reception circuit according to a fifteenth embodiment of the present invention. In FIG. 23, in the fifteenth embodiment, an inverter INV1 of the first embodiment is provided with an n-type field effect transistor TN10 to form a differential amplifier circuit 115.

That is, in FIG. 23, the n-type field effect transistor TN10 is another example of the function control element 13, and is connected between the transistors TP3 and TN2 of the inverter INV1. The enable signal IN3 is supplied to the gate of the transistor TN10. The constant current source transistor TN1, the transistor TN3 of the differential amplifier circuit 11,
The TN4, the bias circuit 11A, and the three-state circuit 12 are the same as those in the first embodiment, and therefore their explanations are omitted.

As described above, according to the differential input type receiver circuit of the fifteenth embodiment of the present invention, the inverter INV1 of the first embodiment has the n-type field effect as shown in FIG. A transistor TN10 is provided, and a differential amplifier circuit 115 including an inverter INV4 is constructed. Further, the transistor TN10 is controlled based on the enable signal IN3. For example, to stop receiving the input signals IN1 and IN2,
As in the first embodiment, by supplying the enable signal IN3 = “L” level to the gate of the transistor TN51, the transistor TN51 performs the OFF operation, the differential amplification function is stopped, and at the same time, the enable signal IN3. The output of the 3-state circuit 12 is set to the "Z" state based on the "L" level. Here, the enable signal IN3 = "L" level is supplied to the transistor TN10, and the transistor TN1
When 0 turns off, the amplification function of the inverter INV1 is stopped.

When receiving the input signals IN1 and IN2, the enable signal IN is applied to the gate of the transistor TN51.
By supplying 3 = “H” level, the transistor TN51 is turned on, the differential amplification function is maintained, and the input signals IN1 and IN2 are differentially amplified. When the enable signal IN3 = "H" level is supplied to the transistor TN10, the transistor TN10 is turned on, the amplifying function of the inverter INV1 is maintained, and the differentially amplified signal level is the enable signal IN3 =. It is output from the 3-state circuit 12 to the internal circuit based on the "H" level.

Therefore, as compared with the first embodiment, the delay function of the enable signal IN3 = "L" level causes the reception function to be stopped and the transistor TN10 connected to the inverter INV1 to perform the OFF operation. It is possible to stop the differential amplification operation when reception is stopped and also stop the amplification operation of the inverter INV1.

As a result, compared with the first embodiment, it is possible to further suppress the power consumption of the differential amplifier circuit 115 when reception is stopped and to improve the performance. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (16) Description of Sixteenth Embodiment FIG. 24 is a configuration diagram of a differential input type reception circuit according to a sixteenth embodiment of the present invention. In FIG. 24, in the sixteenth embodiment, an inverter INV1 of the second embodiment is provided with an n-type field effect transistor TN10 to form a differential amplifier circuit 116.

The n-type field effect transistor TN10
The connection method of is similar to that of the fifteenth embodiment. Further, the constant current source transistor TN1, the differential pair transistors TN3 and TN4, the bias circuit 11A, the bias control circuit 13
The A, the inverter INV4, and the three-state circuit 12 are similar to those in the second and fifteenth embodiments, and the description thereof will be omitted.

As described above, according to the differential input type receiver circuit of the sixteenth embodiment of the present invention, the inverter INV1 of the second embodiment has the n-type field effect as shown in FIG. The transistor TN10 is provided, and the differential amplifier circuit 116 is configured. Also, the transistor TN10 is an enable signal.
Controlled based on IN3. For example, input signals IN1, IN
When the reception of 2 is stopped, as in the second embodiment,
Enable signal IN3 = to bias supply control circuit 13A
By supplying the "L" level, the transistor TN52 performs the OFF operation as in the second embodiment, and the bias circuit 11A and the constant current source Io are disconnected, and
When the transistor TN62 is turned on, the "L" level is supplied to the transistor TN1. As a result, the amplification function of the differential amplifier circuit 112 is stopped, and at the same time, the 3-state circuit 1 is driven based on the enable signal IN3 = "L" level.
The output of 2 is put in the "Z" state.

Here, the enable signal IN3 = "L" level is supplied to the transistor TN10,
When N10 turns off, the amplification function of the inverter INV1 is stopped. When the input signals IN1 and IN2 are received, the enable signal IN3 = "H" level is supplied to the bias supply control circuit 13A to activate the control circuit 13A, as in the second embodiment. The bias circuit 11A and the constant current source Io are connected, and the differential amplifier circuit
The amplification function of 116 is maintained, and the input signals IN1 and IN2 are differentially amplified.

When the enable signal IN3 = "H" level is supplied to the transistor TN10, the transistor TN10 is turned on, the amplifying function of the inverter INV4 is maintained, and the differentially amplified signal level is enabled. The signal is output from the 3-state circuit 12 to the internal circuit based on the signal IN3 = "H" level. Therefore, compared with the second embodiment, the reception function is stopped by the enable signal IN3 = "L" level delay signal and the inverter I
Since the transistor TN10 connected to NV4 performs the OFF operation, it is possible to stop the differential amplification operation when reception is stopped and also stop the amplification operation of the inverter INV4.

As a result, compared with the second embodiment, the power consumption of the differential amplifier circuit 116 when reception is stopped can be further suppressed and the performance can be improved. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (17) Description of Seventeenth Embodiment FIG. 25 is a configuration diagram of a differential input type receiver circuit according to a seventeenth embodiment of the present invention. In FIG. 25, in the seventeenth embodiment, the inverter INV1 of the third embodiment is provided with an n-type field effect transistor TN10 to form a differential amplifier circuit 117.

The n-type field effect transistor TN10
The connection method is the same as in the fifteenth and sixteenth embodiments. In addition, a constant current source transistor TN1, a differential pair transistor TN3, TN4, a bias circuit 11A, an inverter INV.
The 5, p-type field effect transistor TP43, the n-type field effect transistor TN53, and the three-state circuit 12 are the same as those in the third and sixteenth embodiments, and the description thereof will be omitted.

Thus, according to the differential input type receiver circuit of the seventeenth embodiment of the present invention, the inverter INV1 of the third embodiment has an n-type field effect as shown in FIG. The transistor TN10 is provided and the differential amplifier circuit 117 is configured. Also, the transistor TN10 is an enable signal.
Controlled based on IN3. For example, input signals IN1, IN
When the reception of 2 is stopped, as in the third embodiment,
Enable signal to the gates of transistors TP43 and TN53
By supplying IN3 = "L" level, the transistor TP43 is turned on and the transistor TN53 is turned off. As a result, the transistors TP1 and TP2 are turned off.
The current mirror circuit 11B is activated to deactivate, the amplification function of the differential amplifier circuit 113 is stopped, and at the same time, the output of the 3-state circuit 12 is "Z" based on the enable signal IN3 = "L" level. Be put in a state.

Here, the enable signal IN3 = "L" level is supplied to the transistor TN10, and the transistor T10 is turned on.
When N10 turns off, the amplification function of the inverter INV1 is stopped. When receiving the input signals IN1 and IN2, the transistor TP4 is used as in the third embodiment.
By supplying the enable signal IN3 = “H” level to the gates of 3 and TN53, the transistor TP43 performs the OFF operation and the transistor TN53 performs the ON operation. As a result, the current mirror circuit 11B is activated, the amplification function of the differential amplifier circuit 31 is maintained, and the input signals IN1 and IN2 are differentially amplified.

When the enable signal IN3 = "H" level is supplied to the transistor TN10, the transistor TN10 is turned on, the amplifying function of the inverter INV4 is maintained, and the differentially amplified signal level is maintained. Is output from the 3-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level. Therefore, the third
Compared with the embodiment described above, the reception function is stopped by the delay signal of the enable signal IN3 = “L” level, and the transistor TN10 connected to the inverter INV4 performs the OFF operation, so that the differential amplification when the reception is stopped is performed. It is possible to stop the operation and also stop the amplification operation of the inverter INV4.

As a result, compared with the third embodiment, it is possible to further suppress the power consumption of the differential amplifier circuit 117 when reception is stopped and to improve the performance. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (18) Description of 18th Embodiment FIG. 26 is a block diagram of a differential input type receiver circuit according to an 18th embodiment of the present invention. In FIG. 26, in the eighteenth embodiment, an inverter INV1 of the fourth embodiment is provided with an n-type field effect transistor TN10 to form a differential amplifier circuit 118.

The n-type field effect transistor TN10
The connection method is the same as in the fifteenth and sixteenth embodiments. In addition, a constant current source transistor TN1, a differential pair transistor TN3, TN4, a bias circuit 11A, an inverter INV.
2, inverter INV4, n-type field effect transistor T
N54, TN64, TN74, TN84 and 3-state circuit 12
With respect to, since the same as in the fourth and sixteenth embodiments, description thereof will be omitted.

As described above, according to the differential input type receiver circuit of the eighteenth embodiment of the present invention, the n-type field effect as shown in FIG. 26 is applied to the inverter INV1 of the fourth embodiment. The transistor TN10 is provided to configure the differential amplifier circuit 118. Also, the transistor TN10 is an enable signal.
Controlled based on IN3. For example, input signals IN1, IN
When the reception of 2 is stopped, as in the fourth embodiment,
Enable signal IN3 = to transistors TN54 and TN64.
By supplying the "L" level inversion signal, the transistors TN54 and TN64 are turned on, and the gates of the differential pair transistors TN3 and TN4 are fixed to the ground line GND level. Further, by supplying the enable signal IN3 = “L” level to the transistors TN74, TN84, the transistors TN74, TN84 perform an OFF operation, and both input signals IN
The supply of 1 and IN2 is cut off, the amplifying function of the differential amplifier circuit 41 is stopped, and at the same time, the output of the 3-state circuit 12 is set to the "Z" state based on the enable signal IN3 = "L" level.

Here, the enable signal IN3 = "L" level is supplied to the transistor TN10,
When N10 turns off, the amplification function of the inverter INV1 is stopped. When receiving the input signals IN1 and IN2, the transistor TN5 is used as in the fourth embodiment.
By supplying an enable signal IN3 = "H" level inverted signal to the transistors TN54 and TN64,
N64 performs the OFF operation, and the gates of the differential pair transistors TN3 and TN4 are released from the level of the ground line GND. Further, the enable signal IN3 = "H" is applied to the transistors TN74 and TN84.
By supplying a level, the transistor TN74,
TN84 is turned on, both input signals IN1 and IN2 are supplied to the gates of the differential pair transistors TN3 and TN4, respectively.
Both input signals IN1 and IN2 are differentially amplified.

When the enable signal IN3 = "H" level is supplied to the transistor TN10, the transistor TN10 is turned on, the amplifying function of the inverter INV4 is maintained, and the differentially amplified signal level is maintained. Is output from the 3-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level. Therefore, the fourth
Compared with the embodiment described above, the reception function is stopped by the delay signal of the enable signal IN3 = “L” level, and the transistor TN10 connected to the inverter INV4 performs the OFF operation, so that the differential amplification when the reception is stopped is performed. It is possible to stop the operation and also stop the amplification operation of the inverter INV4.

As a result, compared with the fourth embodiment, the power consumption of the differential amplifier circuit 118 when reception is stopped can be further suppressed and the performance can be improved. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (19) Description of Nineteenth Embodiment FIG. 27 is a configuration diagram of a differential input type receiver circuit according to a nineteenth embodiment of the present invention. In FIG. 27, in the nineteenth embodiment, a p-type field effect transistor TP6 is provided in the inverter INV1 of the first embodiment to form a differential amplifier circuit 119.

That is, in FIG. 23, the p-type field effect transistor TP6 is another example of the function control element 13, and is connected between the transistors TP3 and TN2 of the inverter INV1. Further, the inverted signal of the enable signal IN3 is supplied to the gate of the transistor TP6. The constant current source transistor TN1, the differential pair transistor TN3, TN
4, the bias circuit 11A and the three-state circuit 12 are the same as those in the first embodiment, and their explanations are omitted.

As described above, according to the differential input type receiving circuit of the nineteenth embodiment of the present invention, the p-type field effect shown in FIG. 27 is added to the inverter INV1 of the first embodiment. The transistor TP6 is provided, and the differential amplifier circuit 119 is configured. In addition, the transistor TP6 has an enable signal IN3.
Is controlled based on the inversion signal of. For example, input signal IN
When the reception of 1 and IN2 is stopped, the enable signal IN is applied to the gate of the transistor TN51 as in the first embodiment.
By supplying 3 = “L” level, the transistor TN51 performs the OFF operation and the differential amplification function is stopped, and at the same time, the enable signal IN3 = 3 is set based on the “L” level.
The output of the state circuit 12 is set to the "Z" state.

Here, the inverted signal of the enable signal IN3 = “H” level is supplied to the transistor TP6, and the transistor TP6 performs the OFF operation, whereby the inverter INV5
The amplification function of is stopped. When receiving the input signals IN1 and IN2, by supplying the enable signal IN3 = “H” level to the gate of the transistor TN51,
The transistor TN51 is turned on, the differential amplification function is maintained, and the input signals IN1 and IN2 are differentially amplified. When the inverted signal of the enable signal IN3 = “L” level is supplied to the transistor TP6, the transistor TP6 is turned on, the amplifying function of the inverter INV5 is maintained, and the differentially amplified signal level is enabled. Signal IN
3 = Based on “H” level, output from the 3-state circuit 12 to the internal circuit.

Therefore, compared with the first embodiment, the delay function of the enable signal IN3 = “L” level causes the reception function to be stopped and the transistor TP6 connected to the inverter INV5 to perform the OFF operation. It is possible to stop the differential amplification operation when the reception is stopped and also stop the amplification operation of the inverter INV5.

As a result, compared with the first embodiment, the power consumption of the differential amplifier circuit 119 when reception is stopped can be further suppressed and the performance can be improved. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (20) Description of 20th Embodiment FIG. 28 is a configuration diagram of a differential input type receiving circuit according to a 20th embodiment of the present invention. In FIG. 28, in the twentieth embodiment, a p-type field effect transistor TP6 is provided in the inverter INV1 of the second embodiment to form the differential amplifier circuit 120.

The method of connecting the p-type field effect transistor TP6 is the same as in the nineteenth embodiment. Further, the constant current source transistor TN1, the differential pair transistors TN3 and TN4, the bias circuit 11A, the bias control circuit 13
The A, the inverter INV4, and the three-state circuit 12 are the same as those in the second embodiment, and the description thereof is omitted. Thus, according to the differential input type receiver circuit of the twentieth embodiment of the present invention, the inverter INV of the second embodiment is
1 shows a p-type field effect transistor T as shown in FIG.
P6 is provided and the differential amplifier circuit 120 is configured. Also,
The transistor TP6 is controlled based on the inverted signal of the enable signal IN3.

For example, when the reception of the input signals IN1 and IN2 is stopped, the enable signal IN3 = "L" level is supplied to the bias supply control circuit 13A, so that the transistor TN52 is supplied as in the second embodiment. Turned off,
The bias circuit 11A and the constant current source Io are disconnected from each other, and the transistor TN62 is turned on to supply the "L" level to the transistor TN1. As a result, the amplification function of the differential amplifier circuit 120 is stopped, and at the same time, the output of the 3-state circuit 12 is set to the "Z" state based on the enable signal IN3 = "L" level.

Here, the inverted signal of the enable signal IN3 = “H” level is supplied to the transistor TP6, and the transistor TP6 performs the OFF operation, whereby the inverter INV5
The amplification function of is stopped. When the input signals IN1 and IN2 are received, the enable signal IN3 = "H" level is supplied to the bias supply control circuit 13A to activate the control circuit 13A, as in the second embodiment. The bias circuit 11A and the constant current source Io are connected, the amplification function of the differential amplifier circuit 120 is maintained, and the input signals IN1 and IN2 are maintained.
Is differentially amplified.

When the inverted signal of the enable signal IN3 = “L” level is supplied to the transistor TP6, the transistor TP6 is turned on and the inverter I
The amplifying function of NV5 is maintained, and the differentially amplified signal level is output from the 3-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level. Therefore, compared with the second embodiment, the enable signal IN3 = "L" level stops the receiving function and the inverter INV
Since the transistor TP6 connected to 5 performs the OFF operation, it is possible to stop the differential amplification operation when the reception is stopped and also stop the amplification operation of the inverter INV5.

As a result, compared with the second embodiment, the power consumption of the differential amplifier circuit 120 when reception is stopped can be further suppressed and the performance can be improved. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (21) Description of Twenty-First Embodiment FIG. 29 is a configuration diagram of a differential input type reception circuit according to a twenty-first embodiment of the present invention. In FIG. 29, in the twenty-first embodiment, a p-type field effect transistor TP6 is provided in the inverter INV1 of the third embodiment to form the differential amplifier circuit 121.

The method of connecting the p-type field effect transistor TP6 is the same as in the nineteenth and twentieth embodiments.
Further, a constant current source transistor TN1, a differential pair transistor TN3, TN4, a bias circuit 11A, a p-type field effect transistor TP43, an n-type field effect transistor TN53,
Regarding the inverter INV5 and the 3-state circuit 12,
Since it is similar to the third and twentieth embodiments, its explanation is omitted.

As described above, according to the differential input type receiver circuit of the twenty-first embodiment of the present invention, the p-type field effect as shown in FIG. 29 is applied to the inverter INV1 of the third embodiment. The transistor TP6 is provided to configure the differential amplifier circuit 121. In addition, the transistor TP6 has an enable signal IN3.
Is controlled based on the inversion signal of. For example, input signal IN
To stop receiving 1 and IN2, use transistor TP4
By supplying the enable signal IN3 = "L" level to the gates of 3 and TN53, the transistor TP43 is turned on and the transistor TN53 is turned off. As a result, the transistors TP1 and TP2 perform the OFF operation, the current mirror circuit 11B is deactivated, the amplifying function of the differential amplifier circuit 113 is stopped, and at the same time, the enable signal IN3 =
The output of the 3-state circuit 12 is "based on the" L "level.
Z ”state.

Here, the inverted signal of the enable signal IN3 = “H” level is supplied to the transistor TP6, and the transistor TP6 performs the OFF operation, whereby the inverter INV5
The amplification function of is stopped. When receiving the input signals IN1 and IN2, the enable signal IN3 = is applied to the gates of the transistors TP43 and TN53 as in the third embodiment.
By supplying the "H" level, the transistor TP4
3 turns off, and the transistor TN53 turns on. As a result, the current mirror circuit 11B is activated, the amplification function of the differential amplifier circuit 121 is maintained, and the input signal
IN1 and IN2 are differentially amplified.

When the inverted signal of the enable signal IN3 = “L” level is supplied to the transistor TP6, the transistor TP6 is turned on and the inverter I
The amplification function of NV5 is maintained, and the differentially amplified signal level is output from the 3-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level. Therefore, compared with the third embodiment, the enable signal IN3 = “L”
Depending on the level, the reception function is stopped, and the transistor TP6 connected to the inverter INV5 performs the OFF operation, thereby stopping the differential amplification operation when the reception is stopped, and the amplification operation of the inverter INV5. It is possible to stop it.

As a result, compared with the third embodiment, the power consumption of the differential amplifier circuit 121 when reception is stopped can be further suppressed and the performance can be improved. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (22) Description of 22nd Embodiment FIG. 30 is a configuration diagram of a differential input type reception circuit according to a 22nd embodiment of the present invention. In FIG. 30, in the 22nd embodiment, a p-type field effect transistor TP6 is provided in the inverter INV1 of the 4th embodiment to form a differential amplifier circuit 122.

The method of connecting the p-type field effect transistor TP6 is the same as in the 19th to 21st embodiments.
Further, a constant current source transistor TN1, a differential pair transistor TN3, TN4, a bias circuit 11A, an inverter INV2,
n-type field effect transistors TN54, TN64, TN74,
The TN84, the inverter INV5, and the three-state circuit 12 are the same as those in the fourth and twenty-first embodiments, so the description thereof will be omitted.

As described above, according to the differential input type receiver circuit of the twenty-second embodiment of the present invention, the p-type field effect as shown in FIG. 30 is applied to the inverter INV1 of the fourth embodiment. The transistor TP6 is provided to configure the differential amplifier circuit 122. In addition, the transistor TP6 has an enable signal IN3.
Is controlled based on the inversion signal of. For example, input signal IN
When the reception of 1 and IN2 is stopped, the enable signal IN is applied to the transistors TN54 and TN64 as in the fourth embodiment.
By supplying an inversion signal of 3 = “L” level, the transistors TN54 and TN64 are turned on, and the gates of the differential pair transistors TN3 and TN4 are fixed to the ground line GND level. Further, by supplying the enable signal IN3 = “L” level to the transistors TN74, TN84, the transistors TN74, TN84 perform an OFF operation, the supply of both input signals IN1, IN2 is cut off, and the differential amplifier circuit 122 The amplification function is stopped, and at the same time, enable signal IN3 = "L"
The output of the 3-state circuit 12 is set to the "Z" state based on the level.

Here, the inverted signal of the enable signal IN3 = “H” level is supplied to the transistor TP6, and the transistor TP6 performs the OFF operation, whereby the inverter INV5
The amplification function of is stopped. When the input signals IN1 and IN2 are received, the enable signal IN3 = "H" level inversion signal is supplied to the transistors TN54 and TN64 in the same manner as in the fourth embodiment so that the transistor TN5 is supplied.
4, TN64 operates OFF, and the differential pair transistor TN3,
The gate of TN4 is released from the ground line GND level. Also, the enable signal IN3 is applied to the transistors TN74 and TN84.
= “H” level is supplied, the transistors TN74 and TN84 are turned on and both input signals IN1 and IN2 are turned on.
Are supplied to the gates of the differential pair transistors TN3 and TN4, respectively, and both input signals IN1 and IN2 are differentially amplified.

When the inverted signal of the enable signal IN3 = “L” level is supplied to the transistor TP6, the transistor TP6 is turned on and the inverter I
The amplification function of NV5 is maintained, and the differentially amplified signal level is output from the 3-state circuit 12 to the internal circuit based on the enable signal IN3 = “H” level. Therefore, as compared with the fourth embodiment, the enable signal IN3 = "L".
Depending on the level, the reception function is stopped, and the transistor TP6 connected to the inverter INV5 performs the OFF operation, thereby stopping the differential amplification operation when the reception is stopped, and the amplification operation of the inverter INV5. It is possible to stop it.

As a result, compared with the fourth embodiment, it is possible to further suppress the power consumption of the differential amplifier circuit 122 when reception is stopped and to improve the performance. It is possible to reduce the power consumption and improve the reliability of the electronic device in which the type receiver circuit is incorporated. (23) Description of the 23rd Embodiment FIG. 31 is an explanatory diagram of a differential input type receiver circuit according to the third embodiment of the present invention, and FIG. 31 (A) is its configuration diagram.
Reference numerals 31 (A) show the operation explanatory views.

In FIG. 31A, the difference from the first to twenty-second embodiments is that in the twenty-third embodiment, the delay circuit 14 is connected to the three-state circuit 12, the enable signal IN3 is delayed, and the delay signal IND is supplied to the 3-state circuit 12. That is, in FIG. 31A, the delay circuit 14 is a circuit in which a plurality of stages of inverter elements are connected,
It is connected between the supply point of the enable signal IN3 and the 3-state circuit 12. The differential amplifier circuit 10 includes differential amplifier circuits 11, 21, 3 according to the first to twenty-second embodiments of the present invention.
1, 41, 51, 61, 71, 81, 91, 110, 11
1,112,113,114,115,116,117,118,119
, 120, 121, 122 apply. The differential amplifier circuits 71, 81, 9 according to the seventh to fourteenth embodiments of the present invention.
The delay circuit 14 may be shared by 1,110, 111, 112, 113 and 114. For example, the delay signal IND via the delay circuit 14 is supplied to the gate of the n-type field effect transistor TN9 of the differential amplifier circuits 71, 81, 91, 110 according to the seventh to tenth embodiments via the inverter INV3. To do. In addition, the differential amplifier circuit 111 according to the eleventh to fourteenth embodiments.
, 112, 113, 114 p-type field effect transistors TP
The delay signal IND via the delay circuit 14 is supplied to the gate of 5. The differential amplifier circuit element and the 3-state circuit 1
The description of No. 2 is omitted because it is the same as in the first to twenty-second embodiments.

Thus, according to the differential input type receiving circuit of the twenty-third embodiment of the present invention, the delay circuit 14 is connected to the three-state circuit 12 as shown in FIG.
The circuit 14 delays the enable signal IN3. Therefore, the differential amplifier circuits 11 according to the first to twenty-second embodiments,
21, 31, 41, 51, 61, 71, 81, 91, 11
0, 111, 112, 113, 114, 115, 116, 117, 118
, 119, 120, 121, 122 n-type field effect transistors TN1, TN53, TN54, TN64, TN74, TN84,
The enable signal IN3 is supplied to the function control elements 13 such as the p-type field effect transistors TP43 and TP6 and the bias supply control circuit 11A earlier than the three-state circuit 12, and the potential at the operating point a of the differential amplifier circuit 21. After the level reaches the threshold voltage Vth of the inverters INV1, INV4, INV5, the delayed enable signal IN3 can be supplied to the 3-state circuit 12.

As a result, the differential amplifier circuits 11, 21, 31, 41, 51, 61, 71, 81, 9 are used when the reception state of the differential input type receiving circuit is changed to the operating state.
1,110,111,112,113,114,115,116,117
, 118, 119, 120, 121, 122 transition to stable operation, the output high impedance state is released, and it becomes possible to take in more stable input signals IN1, IN2 to the internal circuit. It greatly contributes to the improvement of the reliability of the interface circuit for the communication modem which incorporates the dynamic input type receiving circuit.

[0180]

As described above, according to the first differential input type receiving circuit of the present invention of the present invention, the function control element composed of the n-type field effect transistor is connected to the differential amplifier circuit, The amplification function of the differential amplifier circuit is controlled based on the operation permission signal. Therefore, when an operation permission signal of a predetermined level is supplied to the gate of the n-type field effect transistor, the reception function of the differential input type reception circuit is stopped and the signal is supplied to the input section. Also, it becomes possible to forcibly stop the transistor operation of the differential amplifier circuit.

Further, according to the second differential input type receiving circuit of the present invention, the function control element including the bias supply control circuit is connected between the constant current source of the differential amplifier circuit and the bias circuit. Therefore, when an operation permission signal of a predetermined level is supplied to the bias supply control circuit, the transistor operation of the differential amplifier circuit when reception is stopped is forcibly stopped, like the first differential input type reception circuit. It becomes possible.

Further, according to the third differential input type receiving circuit of the present invention, a p-type field effect transistor is provided between the common gate of the current mirror circuit of the differential amplifier circuit and the power supply line on the high potential side. Further, an n-type field effect transistor is connected between the common gate and the differential pair transistor, and both transistors are controlled based on the operation permission signal.

Therefore, when an operation permission signal of a predetermined level is supplied to the gate of the n-type and p-type field effect transistors, the differential input type reception circuit is received like the first and second differential input type reception circuits. It is possible to stop the reception function of the circuit and forcibly stop the transistor operation of the differential amplifier circuit even in the state where the signal is supplied to the input section.

Further, according to the fourth differential input type receiving circuit of the present invention, the first switching circuit is connected between the differential pair transistor, the low potential side power supply line and the input signal supply section. , Which is controlled based on the operation permission signal and the inverted signal of the operation permission signal. Therefore, if an operation permission signal of a predetermined level is supplied to the first switching circuit,
Unlike the first to third differential input type receiving circuits, the receiving function can be stopped and the input part of the differential pair transistor separated from the input part can be fixed to the ground line level.

Further, according to the fifth differential input type receiving circuit of the present invention, the second switching circuit is connected between the differential pair transistor and the current mirror circuit, and the second switching circuit is an operation permission signal or an operation permission signal. It is controlled based on the inverted signal of the signal. For this reason, when an operation permission signal of a predetermined level is supplied to the second switching circuit, the reception function of the differential amplifier circuit is stopped and the second amplification circuit is used as in the first to fourth differential input type reception circuits. It is possible to stop the amplifying operation of the differential amplifier circuit when the reception is stopped by switching the switching circuit of.

Further, according to the sixth differential input type receiving circuit of the present invention, an n-type field effect transistor or a p-type field effect transistor is connected to the output circuit of the differential amplifier circuit, and both transistors are connected. , The operation permission signal or the inverted signal of the operation permission signal. Therefore, the n
When a predetermined level of operation permission signal is supplied to the p-type and p-type field effect transistors, the reception function is stopped and the transistor connected to the output circuit is different from the first to fifth differential input type reception circuits. The switch operation makes it possible to stop the amplification operation of the differential amplifier circuit when reception is stopped, and also stop the amplification operation of the output circuit.

Further, according to the seventh differential input type receiving circuit of the present invention, in the first to sixth differential input type receiving circuits of the present invention, the delay circuit is connected to the output control circuit and the function control element. The output control circuit and the function control element are controlled based on the delayed operation permission signal. Therefore, when a delay signal of a predetermined level is supplied to the output control circuit or the function control element, the differential amplifier circuit transits to a stable operation as compared with the first to sixth differential input type receiving circuits of the present invention. After that,
The output high impedance state is released, and a more stable input signal can be taken into the internal circuit.

This makes it possible to suppress the power consumption of the differential amplifier circuit when the reception function is stopped as much as possible.
It is possible to reduce the power consumption of an electronic device incorporating the differential input type receiving circuit. This largely contributes to the improvement of the reliability of the communication modem interface circuit and the like incorporating the differential input type receiving circuit.

[Brief description of drawings]

FIG. 1 is a principle diagram (1) of a differential input type receiving circuit according to the present invention.

FIG. 2 is a principle diagram (2) of the differential input type receiving circuit according to the present invention.

FIG. 3 is a principle diagram (No. 3) of the differential input type receiving circuit according to the present invention.

FIG. 4 is a principle diagram (4) of the differential input type receiving circuit according to the present invention.

FIG. 5 is a configuration diagram and an operation explanatory diagram of the differential input type receiving circuit according to the first embodiment of the present invention.

FIG. 6 is a supplementary explanatory diagram of the differential input type receiving circuit according to each embodiment of the present invention.

FIG. 7 is a configuration diagram of a differential input type receiving circuit according to a second embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of the differential input type receiving circuit according to the second embodiment of the present invention.

FIG. 9 is a configuration diagram of a differential input type receiving circuit according to a third embodiment of the present invention.

FIG. 10 is an operation explanatory diagram of the differential input type receiving circuit according to the third embodiment of the present invention.

FIG. 11 is a configuration diagram of a differential input type receiving circuit according to a fourth embodiment of the present invention.

FIG. 12 is an operation explanatory diagram of the differential input type receiving circuit according to the fourth embodiment of the present invention.

FIG. 13 is a configuration diagram and an operation explanatory diagram of a differential input type receiving circuit according to a fifth embodiment of the present invention.

FIG. 14 is a configuration diagram and an operation explanatory diagram of a differential input type receiving circuit according to a sixth embodiment of the present invention.

FIG. 15 is a configuration diagram of a differential input type receiving circuit according to a seventh embodiment of the present invention.

FIG. 16 is a configuration diagram of a differential input type reception circuit according to an eighth embodiment of the present invention.

FIG. 17 is a configuration diagram of a differential input type receiving circuit according to a ninth embodiment of the present invention.

FIG. 18 is a configuration diagram of a differential input type reception circuit according to a tenth embodiment of the present invention.

FIG. 19 is a configuration diagram of a differential input type reception circuit according to an eleventh embodiment of the present invention.

FIG. 20 is a configuration diagram of a differential input type reception circuit according to a twelfth embodiment of the present invention.

FIG. 21 is a configuration diagram of a differential input type receiving circuit according to a thirteenth embodiment of the present invention.

FIG. 22 is a configuration diagram of a differential input type reception circuit according to a fourteenth embodiment of the present invention.

FIG. 23 is a configuration diagram and an operation explanatory diagram of a differential input type receiving circuit according to a fifteenth embodiment of the present invention.

FIG. 24 is a configuration diagram and an operation explanatory diagram of a differential input type receiving circuit according to a sixteenth embodiment of the present invention.

FIG. 25 is a configuration diagram of a differential input type receiving circuit according to a seventeenth embodiment of the present invention.

FIG. 26 is a configuration diagram of a differential input type receiving circuit according to an eighteenth embodiment of the present invention.

FIG. 27 is a configuration diagram of a differential input type receiving circuit according to a nineteenth embodiment of the present invention.

FIG. 28 is a configuration diagram of a differential input type receiving circuit according to a twentieth embodiment of the present invention.

FIG. 29 is a configuration diagram of a differential input type reception circuit according to a twenty-first embodiment of the present invention.

FIG. 30 is a configuration diagram of a differential input type reception circuit according to a twenty-second embodiment of the present invention.

FIG. 31 is a configuration diagram of a differential input type receiving circuit according to a 23rd embodiment of the present invention.

FIG. 32 is an explanatory diagram of a differential input type reception circuit according to a conventional example.

[Explanation of symbols]

 11 ... Differential amplifier circuit, 11A ... Bias circuit, 11B, 11C ... Current mirror circuit, 11D ... Output circuit, 12 ... Output control means (3-state circuit), 13 ... Function control element, 13A ... Bias supply control circuit, 13B ... 1st switching circuit, 13C ... 2nd switching circuit, 14 ... delay circuit, TN ... n type field effect transistor, TP ... p type field effect transistor, VCC ... high potential side power supply line, GND ... low Power line (ground line) on the potential side, IN1, IN2 ... Input signal, IN3 ... Operation enable signal.

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H03K 19/0175 H04L 25/02 R 9199-5K

Claims (8)

[Claims] 1. A differential amplifier circuit (11) for differentially amplifying two input signals (IN1, IN2), and an output for outputting the differentially amplified signal level based on an operation permission signal (IN3). A control circuit (12), a function control element (13) is provided in the differential amplifier circuit (11), and the function control element (13) is a differential amplifier circuit based on an operation permission signal (IN3). A differential input type receiving circuit characterized by controlling the amplification function of (11). 2. The differential point in which the function control element (13) is composed of an n-type field effect transistor (TN), and the n-type field effect transistor (TN) is provided in a differential amplifier circuit (11). The operation permission signal (IN3) is supplied to the gate of the n-type field effect transistor (TN), which is connected between (c) and the constant current source (Io). Differential input type receiver circuit. 3. The function control element (13) comprises a bias supply control circuit (13A), and the bias supply control circuit (13A) is a constant current source (I) of a differential amplifier circuit (11).
o) and a bias circuit (11A), and the bias supply control circuit (13A) is controlled based on an operation permission signal (IN3). Receiver circuit. 4. The function control element (13) comprises a p-type field effect transistor (TP) and an n-type field effect transistor (TN), and the p-type field effect transistor (TP) is a differential amplifier circuit. The n-type field effect transistor (T) is connected between the common gate of the current mirror circuit (11B) of (11) and the power supply line (VCC) on the high potential side.
N) is the common gate (G) of the current mirror circuit (11B)
And an operation enable signal (IN3) to the gates of the p-type and n-type field effect transistors (TP, TN), which are connected to the drains of the differential pair transistors (TN3 or TN4) of the differential amplifier circuit (11). The differential input type receiving circuit according to claim 1, wherein 5. The function control element (13) is composed of a first switching circuit (13B), and the first switching circuit (13B) is a differential pair transistor (TN3, TN4) of a differential amplifier circuit (11). ) Gate and the power supply line on the low potential side (G
ND) and the input signal (IN1, IN2) supply unit, and the first switching circuit (13B) is based on the operation permission signal (IN3) and the inverted signal of the operation permission signal (IN3). The differential input type receiving circuit according to claim 1, wherein the receiving circuit is controlled by the following. 6. The function control element (13) comprises a second switching circuit (13C), and the second switching circuit (13C) comprises a differential pair transistor (TN3, TN4) of a differential amplifier circuit (11). ) And the current mirror circuit (11C), and is connected to the second switching circuit (13C).
Is controlled based on an operation permission signal (IN3) or an inverted signal of the operation permission signal (IN3). 7. The function control element (13) comprises an n-type field effect transistor (TN) or a p-type field effect transistor (TP), and the n-type field effect transistor (TN) or p-type electric field. The effect transistor (TP) is connected to the output circuit (11D) of the differential amplifier circuit (11),
The n-type field effect transistor (TN) or the p-type field effect transistor (TP) is an operation permission signal (IN3).
Alternatively, the control is performed based on an inverted signal of the operation permission signal (IN3) or a delayed signal of both signals.
5. The differential input type receiving circuit described in 5. 8. A delay circuit (14) is connected to the output control circuit (12) or the function control element (13), and the delay circuit (14) delays the operation permission signal (IN3). The differential input type receiving circuit according to claim 1.