JP2001144558A - Differential amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential amplifier that can prevent reduction in a phase margin, realize a circuit configuration that is hardly oscillated, control a gate voltage of an output transistor(TR) without the need for a gate bias power supply circuit for an upper side TR of a loopback cascode current mirror circuit and obtain a rail-to-rail common mode output voltage range with less output on-resistance. SOLUTION: The differential amplifier has a differential input circuit and a loopback cascode current mirror circuit (Q11, Q12, Q13, and Q14) whose gates are all connected receives a current output signal of the differential input circuit so as to control a gate voltage of an output TR (Q22).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier,
The present invention relates to a differential amplifier that has a function of outputting a common mode voltage of Rail-to-Rail and is monolithically integrated using CMOS technology.

[0002]

2. Description of the Related Art In recent years, there has been a growing demand for low power consumption semiconductor components from the viewpoint of environmental protection. In the differential amplifier, power consumption at the time of quiescent and power consumption at the time of output of the operational amplifier using the bipolar transistor has become a problem. Therefore, in order to solve these problems, CMOS
CMOS differential amplifier circuits with technology-based rail-to-rail configurations and common-mode input voltage ranges have attracted attention.

A conventional CMOS differential amplifier circuit having a rail-to-rail common-mode input voltage range is disclosed in Japanese Unexamined Patent Publication No. 7-15 / 1995.
249, and its outline will be described below with reference to the drawings. FIG. 2 is an equivalent circuit diagram showing an example of a conventional differential amplifier, which is a circuit described in Japanese Patent Application Laid-Open No. 7-15249. The reference numerals used in the drawings refer to those described in the above publication.

In FIG. 2, transistors Q1, Q2,
The differential output currents I3 and I4 output from the P-channel differential input unit 14 composed of Q6 are output from the junction between the source of the transistor Q12 and the drain of the transistor Q14 of the folded cascode current mirror circuit 18/20 and the transistor Q11. To the junction of the source of Q13 and the drain of Q13. On the other hand, the differential output currents I1 and I2 output from the N-channel differential input section 12 composed of the transistors Q4, Q5 and Q3 are equal to the junction between the source of the transistor Q10 and the drain of the transistor Q8 of the folded cascode current mirror circuit 22. Section and transistor Q9
And the junction of the drain of the transistor Q7.

The gate connection between the transistor Q11 and the transistor Q12 is biased by the bias voltage VB3, and the transistor Q9 is biased by the bias voltage VB2.
And the gate coupling of transistor Q10 is biased. These form a folded cascode gain stage,
The gate voltages of the output transistors Q17 and Q18 of the output unit 24 are controlled. Further, a current limited by the transistor Q16 flows between the source and the drain of the transistor Q15 to generate a gate-source voltage of the transistor Q15, thereby controlling the voltage between the gate of the transistor Q17 and the gate of the transistor Q18. And the current consumption of the transistor Q18 is minimized.

Next, an outline of a CMOS differential input circuit having a rail-to-rail common-mode input voltage range in which a bias power supply is not configured will be described. Japanese Patent No. 2597690 is an example of this case.

FIG. 3 is an equivalent circuit diagram showing another example of a conventional differential amplifier, which is a circuit described in the aforementioned Japanese Patent No. 2597690. Note that the reference numerals used in this drawing also refer to those described in the above-mentioned publications, and therefore, the same reference numerals as those used in FIG. 2 exist, but these do not correspond.

In FIG. 3, the differential output current output from P-channel differential input stage transistors Q38 and Q42 is the same as that of transistor Q60 of transistors Q60, Q62, Q70 and Q74 forming the folded cascode current mirror circuit. The signal is input to the junction between the source and the drain of the transistor Q62 and the junction of the source of the transistor Q70 and the drain of the transistor Q74.

On the other hand, the differential output current output from N-channel differential input stage transistors Q28 and Q32 is
The signals are input to the junction between the source of the transistor Q68 and the drain of the transistor Q66 and the junction between the source of the transistor Q58 and the drain of the transistor Q56 among the transistors Q66, Q68, Q56, and Q58 forming the folded cascode current mirror circuit. Thus, a folded cascode gain stage is formed, and the junction between the drain of the transistor Q58 and the drain of the transistor Q60 is used as the output Vout.

The auxiliary amplifying section includes transistors Q80 and Q8.
6, Q82, Q90 and transistor Q88.
For example, when the voltage at the differential input terminal 24 becomes much smaller than the voltage at the input terminal 26, the current flowing through the transistor Q28 decreases and the current flowing through the transistor Q68 increases. Further, the current flowing through the transistor Q32 increases, and the current flowing through the transistor Q58 decreases. At the same time, the current flowing through transistor Q38 increases,
The current flowing through transistor Q70 decreases. Further, the current flowing through the transistor Q42 decreases, the voltage at the junction 64 decreases, and the transistor Q60 turns on hard.

As a result, the voltage at the junction 50 is increased, and the voltage is reduced to the analog grounded transistor Q8.
2 becomes higher than the gate potential of transistor Q82.
And a larger current flows through the transistor Q86 to boost the voltage at the junction 65. Thereby, the transistor Q
62 and transistor Q74 carry more current, which reduces the voltage at junction 64 and junction 78, and turns on transistor Q60 and transistor Q70 harder. From these operations, the gain of the output unit increases.

The configuration and operation of the other parts of this differential amplifier circuit are not directly related to the present invention in comparison with the present invention.

[0013]

However, such a configuration has the following problems.

(1) With the increase in the circuit scale, not only the chip area, the manufacturing cost, the failure rate and the like tend to increase, but also the oscillation is possible due to the decrease in the phase margin generated by the pole related to the transfer function of the added circuit. Tend to be higher.

(2) It is necessary to apply a gate bias voltage to the upper transistor of the cascode type current mirror circuit which receives the output current of the differential input circuit.
In a bias circuit of an OS circuit, a generated current value has a large variation, which makes it difficult to control.

(3) When the output portion is a cascode type current mirror circuit, the operating (ON) resistance of the lower transistor is added to the output circuit, so that the output impedance increases and the output voltage range tends to narrow. Become.

The present invention has been made to solve the above-mentioned conventional problems. The present invention prevents a decrease in phase margin, realizes a circuit configuration in which oscillation is difficult, and provides a gate bias power supply circuit for an upper transistor of a folded cascode type current mirror circuit. It is an object of the present invention to provide a differential amplifier capable of controlling the gate voltage of an output transistor without requiring the same and obtaining a rail-to-rail common-mode output voltage range with a small output on-resistance.

[0018]

According to the present invention, there is provided a differential amplifier comprising:
The current output signal of the differential input circuit is received by the folded cascode type current mirror circuit connecting all the gates,
The gate voltage of the output transistor is controlled.

According to the present invention, it is possible to suppress the occurrence of poles, thereby preventing a decrease in phase margin, realizing a circuit configuration that is less likely to oscillate, and providing a current output signal of the differential input circuit to all gates. Is received by the folded cascode type current mirror circuit to which the connection is made, it is not necessary to form a bias circuit which is difficult to configure in a CMOS circuit, and it is possible to control the gate voltage of the output transistor.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an equivalent circuit diagram showing a configuration of a differential amplifier according to an embodiment of the present invention. Note that some of the reference numerals used in FIG. 1 are the same as those used in FIG. 2 and FIG. 3, but they have no correspondence.

In FIG. 1, P-channel input transistors Q5 and Q6 to which a constant current I1 is supplied from a power supply Vcc by transistors Q1 and Q2 (hereinafter, a symbol I representing a current is assigned only to the P-channel side), N-channel input transistors Q7 and Q8 supplied with a constant current by transistors Q3 and Q4 provide
A differential input circuit having a common-mode input voltage range in the form of a rail is configured, and its P-channel output signal currents I2 and I3 are a current mirror circuit including a transistor Q11 and a transistor Q12 having a drain and a gate connected, and The current mirror circuit and the gate are input to the junction of both the source and the drain of the cascode type current mirror circuit formed by the junction of the current mirror circuit formed by the common transistor Q13 and the transistor Q14. A current mirror circuit composed of a transistor Q17 and a transistor Q18 to which the current mirror circuit is connected, and a cascode type current mirror formed by joining a current mirror circuit composed of a transistor Q15 and a transistor Q16 having a common gate with the current mirror circuit. Is input to the junction of the scan and the drain.

On the other hand, the current sources of these current mirror circuits include P-channel current mirror circuit constant current (I4, I5) sources of transistors Q9 and Q10, and N current sources of transistors Q19 and Q20.
A channel current mirror circuit constant current source is used, and a current is supplied to each of the cascode type current mirror circuits from these current sources, whereby the output transistor Q21 is generated by the drain voltages of the transistors Q12 and Q18 of the cascode type current mirror circuit.
And the gate voltage of the output transistor Q22 can be controlled to obtain an output Vout in the rail-to-rail output voltage range.

As described above, according to the present embodiment, the elements constituting the differential amplifier are composed of a relatively small number of elements, and the occurrence of poles can be suppressed, thereby reducing the phase margin. In addition to realizing a circuit configuration that prevents oscillation and oscillates, the gate voltage of the output transistor is controlled without the gate bias power supply circuit of the upper transistor of the folded cascode type current mirror circuit, and the rail-to-rail common-mode output with low output ON resistance An output in a voltage range can be obtained.

[0024]

As described above, according to the present invention, the current output signal of the differential input circuit is received by the folded cascode type current mirror circuit to which all gates are connected. An advantageous effect is obtained in that the gate voltage can be controlled to obtain an output in the common-mode output voltage range of rail-to-rail.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a configuration of a differential amplifier according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing an example of a conventional differential amplifier.

FIG. 3 is an equivalent circuit diagram showing another example of the conventional differential amplifier.

[Explanation of symbols]

 Q1-Q22 Transistor Vcc power supply

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J066 AA01 AA12 CA00 CA54 CA74 CA92 FA20 HA10 HA17 HA25 HA29 KA05 KA09 MA17 MA21 ND01 ND14 ND22 ND23 PD01

Claims (2)

[Claims] 1. A differential input circuit, a folded cascode current mirror circuit connecting all gates to which a current output signal of the differential input circuit is input, and an output transistor controlled by an output of the cascode current mirror circuit A differential amplifier comprising a circuit. 2. A differential input circuit having a rail-to-rail common-mode input voltage range, a folded cascode current mirror circuit connecting all gates to which a current output signal of the differential input circuit is input, and A differential amplifier including an output transistor circuit controlled by an output of a cascode current mirror circuit and obtaining an output in a rail-to-rail common-mode output voltage range.