KR0145857B1 - Current consumption optimization circuit in operational amplifier - Google Patents
Current consumption optimization circuit in operational amplifier Download PDFInfo
- Publication number
- KR0145857B1 KR0145857B1 KR1019950023994A KR19950023994A KR0145857B1 KR 0145857 B1 KR0145857 B1 KR 0145857B1 KR 1019950023994 A KR1019950023994 A KR 1019950023994A KR 19950023994 A KR19950023994 A KR 19950023994A KR 0145857 B1 KR0145857 B1 KR 0145857B1
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- South Korea
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- operational amplifier
- terminal
- current consumption
- pmos transistor
- current
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
- H03F3/45219—Folded cascode stages
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야:1. The technical field to which the invention described in the claims belongs:
연산증폭기에 관한것으로서, 특히 디지탈 신호체계에서 연산증폭기의 동작을 불필요할때 전력소모를 줄일 수 있는 연산증폭기의 전력소모 최적화 회로에 관한 것이다.The present invention relates to an operational amplifier, and more particularly, to a power consumption optimization circuit of an operational amplifier that can reduce power consumption when an operation of an operational amplifier is unnecessary in a digital signal system.
2. 발명이 해결하려고 하는 기술적 과제:2. The technical problem the invention is trying to solve:
디지탈 신호체계에서 연산증폭기의 동작이 요구되지 않을시 전류의 흐름을 차단하여 전류의 소모를 억제시키는 회로를 제공함에 있다.The present invention provides a circuit that suppresses the current consumption by blocking the flow of current when the operation of the operational amplifier is not required in the digital signal system.
3. 발명의 해결방법의 요지:3. Summary of the Solution of the Invention:
P,N모스트랜지스터(Q1~Q4)로 구성된 차동 입력증폭기(101)와, 레벨 쉬프트 및 차동/싱글 앤디드 이득회로(103)용 N모스트랜지스터(Q5)와, 상기 P,N모스트랜지스터(Q6, Q7)로 구성된 출력버퍼(105)로 구성된 연산증폭기에 있어서, 상기 PMOS트랜지스터(Q6)의 드레인단과 전원단(Vdd)간에 PMOS트랜지스터(Q101)를 연결하고, 상기 PMOS트랜지스터(Q101)의 게이트에 전원다운단(301)를 연결하여 동작이 필요치 않을시 전원다운단(301)과 상기 N모스트랜지스터(Q5, Q7)의 게이트에 인가되는 바이어스단(302)으로 인가되는 제어신호에 의해 전류(l1, l2)의 흐름을 억제하여 전류소모를 줄이도록 구성됨을 특징으로 하는 연산증폭기에 있어서 전류소모 최적화 회로.A differential input amplifier 101 composed of P and N MOS transistors Q1 to Q4, an N MOS transistor Q5 for level shift and differential / single-ended gain circuit 103, and the P and N MOS transistor Q6. In the operational amplifier composed of an output buffer 105 composed of Q7, a PMOS transistor Q101 is connected between the drain terminal and the power supply terminal Vdd of the PMOS transistor Q6, and is connected to a gate of the PMOS transistor Q101. When operation is not necessary by connecting the power down terminal 301, the current l1 is controlled by a control signal applied to the power down terminal 301 and the bias terminal 302 applied to the gates of the N MOS transistors Q5 and Q7. , current consumption optimization circuit in the operational amplifier, characterized in that to suppress the flow of l2) to reduce the current consumption.
4. 발명의 중요한 용도:4. Important uses of the invention:
연산증폭기 전류소모 최적화 회로.Operational amplifier current consumption optimization circuit.
Description
제1도는 종래의 연산증폭기에 대한 블럭도.1 is a block diagram of a conventional operational amplifier.
제2도는 제1도의 구체 회로도.2 is a concrete circuit diagram of FIG.
제3도는 본 발명의 실시예에 따른 회로도.3 is a circuit diagram according to an embodiment of the present invention.
제4도는 제3도의 동작 파형도.4 is an operational waveform diagram of FIG.
본 발명은 연산증폭기에 관한것으로서, 특히 디지탈 신호체계에서 연산증폭기의 동작이 불필요로할시 전류소모를 줄일 수 있는 연산증폭기의 전류소모 최적화 회로에 관한 것이다.The present invention relates to an operational amplifier, and more particularly, to a current consumption optimization circuit of an operational amplifier that can reduce the current consumption when the operation of the operational amplifier is unnecessary in a digital signal system.
종래의 연산증폭기는 제1도와 같이 차동입력증폭기(101), 레벨쉬프트 및 차동/싱글 엔디드 이득회로(103), 출력버퍼(105)로 구성되어 있다. 제1도의 연산증폭기는 제2도와 같이 구체적으로 구성되어 있음을 나타낼 수 있다. 제2도에서 N.P모스트랜지스터(Q1, Q2, Q3, Q4)는 차동입력증폭기(101)이고, N모스트랜지스터(Q5)는 레벨쉬프트 및 차동/싱글 앤디드이득회로(103)이다. P모스트랜지스터(Q6, Q9)와 전류-소스 로드형 N형 트랜지스터(Q7)는 출력버퍼이다.The conventional operational amplifier is composed of a differential input amplifier 101, a level shift and differential / single-ended gain circuit 103, and an output buffer 105 as shown in FIG. The operational amplifier of FIG. 1 may indicate that the operational amplifier is specifically configured as shown in FIG. In FIG. 2, the N.P MOS transistors Q1, Q2, Q3, and Q4 are differential input amplifiers 101, and the N MOS transistors Q5 are level shift and differential / single-ended gain circuits 103. In FIG. The P-most transistors Q6 and Q9 and the current-source loaded N-type transistor Q7 are output buffers.
상기 제2도의 연산증폭기 트랜지스터(Q1~Q7)의 동작 특성을 리니어 또는 포화 영역에 존재함으로 연산증폭기의 동작이 필요가 없는 경우에도 제2도에서 전류(l1, l2)가 흐르게 되어 불필요한 전류 소모가 되는 문제점이 있었다.Since the operational characteristics of the operational amplifier transistors Q1 to Q7 of FIG. 2 exist in the linear or saturation region, currents l1 and l2 flow in FIG. 2 even when the operation of the operational amplifier is not necessary. There was a problem.
따라서 본 발명의 목적은 디지탈 신호체계에서 연산증폭기의 동작이 요구되지 않을시 전류의 흐름을 차단하여 전류의 소모를 억제시키는 연산증폭기를 제공함에 있다.Accordingly, an object of the present invention is to provide an operational amplifier that suppresses the current consumption by blocking the flow of current when the operation of the operational amplifier is not required in the digital signal system.
이하 본 발명을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3도는 본 발명에 따른 회로도로서, 본 발명은 제2도의 도시와 같이 PMOS트랜지스터(Q6)의 드레인단과 전원단(Vdd)간에 PMOS트랜지스터(Q101)를 연결하고, 상기 PMOS트랜지스터(Q101)의 게이트에 전원다운단(301)이 연결되며, 그외의 구성은 동일하다.FIG. 3 is a circuit diagram according to the present invention. The present invention connects the PMOS transistor Q101 between the drain terminal of the PMOS transistor Q6 and the power supply terminal Vdd, as shown in FIG. 2, and the gate of the PMOS transistor Q101. Power down stage 301 is connected to, the other configuration is the same.
제4도는 본 발명의 실시예에 따른 제3도의 동작파형도로서, (4a)는 제3도의 전원다운단(301)의 입력파형이고, (4b)는 바이스단(302)의 입력파형예이다.4 is an operating waveform diagram of FIG. 3 according to an embodiment of the present invention, where 4a is an input waveform of the power down stage 301 of FIG. 3, and 4b is an example of an input waveform of the vise stage 302. FIG. .
따라서 본 발명의 구체적 일실시예를 제3도~제4도를 참조하여 상세히 설명하면, 종래의 연산증폭기는 제2도와 같이 N.PMOS트랜지스터(Q5, Q6)에서 전류(l1, l2)가 항상 흐르게 되어 있다. 역시 제3도의 도시와 같이 본 발명의 예에서도 이와 같은 동작은 일어 날수 있다. 따라서 본 발명은 PMOS트랜지스터(Q101)를 연결하고 전원다운단(301)과 바이스단(302)으로 제공되는 전류다운과 바이어싱에 의해 전류 소모를 줄이고자 한다. 본 발명의 제3도와 같이 구성되는 연산증폭기에서 제4도 (4a), (4b)와 같은 파형을 제어신호로 받아들이되, (4a)의 T1, T2의 경우 바이어스단(302)의 입력신호가 로우일때는 트랜지스터(Q5, Q7)가 오프되어 연산증폭기는 동작하지 않게 되어 이때 전류(l1, l2)가 흐르지 않는다. 그런데 제4도(4a)의 T3, T5의 경우 바이어스단(302)의 신호와 전력다운단(301)의 신호가 하이일때는 N,PMOS트랜지스터(Q5), (Q7)가 온(ON), 오프(OFF)가 된다. 이때 상기 NMOS트랜지스터(Q5)가 온(ON)이므로 전류(l1)은 흐르지만 PMOS트랜지스터(Q101)가 오프(OFF)이므로 NMOS트랜지스터(Q7)가 온 임에도 불구하고 전류(l2)가 흐르지 않는다. 한편, 상기(4a)의 T4, T6의 경우 바이어스단(302)는 하이이고, 전력다운단(301)이 로우일 때는 NMOS트랜지스터(Q5, Q9), PMOS트랜지스터(Q101)은 모두 온(ON)이 되어 연산증폭기가 정상 동작을 한다. 상기 한 바와 같이 바이어스단(302)이 로우인 경우 연산증폭기를 동작시키지 않고, 하이일때 전력다운단(301)의 신호에 의해 선택적으로 연산증폭기를 동작시킴을 알 수 있다. 상기 바이어스단(302)과 전력 다운단(301)을 통해 동시에 입력하도록 하여 연산증폭기를 구동하는 이유는 다음과 같다. 차동증폭기회로에서 제4도의 (4a), (4b)의 2개의 제어신호즉, 전력다운단(301)과 바이어스단(302)를 동시에 사용하여서 전력소모를 최소화하고자 하는데 있다. 즉, 제4도의 (4a)의 전력다운단(301)의 신호가 엑티브 로우일 때와 (4b)의 바이어스단(302)의 신호가 엑티브 하이일 때만 차동증폭기가 동작을 하고, 그렇지 않을 경우에는 동작이 되지 않도록 한다.Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 3 to 4, in the conventional operational amplifier, as shown in FIG. 2, currents l1 and l2 are always present in the N. PMOS transistors Q5 and Q6. It is supposed to flow. Also in the example of the present invention as shown in FIG. 3, such an operation may occur. Therefore, the present invention is to reduce the current consumption by connecting the PMOS transistor (Q101) and the current down and biasing provided to the power down stage 301 and the vise stage 302. In the operational amplifier configured as shown in FIG. 3 of the present invention, waveforms as shown in FIGS. 4A and 4B are received as control signals. In the case of T1 and T2 of (4a), the input signal of the bias stage 302 is When it is low, transistors Q5 and Q7 are turned off so that the operational amplifier does not operate. At this time, currents l1 and l2 do not flow. However, in the case of T3 and T5 of FIG. 4A, when the signal of the bias terminal 302 and the signal of the power down terminal 301 are high, the N, PMOS transistors Q5 and Q7 are turned ON. OFF. At this time, since the NMOS transistor Q5 is ON, the current l1 flows, but since the PMOS transistor Q101 is OFF, the current l2 does not flow even though the NMOS transistor Q7 is on. On the other hand, in the case of T4 and T6 of (4a), when the bias stage 302 is high and the power down stage 301 is low, the NMOS transistors Q5 and Q9 and the PMOS transistor Q101 are all ON. This causes the operational amplifier to operate normally. As described above, when the bias stage 302 is low, the operational amplifier is not operated. When the bias stage 302 is low, the operational amplifier is selectively operated by the signal of the power down stage 301. The reason for driving the operational amplifier by simultaneously inputting through the bias stage 302 and the power down stage 301 is as follows. In the differential amplifier circuit, two control signals (4a) and (4b) of FIG. 4, that is, the power down stage 301 and the bias stage 302 are simultaneously used to minimize power consumption. That is, the differential amplifier operates only when the signal of the power down terminal 301 of 4a of FIG. 4 is active low and when the signal of the bias terminal 302 of 4b is active high. Do not operate.
제3도는 1개의 차동증폭기만을 사용하여 구동한 예이지만 하나의 바이어스단(302)에서 발생하는 하나의 바이어스신호로 여러개의 차동증폭기가 실장된 시스템에서 각각의 차동증폭기를 구동하는 경우 각각의 차동증폭기의 전력다운단(301)으로 인가되는 각각의 전력다운신호에 의해 선택적으로 동작토록 구성되어 있다. 따라서 1개의 차동증폭기만을 사용하고자 할 때 상기 바이어스단(302)에 바이어스신호를 제공하여 인에이블(Enable)하면 차동증폭기의 전체가 동시에 인에이블되나 전력다운단으로 인가되는 신호는 여러 차동증폭기의 각각 별도로 인가하여 구동 출력을 발생하도록 구성되어 있다. 그리고 상기 바이어스단(302)의 신호가 없으면 여러 차동증폭기는 전체 동시에 디스에이블 된다. 따라서 여러 차동증폭기가 바이어스단(302)의 바이어스신호에 의해 동시에 인에이블되더라도, 해당 각각 다른 전력다운단(301)의 전력다운신호에 의해 원하는 차동증폭기만 구동되므로 전류소모를 최소화시킬수 있다.3 is an example of driving using only one differential amplifier, but when driving each differential amplifier in a system in which several differential amplifiers are mounted with one bias signal generated from one bias stage 302, each differential amplifier Each power down signal applied to the power down stage 301 is configured to operate selectively. Therefore, when only one differential amplifier is to be used, when the bias signal is provided to the bias stage 302 and enabled (Enable), the entire differential amplifier is enabled at the same time, but the signal applied to the power down stage is applied to each of several differential amplifiers. It is configured to generate a drive output by applying separately. In the absence of the signal of the bias stage 302, several differential amplifiers are disabled at the same time. Therefore, even if several differential amplifiers are simultaneously enabled by the bias signal of the bias stage 302, only the desired differential amplifier is driven by the power down signals of the respective different power down stages 301, thereby minimizing the current consumption.
상술한 바와같이 디지탈 회로에 연산증폭기를 동작시킬 필요가 없을 경우 해당 차동증폭기에서는 전류를 흐르지 않도록 하여 전류소모를 최소화시킬 수 있는 이점이 있다.As described above, when the operational amplifier does not need to be operated in the digital circuit, there is an advantage of minimizing the current consumption by preventing the current from flowing in the corresponding differential amplifier.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950023994A KR0145857B1 (en) | 1995-08-03 | 1995-08-03 | Current consumption optimization circuit in operational amplifier |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950023994A KR0145857B1 (en) | 1995-08-03 | 1995-08-03 | Current consumption optimization circuit in operational amplifier |
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| KR970013645A KR970013645A (en) | 1997-03-29 |
| KR0145857B1 true KR0145857B1 (en) | 1998-12-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100784535B1 (en) * | 2006-02-20 | 2007-12-11 | 엘지전자 주식회사 | Operational amplifier and device and method for driving LCD using the same |
| KR101010141B1 (en) * | 2004-07-16 | 2011-01-24 | 주식회사 하이닉스반도체 | Differential amplifier |
-
1995
- 1995-08-03 KR KR1019950023994A patent/KR0145857B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101010141B1 (en) * | 2004-07-16 | 2011-01-24 | 주식회사 하이닉스반도체 | Differential amplifier |
| KR100784535B1 (en) * | 2006-02-20 | 2007-12-11 | 엘지전자 주식회사 | Operational amplifier and device and method for driving LCD using the same |
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| Publication number | Publication date |
|---|---|
| KR970013645A (en) | 1997-03-29 |
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