CN108696275B

CN108696275B - Buffer circuit

Info

Publication number: CN108696275B
Application number: CN201710223228.0A
Authority: CN
Inventors: 陈明东; 林惠祯; 王又法
Original assignee: Guangbao Technologies Singapore Private Ltd
Current assignee: Guangbao Technologies Singapore Private Ltd
Priority date: 2017-04-07
Filing date: 2017-04-07
Publication date: 2021-11-12
Anticipated expiration: 2037-04-07
Also published as: CN108696275A

Abstract

The invention provides a buffer circuit. The buffer circuit operates at a working voltage and receives the working voltage from an input end thereof, wherein the working voltage is controlled in a voltage interval. The buffer circuit at least comprises a high-voltage constant-current buffer circuit. In the high-voltage constant-current buffer circuit, the source electrode of the first NMOS transistor is grounded, and the two drain electrodes of the first PMOS transistor and the first NMOS transistor are connected. The source electrode of the second PMOS transistor is connected with the input end of the buffer circuit, and the drain electrode of the second PMOS transistor is connected with the source electrode of the first PMOS transistor. The input end of the series current mirror is connected with the input end of the buffer circuit, and the output end of the series current mirror is connected with the grid of the first PMOS transistor and the grid of the second PMOS transistor. The first PMOS transistor is a high voltage PMOS transistor, the first NMOS transistor is a low voltage NMOS transistor, and the second PMOS transistor is a low voltage PMOS transistor. The buffer circuit provided by the invention can improve the reliability of the circuit.

Description

Buffer circuit

Technical Field

The present invention relates to the field of electronic circuits, and more particularly, to a buffer circuit capable of providing a stable output current even when an operating voltage varies within a wide voltage range.

Background

In an Intelligent Power Module (IPM) application, the buffer circuit is usually used to provide sufficient driving Power to the load. For the smart power module, the load is mostly Bipolar Junction Transistor (BJT), so the current outputted from the buffer circuit to the load cannot be too large. The reason is that if the current output from the buffer circuit to the load is too large, a propagation delay (propagation delay) of the output of the smart power module will be caused.

Referring to fig. 1, fig. 1 is a circuit diagram of a buffer circuit according to the prior art. As shown in fig. 1, in order to enable the buffer circuit 100 to operate in a larger operating voltage range, the conventional buffer circuit 100 is configured with an NMOS transistor MN1 'and a PMOS transistor MP 1', and the NMOS transistor MN1 'and the PMOS transistor MP 1' are both designed as high voltage transistors. In addition, another PMOS transistor MP2 'is configured in the conventional buffer circuit 100 to limit the voltage at the output terminal of the level shifter and the voltage at the gate of the PMOS transistor MP 1' to a predetermined voltage. The source of the PMOS transistor MP2 ' is connected to the input terminal of the buffer circuit 100 for receiving the operating voltage, and the gate and the drain of the PMOS transistor MP2 ' are connected to the gate of the PMOS transistor MP1 '.

However, although the buffer circuit 100 can operate in a large operating voltage range, its output current changes with the operating voltage. More specifically, the output current of such a buffer circuit increases significantly with an increase in the operating voltage. That is, if the buffer circuit is used in an Intelligent Power Module (IPM) application, it may provide an excessive output current to a load (e.g., NPN bjt), which may cause a delay in the transmission of the output of the IPM.

Disclosure of Invention

The invention discloses a buffer circuit. The buffer circuit operates at a working voltage and receives the working voltage from an input terminal of the buffer circuit, wherein the working voltage is controlled in a voltage interval. The buffer circuit at least comprises a high-voltage constant-current buffer circuit, and the high-voltage constant-current buffer circuit comprises a first PMOS transistor, a first NMOS transistor, a second PMOS transistor and a series-connection type current mirror. In the high-voltage constant-current buffer circuit, the source electrode of the first NMOS transistor is grounded, and the drain electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor. The source of the second PMOS transistor is connected to the input end of the buffer circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The input end of the series current mirror is connected to the input end of the buffer circuit, and the output end of the series current mirror is connected to the grid of the first PMOS transistor and the grid of the second PMOS transistor. In the high-voltage constant-current buffer circuit, the first PMOS transistor is designed as a high-voltage PMOS transistor, the first NMOS transistor is designed as a high-voltage NMOS transistor, and the second PMOS transistor is designed as a low-voltage PMOS transistor, so that the change of the output current of the buffer circuit caused by the buffer circuit working at different working voltages is reduced.

In the buffer circuit, the series current mirror includes a fourth PMOS transistor and a fifth PMOS transistor. The source electrode of the fourth PMOS transistor is the input end of the series current mirror, the drain electrode of the fifth PMOS transistor is the output end of the series current mirror, the drain electrode of the fourth PMOS transistor is connected with the source electrode of the fifth PMOS transistor, and the grid electrode of the fourth PMOS transistor is connected with the grid electrode of the fifth PMOS transistor and is further connected with the output end of the series current mirror.

In the buffer circuit, the fourth PMOS transistor of the series current mirror is a low voltage PMOS transistor, and the fifth PMOS transistor is a high voltage PMOS transistor.

In the buffer circuit, the buffer circuit further includes a resistor. The resistor is connected with the output end of the series-connection type current mirror, the grid electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor.

In the buffer circuit, the buffer circuit further comprises a current accelerating circuit. The current accelerating circuit is connected with the high-voltage constant-current buffer circuit and the pulse generator and receives a switching signal of the pulse generator. The pulse generator outputs a narrow pulse signal to turn on the second NMOS transistor to drive a PMOS current mirror in the current accelerating circuit, and the PMOS current mirror directly outputs a current to increase the output current of the high-voltage constant-current buffer circuit. When the input signal of the pulse generator is converted from low potential to high potential, the pulse generator outputs a narrow pulse signal to the current accelerating circuit, so that the current accelerating circuit amplifies the received output current of the high-voltage constant-current buffer circuit and outputs the amplified output current.

In the buffer circuit, the current accelerating circuit comprises a PMOS current mirror, a second NMOS transistor and a third NMOS transistor. The drain of the second NMOS transistor is connected to the PMOS current mirror, and the gate of the second NMOS transistor is connected to the pulse generator. The drain of the third NMOS transistor is connected to the source of the second NMOS transistor, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor receives a buffer bias voltage. When the input signal of the pulse generator is converted from low potential to high potential, the pulse generator outputs a narrow pulse signal to turn on the second NMOS transistor, so that the third NMOS transistor provides an accelerating current to the PMOS current mirror, and the output current of the high-voltage constant-current buffer circuit received by the current accelerating circuit is amplified and then output.

In the buffer circuit, the second NMOS transistor is a high voltage NMOS transistor.

In the buffer circuit, the PMOS current mirror includes a sixth PMOS transistor and a seventh PMOS transistor with two gates connected. The sources of the sixth PMOS transistor and the seventh PMOS transistor are both connected to the input terminal of the buffer circuit, and the two gates and the two drains of the sixth PMOS transistor and the seventh PMOS transistor are further connected to the drain of the second NMOS transistor.

In the buffer circuit, the sixth PMOS transistor is a low voltage PMOS transistor, and the seventh PMOS transistor is a high voltage PMOS transistor.

In the buffer circuit, the voltage interval is 4.5V to 30V.

In summary, since the first PMOS transistor and the first NMOS transistor in the high-voltage constant-current buffer circuit are designed as high-voltage transistors, the buffer circuit provided by the invention can operate in a wide range of operating voltages. Moreover, the configuration of the second PMOS transistor and the series current mirror enables the buffer circuit to provide a stable low output current even under different operating voltages. In addition, when the buffer circuit operates at a lower working voltage, the current accelerating circuit can amplify and output the output current of the high-voltage constant-current buffer circuit so as to stabilize the output current of the buffer circuit.

For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are included to illustrate, but are not to be construed as limiting the scope of the invention.

Drawings

Fig. 1 is a circuit diagram of a buffer circuit shown according to the prior art.

Fig. 2 is a circuit diagram of a buffer circuit according to an embodiment of the present invention.

Fig. 3 is a graph showing the relationship between the output current and the operating voltage according to the buffer circuit shown in fig. 1 and 2.

Fig. 4 is a circuit diagram of a buffer circuit according to another embodiment of the invention.

Fig. 5 is a graph of output voltage versus time for a load of a smart power module driven according to the buffer circuit shown in fig. 4.

Detailed Description

Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are disclosed so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, like numerals refer to like elements throughout.

(buffer circuit embodiment)

Referring to fig. 2, fig. 2 is a circuit diagram of a buffer circuit according to an embodiment of the invention. The Buffer Circuit 200 provided in this embodiment at least includes a High Voltage Constant Current Buffer Circuit (High Voltage Constant Current Buffer Circuit) CA, and as shown in fig. 2, an input terminal Vin of the High Voltage Constant Current Buffer Circuit CA is an input terminal of the Buffer Circuit 200. The buffer circuit 200 operates at a working voltage, and the working voltage is provided by a supply voltage Vcc received by an input terminal of the buffer circuit 200. Therefore, the supply voltage Vcc is controlled in a voltage interval. In the present embodiment, the voltage interval of the supply voltage Vcc received by the input terminal of the buffer circuit 200 may be 4.5 volts to 30 volts. In order to operate in the voltage range of 4.5v to 30v, the high voltage constant current buffer circuit CA includes a first PMOS transistor MP1 and a first NMOS transistor MN1, wherein the source of the first NMOS transistor MN1 is grounded, and the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN 1. In addition, to support the larger supply voltage Vcc of the buffer circuit 200, the first PMOS transistor MP1 is designed as a high voltage PMOS transistor, and the first NMOS transistor MN1 is designed as a high voltage NMOS transistor.

It should be noted that, unlike the prior art shown in fig. 1, in the present embodiment, the high-voltage constant current buffer circuit CA further includes a second PMOS transistor MP2, a series current mirror SM and a resistor R1. As shown in fig. 2, the source of the second PMOS transistor MP2 is coupled to the supply voltage Vcc of the high-voltage constant current buffer circuit CA, and the drain of the second PMOS transistor MP2 is connected to the source of the first PMOS transistor MP 1. In addition, the input terminal of the series current mirror SM is coupled to the supply voltage Vcc of the high-voltage constant current buffer circuit CA, and the output terminal of the series current mirror SM is connected to the high-voltage constant current buffer circuit CA. The other end of the resistor R1 is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP 2. Thus, the gate voltage of the first PMOS transistor MP1 and the gate voltage of the second PMOS transistor MP2 are controlled by the series current mirror SM and the resistor R1.

Further, the series current mirror SM is formed by a series connection of a fourth PMOS transistor MP4 and a fifth PMOS transistor MP 5. The fourth PMOS transistor MP4 needs to be designed as a low voltage PMOS transistor and the fifth PMOS transistor MP5 needs to be designed as a high voltage PMOS transistor, so that the cascode current mirror SM can have a similar circuit configuration and scaled size compared to a high voltage current mirror formed by the first PMOS transistor MP1 and the second PMOS transistor MP 2. The source of the fourth PMOS transistor MP4 is coupled to the supply voltage Vcc of the high-voltage constant current buffer circuit CA, and the drain of the fifth PMOS transistor MP5 is the output terminal of the series current mirror SM. The drain of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP 5.

As mentioned above, the high-voltage constant-current buffer circuit CA includes the resistor R1, and as shown in fig. 2, the resistor R1 is connected between the output terminal of the series current mirror SM, the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP 2. In more detail, the drain of the fifth PMOS transistor MP5, the gate of the fourth PMOS transistor MP4, and the gate of the fifth PMOS transistor MP5 are all connected to the resistor R1. Since the bias voltages of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 in the series current mirror SM are susceptible to the temperature variation of the circuit, the resistor R1 is required for temperature compensation. That is, the resistor R1 helps to reduce the temperature sensitivity of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 in the series current mirror SM.

In addition, since the gate of the fourth PMOS transistor MP4 is connected to the gate of the fifth PMOS transistor MP5, the output impedance of the series current mirror SM increases. The increased output impedance of the series current mirror SM makes the output current Iout of the buffer circuit 200 less prone to variation due to different supply voltages Vcc. Referring to fig. 3, fig. 3 is a graph illustrating a relationship between an output current and an operating voltage of the buffer circuit shown in fig. 1 and fig. 2. As can be seen from fig. 3, if the supply voltage of the conventional buffer circuit 100 increases from 5 volts to 35 volts, the output current Iout thereof increases approximately from 200 μ a to 350 μ a (as shown by the curve CT1 in fig. 3); however, if the operating voltage of the buffer circuit 200 provided in the present embodiment increases from 5 volts to 35 volts, the output current Iout increases from 225 μ a to 250 μ a (as shown by the curve CT2 in fig. 3). That is, since only the PMOS transistor MP 1' is provided, the output current Iout of the conventional buffer circuit 100 varies greatly (350 μ a-200 μ a ═ 150 μ a) when operating at different supply voltages, but the buffer circuit 200 provided in this embodiment can reduce the output current Iout variation (250 μ a-225 μ a ═ 25 μ a) when the buffer circuit 200 operates at different supply voltages because the series current mirror SM shown in fig. 2 is additionally provided.

More specifically, referring to fig. 3 again, when operating at different supply voltages Vcc, compared to the conventional buffer circuit 100 only provided with the PMOS transistor MP 1', the output current Iout of the buffer circuit 200 provided in the present embodiment not only has smaller variation, but also has smaller current value, which is favorable for applying the buffer circuit 200 provided in the present embodiment to the smart power module to drive the load of the smart power module with the output current, such as: NPN bipolar junction transistor. The reason is that, in general, the load of the smart power module can work in a larger voltage range, but needs to work in a smaller output current. If the current output from the buffer circuit to the load of the smart power module is too large, a propagation delay (propagation delay) of the output of the smart power module will be caused.

In addition, as shown in fig. 2, in order to provide sufficient voltage to the high voltage constant current buffer circuit CA, two inverters INV1 and INV2 and a level shifter LS are further provided in the circuit shown in fig. 2, and the inverters INV1 and INV2 and the level shifter LS are connected to the high voltage constant current buffer circuit CA. In more detail, the inverter INV1 is connected to the inverter INV2 and receives the supply voltage Vcc1, and the inverter INV2 is connected to the level shifter LS. The level shifter LS is configured to increase the supply voltage Vcc1, and then supply the increased supply voltage Vcc1 to the high-voltage constant current buffer circuit CA.

In the present embodiment, the inverters INV1 and INV2 are CMOS inverters each composed of an NMOS transistor and a PMOS transistor. In addition, the level shifter LS is composed of three PMOS transistors and three NMOS transistors. Notably, since the level shifter LS is configured to increase the supply voltage Vcc1, two of the NMOS transistors in the level shifter LS must be designed as high voltage NMOS transistors capable of withstanding higher voltages. In addition, as shown in fig. 2, the NMOS transistor in the level shifter LS, which is designed as a low voltage NMOS transistor, has its gate coupled to a buffer bias voltage Vb 1.

To describe the circuit design of the buffer circuit of the present invention in more detail, an embodiment will be described in further detail below.

In the following embodiment, portions different from those of the above-described embodiment of fig. 2 will be described, and the remaining omitted portions are the same as those of the above-described embodiment of fig. 2. Also, for convenience of explanation, like reference numerals or signs refer to like components.

[ Another embodiment of a buffer circuit ]

Referring to fig. 4, fig. 4 is a circuit diagram of a buffer circuit according to another embodiment of the invention. The difference between the present embodiment and the foregoing embodiment shown in fig. 2 is that, in addition to the high-voltage constant-current buffer circuit CA, the buffer circuit 400 provided in the present embodiment further includes a current accelerating circuit CS.

As shown in fig. 4, the current accelerating circuit CS includes a pulse generator PG, a PMOS current mirror PM, a second NMOS transistor NM2, and a third NMOS transistor NM 3. A gate of the second NMOS transistor NM2 is connected to the output terminal of the pulse generator PG, and a drain of the second NMOS transistor NM2 is connected to the input terminal of the PMOS current mirror PM. In addition, the drain of the third NMOS transistor NM3 is connected to the source of the second NMOS transistor NM2, the source of the third NMOS transistor NM3 is grounded, and the gate of the third NMOS transistor NM3 receives a buffer bias voltage Vb 2.

In addition, the PMOS current mirror PM includes a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7 connected to each other. The source of the sixth PMOS transistor MP6 and the source of the seventh PMOS transistor MP7 are both coupled to the supply voltage of the buffer circuit 400. The gate and drain of the sixth PMOS transistor MP6, and the gate 400 of the seventh PMOS transistor MP7 are connected to the drain of the second NMOS transistor NM 2.

In detail, as shown in fig. 4 again, the voltage received by the input terminal of the pulse generator PG is equal to the input signal received by the input terminal of the buffer circuit 400. When the input signal received by the input terminal of the buffer circuit 400 changes from low potential to high potential, the pulse generator PG generates a narrow pulse signal to turn on the PMOS current mirror PM. The third NMOS transistor NM3 is configured to act as a current source, and the second NMOS transistor NM2 is configured to act as a switch, wherein the gate of the second NMOS transistor NM2 is connected to the output terminal of the pulse generator PG. The second NMOS transistor NM2 is to turn on the third NMOS transistor NM3 as a current source. When the second NMOS transistor NM2 is turned on, the PMOS current mirror PM is turned on, so that an accelerating current flows from the PMOS current mirror PM to the output terminal of the high-voltage constant-current buffer circuit CA, and finally, the current accelerating circuit amplifies the received output current of the high-voltage constant-current buffer circuit CA by the accelerating current and outputs the amplified current.

The main consideration of this design is that, as mentioned above, the buffer circuit 400 provided in this embodiment can be applied in the smart power module to output current to drive the load of the smart power module, such as: NPN bipolar junction transistor. Referring to fig. 5, fig. 5 is a graph of output voltage versus time of a load of the smart power module driven by the buffer circuit shown in fig. 4. As shown in fig. 5, when the buffer circuit 200 operates at a smaller supply voltage Vcc, the current accelerating circuit CS directly outputs the output current of the high-voltage constant-current buffer circuit CA as the output current Iout of the buffer circuit 400 to drive the load (not shown) of the smart power module, in which case the Fall Time (Fall Time) of the output voltage of the smart power module is about 0.06 μ S (as shown by the curve CT3 in fig. 5). In contrast, when the operating voltage at the input terminal of the buffer circuit 400 operates at a smaller supply voltage Vcc, the output current of the high-voltage constant-current buffer circuit CA can be amplified by the accelerating current generated by the current accelerating circuit CS, and then used as the output current Iout of the buffer circuit 400 to drive the load of the smart power module, in which case the falling time of the output voltage of the smart power module is shortened to about 0.04 μ S (as shown by the curve CT4 in fig. 5).

It should be noted that in the present embodiment, the second NMOS transistor in the current accelerating circuit CS is designed as a high voltage NMOS transistor, and the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 in the PMOS current mirror PM are respectively designed as a low voltage PMOS transistor and a high voltage PMOS transistor. The reason why the seventh PMOS transistor MP7 in the PMOS current mirror PM is designed as a high voltage PMOS transistor is because the high voltage PMOS transistor can withstand a larger voltage, so that the current accelerating circuit CS will not damage the circuit 400 even if the buffer circuit operates at a larger supply voltage.

(possible technical effects of the embodiment)

In summary, the buffer circuit provided by the present invention can operate in a wide range of operating voltages, such as: 4.5 volts to 30 volts, and has at least the following advantages:

first, when the buffer circuit is applied to an intelligent power module for outputting current to drive a load of the intelligent power module, the buffer circuit can stably provide low output current even when operating in a wide range of operating voltages, so as to prevent the load of the intelligent power module from being excessively driven to cause transmission delay of the output of the intelligent power module.

In addition, the buffer circuit provided by the invention is also provided with a current accelerating circuit. When the buffer circuit operates at a lower supply voltage, the output current of the high-voltage constant-current buffer circuit is amplified (i.e., added with the accelerating current generated by the current accelerating circuit), and then is used as the output current of the buffer circuit to drive the load of the intelligent power module. This can shorten the fall time of the output voltage of the intelligent power module.

The above description is only an embodiment of the present invention, and is not intended to limit the claims of the present invention.

Claims

1. A buffer circuit, which operates at a working voltage and is received by an input terminal of the buffer circuit, wherein the working voltage is controlled in a voltage interval, and the buffer circuit comprises:

a high voltage constant current snubber circuit, comprising:

the source electrode of the first NMOS transistor is grounded, and the drain electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor;

the source electrode of the second PMOS transistor is connected to the input end of the buffer circuit, and the drain electrode of the second PMOS transistor is connected to the source electrode of the first PMOS transistor; and

the input end of the series current mirror is connected to the input end of the buffer circuit, and the output end of the series current mirror is connected to the grid electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor; and

the current accelerating circuit is connected with the high-voltage constant-current buffer circuit and a pulse generator and receives a switching signal of the pulse generator;

the second PMOS transistor of the high-voltage constant-current buffer circuit is a low-voltage PMOS transistor, the first PMOS transistor of the high-voltage constant-current buffer circuit is a high-voltage PMOS transistor, and the first NMOS transistor of the high-voltage constant-current buffer circuit is a high-voltage NMOS transistor, so that the change of the output current of the buffer circuit caused by the change of the working voltage is reduced;

the pulse generator outputs a narrow pulse signal to turn on a second NMOS transistor to drive a PMOS current mirror in the current accelerating circuit, and the PMOS current mirror directly outputs a current to increase the output current of the high-voltage constant-current buffer circuit;

when an input signal of the pulse generator is converted from a low potential to a high potential, the pulse generator outputs the narrow pulse signal to the current accelerating circuit, so that the current accelerating circuit amplifies and outputs the received output current of the high-voltage constant-current buffer circuit.

2. The buffer circuit of claim 1, wherein the series current mirror comprises:

and the source electrode of the fourth PMOS transistor is the input end of the serial current mirror, the drain electrode of the fifth PMOS transistor is the output end of the serial current mirror, the drain electrode of the fourth PMOS transistor is connected to the source electrode of the fifth PMOS transistor, and the grid electrode of the fourth PMOS transistor is connected with the grid electrode of the fifth PMOS transistor and is further connected to the output end of the serial current mirror.

3. The buffer circuit of claim 2, wherein the fourth PMOS transistor of the series current mirror is a low voltage PMOS transistor and the fifth PMOS transistor is a high voltage PMOS transistor.

4. The buffer circuit of claim 3, wherein the buffer circuit further comprises:

and the resistor is connected with the output end of the series-connection type current mirror, the grid electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor.

5. The buffer circuit of claim 1, wherein the current accelerating circuit comprises:

a PMOS current mirror;

a second NMOS transistor, wherein the drain of the second NMOS transistor is connected to the PMOS current mirror, and the gate of the second NMOS transistor is connected to the pulse generator; and

a third NMOS transistor, a drain of which is connected to a source of the second NMOS transistor, a source of which is grounded, and a gate of which receives a buffer bias voltage;

when the input signal of the pulse generator is converted from a low potential to a high potential, the pulse generator outputs the narrow pulse signal to turn on the second NMOS transistor, so that the third NMOS transistor provides an accelerating current to the PMOS current mirror, and the output current of the high-voltage constant current buffer circuit received by the current accelerating circuit is amplified and then output.

6. The buffer circuit of claim 5, wherein the second NMOS transistor is a high voltage NMOS transistor.

7. The buffer circuit of claim 5, wherein the PMOS current mirror comprises a sixth PMOS transistor and a seventh PMOS transistor connected to each other by two gates, the sources of the sixth PMOS transistor and the seventh PMOS transistor are connected to the input terminal of the buffer circuit, and the two gates and the two drains of the sixth PMOS transistor and the seventh PMOS transistor are further connected to the drain of the second NMOS transistor.

8. The buffer circuit of claim 7, wherein the sixth PMOS transistor is a low voltage PMOS transistor and the seventh PMOS transistor is a high voltage PMOS transistor.

9. The buffer circuit of claim 1, wherein the voltage interval is 4.5V to 30V.