TWI632775B - Buffer circuit - Google Patents

Abstract

A snubber circuit operates at an operating voltage and receives the operating voltage from its input, wherein the operating voltage is controlled to a voltage interval. The buffer circuit includes at least a high voltage constant current buffer circuit. In the high voltage constant current buffer circuit, the source of the first NMOS transistor is grounded, and the first PMOS transistor is connected to the two drains of the first NMOS transistor. The source of the second PMOS transistor is connected to the input end of the buffer circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The input end of the series current mirror is connected to the input end of the buffer circuit, and the output end of the series current mirror is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The first PMOS transistor is a high voltage PMOS transistor, the first NMOS transistor is a low voltage NMOS transistor, and the second PMOS transistor is a low voltage PMOS transistor to reduce the operation of the buffer circuit at different voltages. The change in output current.

Description

Buffer circuit

The present invention relates to a high voltage and constant current buffer circuit, and more particularly to a buffer circuit capable of providing a stable output current even if the operating voltage fluctuates within a wide range of voltage ranges.

In the application of Intelligent Power Module (IPM), the snubber circuit is often used to provide sufficient driving power to the load. For smart power modules, the load is mostly Bipolar Junction Transistor (BJT). Therefore, the current output from the snubber circuit to the load should not be too large. The reason is that if the current output from the snubber circuit to the load is too large, the propagation delay of the output of the smart power module will be caused.

Please refer to FIG. 1. FIG. 1 is a circuit diagram of a buffer circuit according to the prior art. As shown in FIG. 1, in order to enable the buffer circuit 100 to operate in a large operating voltage range, an NMOS transistor MN1' and a PMOS transistor MP1' are disposed in the conventional buffer circuit 100, and the NMOS transistor is disposed. Both MN1' and this PMOS transistor MP1' are designed as high voltage transistors. In addition to this, another PMOS transistor MP2' is disposed in the conventional buffer circuit 100 to limit the output terminal voltage of the level shifter and the gate voltage of the PMOS transistor MP1' to a predetermined voltage. The source of the PMOS transistor MP2' is connected to the input end of the buffer circuit 100 to receive the operating voltage, and the gate of the PMOS transistor MP2' is connected to the drain and further connected to the gate of the PMOS transistor MP1'. .

However, such a snubber circuit 100 can operate in a large operating voltage region. Between, but its output current will change with the operating voltage. More specifically, the output current of such a snubber circuit increases significantly as the operating voltage increases. In other words, if such a snubber circuit is used in an intelligent power module (IPM) application, it may provide excessive output current to the load (eg, NPN bipolar junction transistor), resulting in The transmission delay of the output of the smart power module.

Embodiments of the present invention provide a buffer circuit that operates at an operating voltage and receives the operating voltage from an input terminal of the buffer circuit, wherein the operating voltage is controlled to a voltage interval. The buffer circuit includes at least a high voltage constant current buffer circuit, and the high voltage constant current buffer circuit includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a series current mirror. In the high voltage constant current buffer circuit, the source of the first NMOS transistor is grounded, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the second PMOS transistor is connected to the input end of the buffer circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The input end of the series current mirror is connected to the input end of the buffer circuit, and the output end of the serial current mirror is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor. In the high voltage constant current buffer circuit, the first PMOS transistor is designed as a high voltage PMOS transistor, the first NMOS transistor is designed as a high voltage NMOS transistor, and the second PMOS transistor is designed as a low voltage PMOS transistor to reduce the variation of the output current of the snubber circuit caused by the snubber circuit operating at different operating voltages.

In one of the embodiments of the present invention, the snubber circuit further includes a current accelerating circuit. The current accelerating circuit is connected to the high voltage constant current buffer circuit and the pulse generator to receive a switching signal of the pulse generator. The pulse generator outputs a narrow pulse signal as a switching signal to turn on the second NMOS transistor to drive the PMOS current mirror in the current acceleration circuit, so that the PMOS current mirror directly outputs a current to increase the high voltage. The output current of the constant current buffer circuit. When the input signal of the pulse generator is changed from a low potential to a high potential, the pulse generator outputs a narrow pulse signal to the current acceleration circuit, so that the current acceleration circuit amplifies the output current of the received high voltage constant current buffer circuit and outputs the output current.

High voltage constant current buffer circuit high voltage constant current buffer circuit high voltage constant current buffer circuit high voltage constant current buffer circuit in summary, because the first PMOS transistor and the first NMOS transistor in the high voltage constant current buffer circuit are designed as high voltage electricity The crystal, the snubber circuit provided by the present invention is capable of operating over a wide range of operating voltages. Furthermore, the configuration of the second PMOS transistor and the series current mirror allows the snubber circuit to provide a stable low output current at different operating voltages. In addition, when the buffer circuit operates at a lower operating voltage, the current accelerating circuit can amplify the output current of the high voltage constant current buffer circuit and output it to stabilize the output current of the buffer circuit.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

100, 200, 400‧‧‧ buffer circuit

Vcc, Vcc1‧‧‧ supply voltage

INV1, INV2‧‧‧ inverter

LS‧‧‧ position shifter

Vb1, Vb2‧‧‧ buffer bias

MP1', MP2'‧‧‧ PMOS transistor

MN1'‧‧‧ NMOS transistor

MP1‧‧‧First PMOS transistor

MP2‧‧‧second PMOS transistor

MN1‧‧‧First NMOS transistor

MN2‧‧‧Second NMOS transistor

MN3‧‧‧ Third NMOS transistor

Iout‧‧‧Output current

MP4‧‧‧fourth PMOS transistor

MP5‧‧‧ Fifth PMOS transistor

MP6‧‧‧6th PMOS transistor

MP7‧‧‧ seventh PMOS transistor

SM‧‧‧Spliced Current Mirror

PM‧‧‧PMOS current mirror

CA‧‧‧High voltage constant current buffer circuit

CS‧‧‧current accelerating circuit

PG‧‧‧pulse generator

R1‧‧‧ resistance

Vin‧‧‧ input

CT1, CT2, CT3, CT4‧‧‧ curves

1 is a circuit diagram of a snubber circuit according to the prior art.

2 is a circuit diagram of a buffer circuit provided by an embodiment of the present invention.

FIG. 3 is a graph showing the relationship between the output current and the operating voltage of the snubber circuit illustrated in FIGS. 1 and 2.

4 is a circuit diagram of a buffer circuit provided by another embodiment of the present invention.

FIG. 5 is a graph showing the relationship between the output voltage of the load of the smart power module driven by the buffer circuit shown in FIG. 4 and time.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the concept of the present invention may be The invention is in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the figures, like numerals are used to indicate like elements.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "and/or" includes any of the associated listed items and all combinations of one or more.

[Example of snubber circuit]

Please refer to FIG. 2. FIG. 2 is a circuit diagram of a buffer circuit according to an embodiment of the present invention. The buffer circuit 200 provided in this embodiment includes at least a high voltage constant current buffer circuit CA. As shown in FIG. 2A, the input terminal Vin of the high voltage constant current buffer circuit CA is the input of the buffer circuit 200. end. The buffer circuit 200 operates at an operating voltage, and the operating voltage is provided by a supply voltage Vcc received at an input of the buffer circuit 200. Therefore, the supply voltage Vcc is controlled to a voltage interval. In this embodiment, the voltage interval of the supply voltage Vcc received at the input end of the buffer circuit 200 may be 4.5 volts to 30 volts. In order to be able to operate in a voltage range of 4.5 volts to 30 volts, the high voltage constant current buffer circuit CA includes a first PMOS transistor MP1 and a first NMOS transistor MN1, wherein the source of the first NMOS transistor MN1 is grounded, and the first PMOS The drain of the transistor MP1 is connected to the drain of the first NMOS transistor MN1. Furthermore, in order to withstand the large supply voltage Vcc of the snubber circuit 200, the first PMOS transistor MP1 is designed as a high voltage PMOS transistor, and the first NMOS transistor MN1 is designed as a high voltage NMOS transistor.

Notably, unlike the prior art illustrated in FIG. 1, in the present embodiment, the high voltage constant current buffer circuit CA further includes a second PMOS transistor MP2 and a series current mirror SM and a resistor R1. As shown in Figure 2, the second PMOS transistor The source of the MP2 is coupled to the supply voltage Vcc of the high voltage constant current buffer circuit CA, and the drain of the second PMOS transistor MP2 is connected to the source of the first PMOS transistor MP1. In addition, the input end of the series current mirror SM is coupled to the supply voltage Vcc of the high voltage constant current buffer circuit CA, and the output end of the series current mirror SM is connected. The other end of the resistor R1 is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2. Thus, the gate voltage of the first PMOS transistor MP1 and the gate voltage of the second PMOS transistor MP2 are controlled by the series current mirror SM and the resistor R1.

Further, the series current mirror SM is composed of a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5 connected in series. The fourth PMOS transistor MP4 needs to be designed as a low voltage PMOS transistor, and the fifth PMOS transistor MP5 needs to be designed as a high voltage PMOS transistor, so that compared to the first PMOS transistor MP1 and the second PMOS transistor A high voltage current mirror composed of a crystal MP2, the series current mirror SM can have a similar circuit structure and a proportional size. The source of the fourth PMOS transistor MP4 is coupled to the supply voltage Vcc of the high voltage constant current buffer circuit CA, and the output of the fifth PMOS transistor MP5 is the output terminal of the serial current mirror SM. The drain of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5.

As described above, the high voltage constant current buffer circuit CA includes a resistor R1, and as shown in FIG. 2, the resistor R1 is connected to the output terminal of the series current mirror SM, the gate of the first PMOS transistor MP1, and the second PMOS battery. Between the gates of the crystal MP2. In more detail, the drain of the fifth PMOS transistor MP5, and the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP5 are both connected to the resistor R1. Since the bias voltages of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 in the series current mirror SM are susceptible to circuit temperature variations, the resistor R1 needs to be set for temperature compensation. That is, the resistor R1 helps to reduce the sensitivity of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 in the series current mirror SM to temperature.

Further, since the gate of the fourth PMOS transistor MP4 is connected to the gate of the fifth PMOS transistor MP5, the output impedance of the series current mirror SM is increased. The increase in the output impedance of the series current mirror SM makes the output current Iout of the snubber circuit 200 less susceptible to variations due to its operation at different supply voltages Vcc. Please refer to FIG. 3. FIG. 3 is a graph showing the relationship between the output current and the operating voltage of the snubber circuit according to FIG. 1 and FIG. As can be seen from FIG. 3, when the conventional snubber circuit 100 increases its supply voltage from 5 volts to 35 volts, its output current Iout increases from 200 μA to 350 μA (as shown by curve CT1 in FIG. 3); however, When the operating voltage of the buffer circuit 200 provided by the embodiment is increased from 5 volts to 35 volts, the output current Iout is increased from about 225 μA to 250 μA (as shown by the curve CT2 in FIG. 3). That is, since only the PMOS transistor MP1' is provided, the conventional snubber circuit 100 has a large change in the output current Iout when operating at different supply voltages (350 μA - 200 μA = 150 μA), but is provided by this embodiment. The buffer circuit 200 is further provided with the series current mirror SM shown in FIG. 2, so that the change of the output current Iout when the buffer circuit 200 operates at different supply voltages is slowed down (250 μA - 225 μA = 25 μA).

More specifically, referring to FIG. 3, when operating at different supply voltages Vcc, the output of the buffer circuit 200 provided in this embodiment is compared to the conventional buffer circuit 100 in which only the PMOS transistor MP1' is provided. The current Iout is not only changed less, but also has a smaller current value. Therefore, the buffer circuit 200 provided in this embodiment is applied to the smart power module for outputting current to drive the smart power module. The load, such as: NPN bipolar junction transistor. The reason is that, in general, the load of the smart power module can work in a larger voltage range, but it needs to work with a smaller output current. If the current output from the snubber circuit to the load of the smart power module is too large, the propagation delay of the output of the smart power module will be caused.

In addition, as shown in FIG. 2, in order to provide a sufficient voltage to the high voltage constant current buffer circuit CA, in the circuit shown in FIG. 2, two inverters INV1 are additionally provided. Together with INV2, and a level shifter LS, the inverters INV1 and INV2 and the level shifter LS are both connected to the high voltage constant current buffer circuit CA. In more detail, the inverter INV1 is connected to the inverter INV2, and receives the supply voltage Vcc1, and the inverter INV2 is connected to the level shifter LS. The level shifter LS is set to increase the supply voltage Vcc1, and then the boosted supply voltage Vcc1 is supplied to the high voltage constant current buffer circuit CA.

In this embodiment, the inverter INV1 and the inverter INV2 are both CMOS inverters composed of an NMOS transistor and a PMOS transistor. In addition, the level shifter LS is composed of three PMOS transistors and three NMOS transistors. Notably, since the level shifter LS is set to increase the supply voltage Vcc1, two of the NMOS transistors in the level shifter LS must be designed to withstand higher voltages of high voltage NMOS Crystal. In addition, as shown in FIG. 2, the NMOS transistor of the level shifter LS designed as a low voltage NMOS transistor has its gate coupled to a buffer bias voltage Vb1.

In order to explain the circuit design of the snubber circuit of the present invention in more detail, an embodiment will be further described below.

In the following embodiments, portions different from the above-described embodiment of Fig. 2 will be described, and the remaining omitted portions are the same as those of the above-described embodiment of Fig. 2. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

[Another embodiment of the buffer circuit]

Please refer to FIG. 4. FIG. 4 is a circuit diagram of a buffer circuit according to another embodiment of the present invention. The difference between this embodiment and the foregoing embodiment shown in FIG. 2 is that, in addition to the high voltage constant current buffer circuit CA, the buffer circuit 400 provided in this embodiment further includes a current accelerating circuit CS.

As shown in FIG. 4, the current accelerating circuit CS includes a pulse generator PG, a PMOS current mirror PM, a second NMOS transistor NM2, and a third NMOS transistor NM3. The gate of the second NMOS transistor NM2 is connected to the output of the pulse generator PG, and the drain of the second NMOS transistor NM2 is connected to the input of the parallel current mirror PM end. In addition, the drain of the third NMOS transistor NM3 is connected to the source of the second NMOS transistor NM2, the source of the third NMOS transistor NM3 is grounded, and the gate of the third NMOS transistor NM3 receives a buffer bias Vb2. .

In addition, the parallel current mirror PM includes a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7 to which two gates are connected. The source of the sixth PMOS transistor MP6 and the source of the seventh PMOS transistor MP7 are coupled to the supply voltage of the buffer circuit 400. The gate and the drain of the sixth PMOS transistor MP6 and the gate 400 of the seventh PMOS transistor MP7 are connected to the drain of the second NMOS transistor NM2.

In detail, as shown in FIG. 4, the voltage received at the input of the pulse generator PG is equal to the input signal received at the input of the buffer circuit 400. When the input signal received at the input of the buffer circuit 400 is turned from a low level to a high level, the pulse generator PG generates a narrow pulse signal to turn on the PMOS current mirror PM. The third NMOS transistor NM3 is provided as a current source, and the second NMOS transistor NM2 is provided as a switch, wherein the gate of the second NMOS transistor NM2 is connected to the output of the pulse generator PG. The second NMOS transistor NM2 is used to turn on the third NMOS transistor NM3 as a current source. When the second NMOS transistor NM2 is turned on, the PMOS current mirror PM is turned on, and then an accelerating current flows from the PMOS current mirror PM to the output terminal of the high voltage constant current buffer circuit CA. Finally, the current accelerating circuit buffers the received high voltage constant current. The output current of the circuit is amplified by the acceleration current and output.

The main consideration of this design is that, as described above, the buffer circuit 400 provided in this embodiment can be applied to a smart power module for outputting current to drive the load of the smart power module, such as: NPN dual polarity connection. Surface transistor. Please refer to FIG. 5. FIG. 5 is a graph showing the relationship between the output voltage of the load of the smart power module driven by the buffer circuit shown in FIG. As shown in FIG. 5, when the buffer circuit 200 operates on a small supply voltage Vcc, the current acceleration circuit CS directly outputs the output current of the high voltage constant current buffer circuit CA as the output current Iout of the buffer circuit 400 to drive the smart power. Module load (not shown), in this case, smart The fall time of the output voltage of the power module is about 0.06 μS (shown as curve CT3 in Figure 5). Differently, when the operating voltage of the input terminal of the buffer circuit 400 is operated at a small supply voltage Vcc, the output current of the high-voltage constant current buffer circuit CA can be amplified by the acceleration current generated by the current-acceleration circuit CS, and then The output current Iout of the snubber circuit 400 drives the load of the smart power module. In this case, the fall time of the output voltage of the smart power module is shortened to about 0.04 μS (as shown by the curve CT4 in FIG. 5).

In addition, in this embodiment, the second NMOS transistor system in the current acceleration circuit CS is designed as a high voltage NMOS transistor, and the sixth PMOS transistor MP6 and the seventh in the parallel current mirror PM. The PMOS transistor MP7 is designed as a low voltage PMOS transistor and a high voltage PMOS transistor, respectively. The reason why the seventh PMOS transistor MP7 in the parallel current mirror PM is designed as a high voltage PMOS transistor is because the high voltage PMOS transistor can withstand a large voltage, so that even if the buffer circuit operates at a large The supply voltage and current acceleration circuit CS will not damage 400.

[Possible effects of the examples]

In summary, the snubber circuit provided by the present invention can operate over a wide range of operating voltages, such as 4.5 volts to 30 volts, and has at least the following advantages: First, when applied to a smart power module for outputting current When driving the load of the smart power module, even if operating over a wide range of operating voltages, the snubber circuit provided by the present invention can stably provide a low output current to prevent the load of the smart power module from being overdriven. The transmission delay of the output of the smart power module.

In addition, the snubber circuit provided by the present invention is also provided with a current accelerating circuit. When the snubber circuit operates at a small supply voltage, the output current of the high voltage constant current snubber circuit is first amplified (ie, the acceleration current generated by the current accelerating circuit is added), and then used as the output current output of the snubber circuit to drive the wisdom. The load of the power module. This approach can shorten the fall time of the output voltage of the smart power module.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

Claims (9)

A buffer circuit is operated at an operating voltage, and the operating voltage is received by an input end of the buffer circuit, wherein the operating voltage is controlled in a voltage interval, the buffer circuit comprises: a high voltage constant current buffer circuit, comprising: a first a PMOS transistor and a first NMOS transistor, a source of the first NMOS transistor is grounded, and a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor; a second PMOS a transistor, a source of the second PMOS transistor is connected to an input end of the buffer circuit, and a drain of the second PMOS transistor is connected to a source of the first PMOS transistor; and a series current mirror The input end of the series current mirror is connected to the input end of the buffer circuit, and the output end of the series current mirror is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor And a current accelerating circuit connected to the high voltage constant current buffer circuit and a pulse generator to receive a switching signal of the pulse generator; wherein the second PMOS transistor of the high voltage constant current buffer circuit is a low voltage PMOS transistor The first PMOS transistor of the high voltage constant current buffer circuit is a high voltage PMOS transistor, and the first NMOS transistor of the high voltage constant current buffer circuit is a high voltage NMOS transistor to reduce the buffer circuit. The output current changes due to the change of the operating voltage; wherein, when one of the pulse generators inputs the signal from a low potential to a high potential, the pulse generator outputs a narrow pulse signal to drive one of the current acceleration circuits The PMOS current mirror directly outputs a current, so that the current accelerating circuit amplifies the output current of the received high voltage constant current buffer circuit and outputs the current. The snubber circuit of claim 1, wherein the series current mirror comprises: a fourth PMOS transistor and a fifth PMOS transistor, the source of the fourth PMOS transistor is an input end of the series current mirror, and the fifth PMOS transistor is substantially the output of the series current mirror The drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, and the gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor and further connected to the gate The output of the series current mirror. The snubber circuit of claim 2, wherein the fourth PMOS transistor of the series current mirror is a low voltage PMOS transistor, and the fifth PMOS transistor is a high voltage PMOS transistor. The snubber circuit of claim 3, further comprising: a resistor connected to the output end of the series current mirror, the gate of the first PMOS transistor and the gate of the second PMOS transistor pole. The snubber circuit of claim 1, wherein the current accelerating circuit comprises: a PMOS current mirror; a second NMOS transistor, wherein a drain of the second NMOS transistor is connected to the parallel current mirror, and a gate of the second NMOS transistor is connected to the pulse generator; and a third NMOS transistor, a drain of the third NMOS transistor is connected to a source of the second NMOS transistor, and the third NMOS is The source of the crystal is grounded, and the gate of the third NMOS transistor receives a buffer bias; wherein the pulse generator outputs the narrow pulse signal when the input signal of the pulse generator changes from a low potential to a high potential The second NMOS transistor is turned on, so that the third NMOS transistor provides an accelerating current to the PMOS current mirror to amplify and output the output current of the high voltage constant current buffer circuit received by the current accelerating circuit. The snubber circuit of claim 5, wherein the second NMOS transistor is a high voltage NMOS transistor. The buffer circuit of claim 5, wherein the PMOS current mirror comprises two The gate is connected to one of the sixth PMOS transistor and the seventh PMOS transistor, and the source of the sixth PMOS transistor and the seventh PMOS transistor are both connected to the input end of the buffer circuit, and the sixth PMOS The transistor and the two gates and the two drains of the seventh PMOS transistor are further connected to the drain of the second NMOS transistor. The snubber circuit of claim 5, wherein the sixth PMOS transistor is a low voltage PMOS transistor, and the seventh PMOS transistor is a high voltage PMOS transistor. The snubber circuit of claim 1, wherein the voltage interval is 4.5V to 30V.