JPH06259965A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten an access time, and to normally send out an address signal by directly inputting a control signal to be inputted, and using it as a control signal to an address input circuit. CONSTITUTION:As a control signal to an address input circuit 105, a control signal D to be inputted to a control input circuit 106, is used, and it is directly inputted to the circuit 105. The signal D is outputted as an internal control signal F through inverters 103 and 104, and is sent out to the internal circuit of a semiconductor integrated circuit. In the circuit 105, the control signal D to be inputted to the circuit 106, is directly inputted to a NOR circuit 101, and a logical add to an address signal A, is taken. Its output B is outputted as an internal address signal C through an inverter 102, and is sent out to the internal circuit of a semiconductor integrated circuit. Then, the signal D is directly inputted to the circuit 105, and since it is not sent through the circuit 106, a delay time is eliminated, an access time to be executed through a control signal, is shortened and the signal C is normally sent out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, an input circuit thereof includes a NOR circuit 201 and an inverter 202 which function as an input first stage circuit in response to an input of an address signal A, as shown in FIG. Address input circuit 205, and inverter 203 and inverter 2 that function as an input first stage circuit in response to the input of control signal D
The NOR circuit 20 included in the address input circuit 205 is configured by including the control signal input circuit 206 including 04.
1 is an input first stage circuit, the transistor ratio is adjusted so that the address signal A operates from the TTL input voltage to the CMOS input voltage, and the inverter 203 included in the control signal input circuit 206 is also the input first stage circuit. The transistor ratio is adjusted so that the control signal D operates from the TTL input voltage to the CMOS input voltage.

In FIG. 2, the control signal D is the inverter 2
It is output as an internal control signal F via 03 and 204 and sent to the internal circuit of the semiconductor integrated circuit. The internal control signal F is simultaneously input to the address input circuit 205 as a control signal for the address input circuit 205, and the NOR circuit 2 in the address input circuit 205 is also input.
01, the logical sum is obtained with the address signal A, and the output B is output as the internal address signal C via the inverter 202 and sent out into the semiconductor integrated circuit.

[0004]

In the input circuit of the conventional semiconductor integrated circuit described above, the control signal input circuit 2 is used as the control signal for the address input circuit 205.
At 06, the internal control signal F is input to the input first stage circuit whose transistor ratio is adjusted, and its output is subjected to waveform shaping and is used. When the access is performed by the control signal, the control signal is The transient delay amount in the input first stage circuit of the input circuit 206 is large, and due to the delay of the internal control signal F obtained by shaping the output of the input circuit 206, it takes time for the address input circuit 205 to determine the internal address. There is a drawback that the delay of the access time becomes a large value as a ratio to the access time of the entire semiconductor integrated circuit.

[0005]

According to the semiconductor integrated circuit of the present invention, the input address signal is C from the TTL input voltage.
An address input circuit having an input first stage whose transistor ratio is adjusted to operate up to a MOS input voltage, and an input first stage whose transistor ratio is adjusted so that an input control signal operates from a TTL input voltage to a CMOS input voltage. In a semiconductor integrated circuit having as an input circuit a control signal input circuit having a control signal input circuit, a control signal input to the control signal input circuit is directly input and used as a control signal for the address input circuit.

The address input circuit is composed of a NOR circuit that outputs a logical sum of the address signal and the control signal and an inverter that inverts and outputs the output of the NOR circuit. The control signal input circuit may include a first inverter that inverts and outputs the control signal, and a second inverter that inverts and outputs the output of the first inverter.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. As shown in FIG. 1, the present embodiment corresponds to the input of the address signal A and NO that functions as an input first stage circuit.
An address input circuit 105 including an R circuit 101 and an inverter 102, and a control signal input circuit 106 including an inverter 103 and an inverter 104, which function as an input first stage circuit, corresponding to the input of a control signal D, are configured. As in the case of the conventional example, the NOR circuit 101 included in the address input circuit 105 has the transistor ratio adjusted so that the address signal A operates from the TTL input voltage to the CMOS input voltage as an input first stage circuit. Similarly, the inverter 103 included in the control signal input circuit 106 is also an input first stage circuit, and the transistor ratio is adjusted so that the control signal D operates from the TTL input voltage to the CMOS input voltage. The difference from the conventional example of this embodiment is that the control signal D input to the control input circuit 106 is used as the control signal for the address input circuit 105 and is directly input to the address input circuit 105.

In FIG. 1, the control signal D is an inverter 1
It is output as an internal control signal F via 03 and 104 and sent to the internal circuit of the semiconductor integrated circuit. The operation itself of the control signal input circuit 106 is similar to that of the conventional example. On the other hand, in the address input circuit 105, the control signal D input to the control input circuit 106 is directly input to the NOR circuit 101 to be ORed with the address signal A, and its output B is passed through the inverter 102. It is output as an internal address signal C and sent to the internal circuit of the semiconductor integrated circuit.

As described above, in the present invention, the control input circuit 1 does not use the internal control signal F as the control signal for the address input circuit 105 unlike the conventional example.
Control signal D input to the direct address input circuit 1
Since it is input to the control signal input circuit 05, the time delay due to passing through the control signal input circuit 106 is eliminated, the access time performed via the control signal is shortened, and the internal address signal C is normally transmitted to the semiconductor integrated circuit. It is sent to the internal circuit.

[0011]

As described above, the present invention is applied to a semiconductor integrated circuit including an address input circuit and a control signal input circuit, and the control signal input circuit is used as a control signal for accessing the address input circuit. By directly inputting and using the control signal to be input to, there is an effect that the access time can be shortened and the internal address signal can be normally sent to the internal circuit of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 101, 201 NOR circuit 102-104, 202-204 Inverter 105, 205 Address input circuit 106, 206 Control signal input circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8941-5J H03K 19/00 101 A

Claims (2)

[Claims] 1. An address input circuit having an input first stage whose transistor ratio is adjusted so that an input address signal operates from a TTL input voltage to a CMOS input voltage, and an input control signal is input from a TTL input voltage. C
In a semiconductor integrated circuit having, as an input circuit, a control signal input circuit having an input initial stage whose transistor ratio is adjusted to operate up to a MOS input voltage, a control signal for the address input circuit is input to the control signal input circuit. Integrated circuit characterized by directly inputting and using a controlled signal. 2. The NOR circuit, wherein the address input circuit calculates a logical sum of the address signal and the control signal and outputs the logical sum.
Circuit and an inverter that inverts and outputs the output of the NOR circuit. The control signal input circuit outputs a first inverter that inverts and outputs the control signal and an output of the first inverter. The semiconductor integrated circuit according to claim 1, which is configured by a second inverter that inverts and outputs.