JPH06252753A - Pll frequency synthesizer - Google Patents
Pll frequency synthesizerInfo
- Publication number
- JPH06252753A JPH06252753A JP5039154A JP3915493A JPH06252753A JP H06252753 A JPH06252753 A JP H06252753A JP 5039154 A JP5039154 A JP 5039154A JP 3915493 A JP3915493 A JP 3915493A JP H06252753 A JPH06252753 A JP H06252753A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- power supply
- output
- voltage output
- charge pump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
- H03L7/0898—Details of the current generators the source or sink current values being variable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＰＬＬ周波数シンセサ
イザに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer.
【０００２】[0002]
【従来の技術】図２は従来のＰＬＬ周波数シンセサイザ
の概略を示すもので、３は電圧制御発振器、４はプログ
ラマブルカウンタ、５は基準信号発生器、６は基準信号
分周器、７は位相比較器、８はチャージポンプ、９はル
ープフィルタ、１０はＰＬＬ周波数シンセサイザの発振
周波数を設定するＭＰＵである。2. Description of the Related Art FIG. 2 schematically shows a conventional PLL frequency synthesizer. 3 is a voltage controlled oscillator, 4 is a programmable counter, 5 is a reference signal generator, 6 is a reference signal frequency divider, and 7 is a phase comparison. , 8 is a charge pump, 9 is a loop filter, and 10 is an MPU for setting the oscillation frequency of the PLL frequency synthesizer.
【０００３】次に、従来のＰＬＬ周波数シンセサイザの
動作を説明する。まず、ＭＰＵ１０が、基準信号発生器
５の発振周波数と発振させたい周波数との間隔から基準
信号の分周比Ｒを決定し、この分周比Ｒを基準信号分周
器６に設定する。ここで、基準信号分周器６の出力周波
数をｆｒとする。ＭＰＵ１０が、発振させたい周波数Ｎ
・ｆｒから電圧制御発振器３の出力の分周数Ｎを決定す
る。ＭＰＵ１０は決定した分周数Ｎをプログラマブルカ
ウンタ４に設定する。Next, the operation of the conventional PLL frequency synthesizer will be described. First, the MPU 10 determines the frequency division ratio R of the reference signal from the interval between the oscillation frequency of the reference signal generator 5 and the frequency to be oscillated, and sets this frequency division ratio R in the reference signal frequency divider 6. Here, the output frequency of the reference signal frequency divider 6 is fr. The frequency N that the MPU 10 wants to oscillate
The frequency division number N of the output of the voltage controlled oscillator 3 is determined from fr. The MPU 10 sets the determined frequency division number N in the programmable counter 4.
【０００４】次に、電圧制御発振器３の出力ｆｖはプロ
グラマブルカウンタ４により１／Ｎに分周されｆｖ／Ｎ
となって出力される。ｆｒとｆｖ／Ｎの位相と周波数を
位相比較器７により比較する。位相比較器７の出力でチ
ャージポンプ８を働かせば電圧制御発振器３を制御する
のに必要な直流電圧が得られる。チャージポンプ８の出
力には位相比較器７で比較された周波数成分や不必要な
雑音が含まれているので、ループフィルタ９によりそれ
らを除去し電圧制御発振器３に出力する。電圧制御発振
器３はループフィルタ９の出力の直流電圧に対応する周
波数を出力する。これをｆｒとｆｖ／Ｎの位相と周波数
が同じになるまで繰り返し、最終的に電圧制御発振器３
の出力は発振させたい周波数であるＮ・ｆｒとなる。Next, the output fv of the voltage controlled oscillator 3 is divided into 1 / N by the programmable counter 4 and fv / N.
Will be output. The phase and frequency of fr and fv / N are compared by the phase comparator 7. If the charge pump 8 is operated by the output of the phase comparator 7, the DC voltage required to control the voltage controlled oscillator 3 can be obtained. Since the output of the charge pump 8 includes the frequency components compared with the phase comparator 7 and unnecessary noise, they are removed by the loop filter 9 and output to the voltage controlled oscillator 3. The voltage controlled oscillator 3 outputs a frequency corresponding to the DC voltage output from the loop filter 9. This is repeated until the phase and frequency of fr and fv / N become the same, and finally the voltage controlled oscillator 3
Output is N · fr which is the frequency to be oscillated.
【０００５】また、このときの過渡応答特性としては、
ループフィルタ９を図３に示すように完全積分ループフ
ィルタとすると、閉ループ伝達関数Ｈ（Ｓ）は式１のよ
うになる。The transient response characteristic at this time is as follows.
Assuming that the loop filter 9 is a perfect integral loop filter as shown in FIG. 3, the closed loop transfer function H (S) is as shown in Expression 1.
【０００６】 Ｈ（Ｓ）＝Ｋ・（Ｓ＋ａ）／（Ｓ2 ＋Ｋ・Ｓ＋ａ・Ｋ）・・・ 式１ そのため、全体のループゲインをＫとして、応答の減衰
率ζ，固有周波数ωは式２および式３のようになる。H (S) = K (S + a) / (S 2 + KS + aK) Equation 1 Therefore, assuming that the overall loop gain is K, the damping ratio ζ of the response and the natural frequency ω are Equation 2 And it becomes like Formula 3.
【０００７】 ζ＝（Ｋ／ａ）1/2 ／２・・・ 式２ ω＝（ａ・Ｋ）1/2 ・・・ 式３ ここで、式１，式２，式３のａは、ループフィルタ９の
増幅器１３の利得をＡとして式４で表されるものであ
る。Ζ = (K / a) 1/2 / 2 Equation 2 ω = (a · K) 1/2 Equation 3 where a in Equation 1, Equation 2, and Equation 3 is The gain of the amplifier 13 of the loop filter 9 is represented by Equation 4 as A.
【０００８】ａ＝１／（Ｒ2 ・Ｃ）・・・ 式４A = 1 / (R 2 · C) ... Equation 4
【０００９】[0009]
【発明が解決しようとする課題】このように従来の構成
では、一度、閉ループを組んでしまうと、そのままで
は、電圧制御発振器３が目的周波数に切り替わる時間
は、基準信号発生器５の周波数と目的周波数との間隔の
みに依存し任意に調節することが出来ず、周波数の切り
替え時間を自由に制御できない。そのため、基準信号発
生器５の周波数と目的周波数との間隔によっては周波数
の切り替え時間が長くなるという問題点がある。また、
周波数切り替えを高速化するためには、周波数の異なる
複数のＰＬＬ周波数シンセサイザを使用してシンセサイ
ザ自体をスイッチで切換えるか、半導体製造プロセスか
ら変えなければならないという問題点がある。As described above, in the conventional configuration, once the closed loop is formed, the time when the voltage controlled oscillator 3 is switched to the target frequency is the frequency of the reference signal generator 5 and the target frequency. It cannot be arbitrarily adjusted because it depends only on the interval with the frequency, and the frequency switching time cannot be freely controlled. Therefore, there is a problem that the frequency switching time becomes long depending on the interval between the frequency of the reference signal generator 5 and the target frequency. Also,
In order to speed up the frequency switching, there is a problem that the synthesizer itself must be switched by using a plurality of PLL frequency synthesizers having different frequencies or the semiconductor manufacturing process must be changed.
【００１０】本発明は、周波数の異なる複数のＰＬＬ周
波数シンセサイザをスイッチで切り換えたり、半導体製
造プロセスを変えることなく、目的周波数への切り替え
が従来にくらべて高速化できるＰＬＬ周波数シンセサイ
ザを提供することを目的とする。The present invention provides a PLL frequency synthesizer that can switch to a target frequency faster than before without changing a plurality of PLL frequency synthesizers having different frequencies with a switch or changing a semiconductor manufacturing process. To aim.
【００１１】[0011]
【課題を解決するための手段】本発明のＰＬＬ周波数シ
ンセサイザは、可変発振器の位相と基準信号発生器の位
相との比較結果に基づいて変化するチャージポンプの出
力により前記可変発振器の位相を前記基準信号発生器の
位相に同期させ、前記可変発振器から目的周波数の信号
を得るＰＬＬ周波数シンセサイザにおいて、チャージポ
ンプの専用の電源と、前記電源の電圧を目的周波数の変
化に応じて制御する制御装置とを設けたことを特徴とす
る。In a PLL frequency synthesizer of the present invention, the phase of the variable oscillator is set to the reference by the output of a charge pump that changes based on the comparison result of the phase of the variable oscillator and the phase of the reference signal generator. In a PLL frequency synthesizer that obtains a signal of a target frequency from the variable oscillator in synchronization with the phase of a signal generator, a dedicated power supply for a charge pump and a control device that controls the voltage of the power supply according to the change in the target frequency. It is characterized by being provided.
【００１２】[0012]
【作用】上記の構成によると、チャージポンプに専用の
電源を接続し、これを制御する制御装置を設けて、可変
発振器の周波数を目的周波数に切り替える際に、制御装
置で目的周波数の変化に応じて前記電源の電圧を制御す
る。According to the above construction, when the charge pump is connected to a dedicated power source and a control device for controlling the power source is provided so that the frequency of the variable oscillator is switched to the target frequency, the control device responds to changes in the target frequency. Control the voltage of the power supply.
【００１３】[0013]
【実施例】以下、本発明の一実施例を図１に基づいて説
明する。なお、従来例を示す図２および図３と同様の作
用をなすものは同一の符号をつけて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. It should be noted that components having the same operations as those of the conventional example shown in FIGS.
【００１４】図１において、可変発振器としての電圧制
御発振器３，プログラマブルカウンタ４，基準信号発生
器５，基準信号分周器６，位相比較器７，チャージポン
プ８，ループフィルタ９，ＭＰＵ１０は従来例と同様で
あり、１１はチャージポンプ８の専用の電源、１２は目
的周波数の上下に応じて電源１１の電圧を制御する制御
装置である。In FIG. 1, a voltage controlled oscillator 3 as a variable oscillator 3, a programmable counter 4, a reference signal generator 5, a reference signal frequency divider 6, a phase comparator 7, a charge pump 8, a loop filter 9 and a MPU 10 are conventional examples. 11 is a power source dedicated to the charge pump 8, and 12 is a control device for controlling the voltage of the power source 11 depending on whether the target frequency is higher or lower.
【００１５】つぎに、本実施例のＰＬＬ周波数シンセサ
イザの動作を説明する。まず、チャージポンプ８の専用
の電源１１の出力は、高電圧側がＶｃｃボルトで低電圧
側が０ボルトであるものとする。ＭＰＵ１０が基準信号
発生器５の発振周波数と目的周波数である発振させたい
周波数との間隔から基準信号の分周比Ｒを決定し基準信
号分周器６に設定する。ここでは、基準信号分周器６の
出力周波数をｆｒとする。ＭＰＵ１０が発振したい周波
数Ｎ・ｆｒから電圧制御発振器３の出力の分周数Ｎを決
定する。ＭＰＵ１０は決定した分周数Ｎをプログラマブ
ルカウンタ４と制御装置１２に設定する。Next, the operation of the PLL frequency synthesizer of this embodiment will be described. First, it is assumed that the output of the power supply 11 dedicated to the charge pump 8 is Vcc volt on the high voltage side and 0 volt on the low voltage side. The MPU 10 determines the frequency division ratio R of the reference signal from the interval between the oscillation frequency of the reference signal generator 5 and the desired frequency to be oscillated and sets it in the reference signal frequency divider 6. Here, the output frequency of the reference signal frequency divider 6 is fr. The frequency division number N of the output of the voltage controlled oscillator 3 is determined from the frequency N · fr at which the MPU 10 wants to oscillate. The MPU 10 sets the determined frequency division number N in the programmable counter 4 and the control device 12.
【００１６】また、制御装置１２は、前回の分周数Ｎの
設定を記憶していて、ＭＰＵ１０から新しく分周数Ｎが
設定されると同時に前回より高い周波数が設定されたの
か低い周波数が設定されたのかを判断し、電源１１を制
御する。もし、前回より高い周波数が設定されたのであ
れば、電源１１の出力の低電圧側は０ボルトのままで高
電圧側を２・Ｖｃｃボルトにする。逆に、低い周波数が
設定されたのであれば、電源１１の出力の高電圧側はＶ
ｃｃボルトのままで、低電圧側を−Ｖｃｃボルトにす
る。これにより、閉ループにおけるループゲインが２倍
に増加する。Further, the control device 12 stores the previous setting of the frequency division number N, and at the same time when the frequency division number N is newly set from the MPU 10, at the same time as the higher frequency than the last time is set or the lower frequency is set. The power supply 11 is controlled by determining whether or not the power supply has been performed. If a higher frequency than the last time is set, the low voltage side of the output of the power supply 11 remains at 0 volt and the high voltage side is set to 2 · Vcc volt. On the contrary, if the low frequency is set, the high voltage side of the output of the power supply 11 is V
The low voltage side is set to -Vcc volt with the cc volt remaining. As a result, the loop gain in the closed loop is doubled.
【００１７】次に、電圧制御発振器３の出力ｆｖはプロ
グラマブルカウンタ４により１／Ｎに分周されｆｖ／Ｎ
となってプログラマブルカウンタ４から出力される。ｆ
ｒとｆｖ／Ｎの位相と周波数を位相比較器７にて比較す
る。位相比較器７の出力でチャージポンプ８を働かせば
電圧制御発振器３を制御するのに必要な直流電圧が得ら
れる。チャージポンプ８の出力には比較周波数成分や不
必要な雑音が含まれているので、ループフィルタ９にて
それらを除去し電圧制御発振器３に出力する。電圧制御
発振器３はループフィルタ９の出力の直流電圧に対応す
る周波数を出力する。これをｆｒとｆｖ／Ｎの位相と周
波数が同じになるまで繰り返し、最終的に電圧制御発振
器３の出力は目的の周波数であるＮ・ｆｒとなる。電圧
制御発振器３の出力がＮ・ｆｒになれば、制御装置１２
は電源１１の出力を、高電圧側をＶｃｃボルト、低電圧
側を０ボルトに戻す。Next, the output fv of the voltage controlled oscillator 3 is divided into 1 / N by the programmable counter 4 and fv / N.
Is output from the programmable counter 4. f
The phase and frequency of r and fv / N are compared by the phase comparator 7. If the charge pump 8 is operated by the output of the phase comparator 7, the DC voltage required to control the voltage controlled oscillator 3 can be obtained. Since the output of the charge pump 8 includes comparison frequency components and unnecessary noise, these are removed by the loop filter 9 and output to the voltage controlled oscillator 3. The voltage controlled oscillator 3 outputs a frequency corresponding to the DC voltage output from the loop filter 9. This is repeated until the phase and frequency of fr and fv / N become the same, and finally the output of the voltage controlled oscillator 3 becomes the target frequency of N · fr. If the output of the voltage controlled oscillator 3 becomes N · fr, the controller 12
Returns the output of the power supply 11 to Vcc volts on the high voltage side and 0 volts on the low voltage side.
【００１８】この構成により、電圧制御発振器３の目的
周波数への切り替えが従来に比べて高速化できる。With this configuration, the switching of the voltage controlled oscillator 3 to the target frequency can be made faster than in the conventional case.
【００１９】[0019]
【発明の効果】本発明の構成によれば、チャージポンプ
に専用の電源を接続し、これを制御する制御装置を設け
たので、可変発振器の周波数を目的周波数に切り替える
際に、制御装置で目的周波数の変化に応じて前記電源の
電圧が制御できる。そのため、可変発振器の目的周波数
への切り替えの速度が向上する。According to the structure of the present invention, the charge pump is connected to the dedicated power supply and the control device for controlling the power supply is provided. Therefore, when the frequency of the variable oscillator is switched to the target frequency, The voltage of the power supply can be controlled according to the change in frequency. Therefore, the speed of switching the variable oscillator to the target frequency is improved.
【図１】本発明の一実施例のＰＬＬ周波数シンセサイザ
の構成図FIG. 1 is a configuration diagram of a PLL frequency synthesizer according to an embodiment of the present invention.
【図２】従来例のＰＬＬ周波数シンセサイザの構成図FIG. 2 is a block diagram of a conventional PLL frequency synthesizer.
【図３】ループフィルタの一例の完全積分ループフィル
タの構成図FIG. 3 is a configuration diagram of a perfect integral loop filter as an example of a loop filter.
３ 可変発振器（電圧制御発振器） ５ 基準信号発生器 ８ チャージポンプ １１ 電源 １２ 制御装置 3 Variable Oscillator (Voltage Controlled Oscillator) 5 Reference Signal Generator 8 Charge Pump 11 Power Supply 12 Controller
Claims (1)
相との比較結果に基づいて変化するチャージポンプの出
力により前記可変発振器の位相を前記基準信号発生器の
位相に同期させ、前記可変発振器から目的周波数の信号
を得るＰＬＬ周波数シンセサイザにおいて、チャージポ
ンプの専用の電源と、前記電源の電圧を目的周波数の変
化に応じて制御する制御装置とを設けたＰＬＬ周波数シ
ンセサイザ。1. The variable oscillator is synchronized with the phase of the reference signal generator by the output of a charge pump that changes based on the result of comparison between the phase of the variable oscillator and the phase of the reference signal generator. A PLL frequency synthesizer for obtaining a signal of a target frequency from a PLL frequency synthesizer provided with a dedicated power supply for a charge pump and a control device for controlling the voltage of the power supply according to a change in the target frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5039154A JPH06252753A (en) | 1993-03-01 | 1993-03-01 | Pll frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5039154A JPH06252753A (en) | 1993-03-01 | 1993-03-01 | Pll frequency synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06252753A true JPH06252753A (en) | 1994-09-09 |
Family
ID=12545196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5039154A Pending JPH06252753A (en) | 1993-03-01 | 1993-03-01 | Pll frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06252753A (en) |
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1993
- 1993-03-01 JP JP5039154A patent/JPH06252753A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59137819U (en) * | 1983-03-07 | 1984-09-14 | 河西工業株式会社 | automotive door trim |
| JPS61133417U (en) * | 1985-02-12 | 1986-08-20 | ||
| JPS624419U (en) * | 1985-06-26 | 1987-01-12 | ||
| JPS63284051A (en) * | 1987-04-07 | 1988-11-21 | フィアット・アウト・ソシエタ・ペル・アチオーニ | Molded part for indoor trimming of automobile and manufacture thereof |
| JPH0191621U (en) * | 1987-12-10 | 1989-06-15 | ||
| JPH01190531A (en) * | 1988-01-25 | 1989-07-31 | Daihatsu Motor Co Ltd | Ornamental structure of door trim for automobile |
| JPH0316514U (en) * | 1989-06-30 | 1991-02-19 | ||
| JPH03200420A (en) * | 1989-12-04 | 1991-09-02 | General Motors Corp <Gm> | Door for rolling stock |
| JPH0442451U (en) * | 1990-08-10 | 1992-04-10 | ||
| JPH0674426U (en) * | 1993-03-31 | 1994-10-21 | 河西工業株式会社 | Interior parts for automobiles |
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